In this paper we present a many-valued logic programming, based on reinterpreted Belnap's 4-valued bilattice: we introduce the new semantics for a 4-valued implication by relative pseudo-complement, used for intuitionistic logics. This kind of logic programming is particularly useful for data integration with possibly incomplete and inconsistent information. We define an ontological encapsulation of the epistemic many-valued logic programs with negation, based on this bilattice, into 2-valued meta logic programs. Obtained 2-valued logic semantically reflects original epistemic many-valued logic, and can be used in order to define many-valued logic entailment and inference closure for many-valued truth assignments.
{"title":"Many-valued intuitionistic implication and inference closure in a bilattice-based logic","authors":"Z. Majkic","doi":"10.1109/ISMVL.2005.22","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.22","url":null,"abstract":"In this paper we present a many-valued logic programming, based on reinterpreted Belnap's 4-valued bilattice: we introduce the new semantics for a 4-valued implication by relative pseudo-complement, used for intuitionistic logics. This kind of logic programming is particularly useful for data integration with possibly incomplete and inconsistent information. We define an ontological encapsulation of the epistemic many-valued logic programs with negation, based on this bilattice, into 2-valued meta logic programs. Obtained 2-valued logic semantically reflects original epistemic many-valued logic, and can be used in order to define many-valued logic entailment and inference closure for many-valued truth assignments.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115372691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we apply the bi-decomposition on multivalued functions and restrict the decomposition to MIN and MAX gates. It is known from (A. Mishchenko et al., 2001) that the MIN and MAX bi-decomposition leads in general to small multi-level circuits, well understandable for humans. Unfortunately, there does not exist a MIN or MAX bi-decomposition for each multi-valued function. In this paper we close this gap by the MAX-MIN multi-decomposition. Experimental results show that our complete decomposition of a set of benchmarks requires approximately the same sum of gates and literals as the known incomplete approach and the number of logic levels could even be reduced in average by 20 percent.
本文将双分解应用于多值函数，并将分解限制在最小门和最大门上。从(A. Mishchenko et al.， 2001)可知，MIN和MAX双分解通常导致小型多级电路，对人类来说是很容易理解的。不幸的是，对于每个多值函数，不存在最小或最大双分解。在本文中，我们通过MAX-MIN多重分解来弥补这一差距。实验结果表明，我们对一组基准的完全分解所需的门和字面量的总和与已知的不完全方法大致相同，逻辑级别的数量甚至可以平均减少20%。
{"title":"Complete bi-decomposition of multiple-valued functions using MIN and MAX gates","authors":"B. Steinbach, C. Lang","doi":"10.1109/ISMVL.2005.14","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.14","url":null,"abstract":"In this paper we apply the bi-decomposition on multivalued functions and restrict the decomposition to MIN and MAX gates. It is known from (A. Mishchenko et al., 2001) that the MIN and MAX bi-decomposition leads in general to small multi-level circuits, well understandable for humans. Unfortunately, there does not exist a MIN or MAX bi-decomposition for each multi-valued function. In this paper we close this gap by the MAX-MIN multi-decomposition. Experimental results show that our complete decomposition of a set of benchmarks requires approximately the same sum of gates and literals as the known incomplete approach and the number of logic levels could even be reduced in average by 20 percent.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121104950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As logic device sizes shrink towards the nanometer scale, a number of important physical limits threaten to soon halt further improvements in computer performance per unit cost. However, the near-term limits are not truly fundamental, and may be avoided by making radical changes to the physical and logical architecture of computers. In particular, certain assumed limits to the energy efficiency of computers have never been rigorously proven, and may be circumvented using physical mechanisms that recover and reuse signal energies with efficiency approaching 100%. However, this concept, called reversible computing, imposes tight constraints on the design of the machine at all levels from physics to algorithms. We review the physical and architectural requirements that must be met if real machines are to break through the barriers preventing further progress, and approach the true fundamental physical limits to computing.
{"title":"Approaching the physical limits of computing","authors":"M. Frank","doi":"10.1109/ISMVL.2005.9","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.9","url":null,"abstract":"As logic device sizes shrink towards the nanometer scale, a number of important physical limits threaten to soon halt further improvements in computer performance per unit cost. However, the near-term limits are not truly fundamental, and may be avoided by making radical changes to the physical and logical architecture of computers. In particular, certain assumed limits to the energy efficiency of computers have never been rigorously proven, and may be circumvented using physical mechanisms that recover and reuse signal energies with efficiency approaching 100%. However, this concept, called reversible computing, imposes tight constraints on the design of the machine at all levels from physics to algorithms. We review the physical and architectural requirements that must be met if real machines are to break through the barriers preventing further progress, and approach the true fundamental physical limits to computing.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"86 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127993160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A packet data transfer scheme is introduced for intra-chip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.
{"title":"Multiple-valued VLSI architecture for intra-chip packet data transfer","authors":"Tomoaki Hasegawa, Y. Homma, M. Kameyama","doi":"10.1109/ISMVL.2005.31","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.31","url":null,"abstract":"A packet data transfer scheme is introduced for intra-chip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122763052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, M. Lukac, Jeff Allen, Stefan Gebauer
The paper presents a new application of decomposition of multiple-valued relations. We developed a theatre of interactive humanoid robots, Hahoe KAIST Robot Theatre. Version 2 includes three full body robots, equipped with vision, speech recognition, speech synthesis and natural language dialog based on machine learning abilities. The needs for this kind of project result from several research questions, especially in emotional computing and gesture generation, but the project has also educational, artistic, and entertainment values. It is a testbed to verify and integrate several algorithms in the domain of computational intelligence. Machine learning methods based on multiple-valued logic are used for representation of knowledge and machine learning from examples.
{"title":"Hahoe KAIST Robot Theatre: learning rules of interactive robot behavior as a multiple-valued logic synthesis problem","authors":"M. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, M. Lukac, Jeff Allen, Stefan Gebauer","doi":"10.1109/ISMVL.2005.18","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.18","url":null,"abstract":"The paper presents a new application of decomposition of multiple-valued relations. We developed a theatre of interactive humanoid robots, Hahoe KAIST Robot Theatre. Version 2 includes three full body robots, equipped with vision, speech recognition, speech synthesis and natural language dialog based on machine learning abilities. The needs for this kind of project result from several research questions, especially in emotional computing and gesture generation, but the project has also educational, artistic, and entertainment values. It is a testbed to verify and integrate several algorithms in the domain of computational intelligence. Machine learning methods based on multiple-valued logic are used for representation of knowledge and machine learning from examples.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"49 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120916643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Karhunen-Loeve (KL) transform of a discrete multiple-valued logic function is studied with respect to algebraic graph theory. The spectrum of a Cayley graph defined over the symmetry group is observed to be equivalent to the KL spectrum of a discrete function when the Cayley graph is generated using that function. It is also observed that the autocorrelation of the discrete function using the symmetry group operator is equivalent to the adjacency matrix of the Cayley graph. In addition to the theoretical interests, the KL spectrum of a discrete multiple-valued logic function can have applications in compact function representation and the determination of function estimates with a reduced support set. Example computations are shown in addition to the presentation of the mathematical properties.
{"title":"The Karhunen-Loeve transform of discrete MVL functions","authors":"M. Thornton","doi":"10.1109/ISMVL.2005.48","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.48","url":null,"abstract":"The Karhunen-Loeve (KL) transform of a discrete multiple-valued logic function is studied with respect to algebraic graph theory. The spectrum of a Cayley graph defined over the symmetry group is observed to be equivalent to the KL spectrum of a discrete function when the Cayley graph is generated using that function. It is also observed that the autocorrelation of the discrete function using the symmetry group operator is equivalent to the adjacency matrix of the Cayley graph. In addition to the theoretical interests, the KL spectrum of a discrete multiple-valued logic function can have applications in compact function representation and the determination of function estimates with a reduced support set. Example computations are shown in addition to the presentation of the mathematical properties.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"455 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127608903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Detection methods for a class of symmetries called antisymmetries are presented. Work in (J. E. Rice et al., 2002) gives details of these antisymmetries for Boolean logic, while this work extends the concept to multi-valued logic. Preliminary ideas for applications of multi-valued antisymmetries are also discussed.
提出了一类称为反对称的对称的检测方法。在(J. E. Rice et al.， 2002)中的工作给出了布尔逻辑的这些反对称性的细节，而这项工作将概念扩展到多值逻辑。讨论了多值不对称应用的初步思路。
{"title":"A characterization of antisymmetry in Boolean and multi-valued functions","authors":"J. Rice, J. Muzio","doi":"10.1109/ISMVL.2005.1","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.1","url":null,"abstract":"Detection methods for a class of symmetries called antisymmetries are presented. Work in (J. E. Rice et al., 2002) gives details of these antisymmetries for Boolean logic, while this work extends the concept to multi-valued logic. Preliminary ideas for applications of multi-valued antisymmetries are also discussed.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127623682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
When communication is expensive, the important task of testing two binary strings for equality can be achieved by generating relatively short fingerprints of each string and comparing those fingerprints. Quantum fingerprinting, in which the fingerprint is encoded onto qubits (the quantum version of the bit), is significantly less expensive: exponentially better in the case of no shared randomness and potentially perfect for the case of shared entanglement. Single-qubit quantum fingerprinting is feasible, and we have demonstrated its advantages theoretically and experimentally
{"title":"Classical vs Quantum Fingerprinting","authors":"B. Sanders","doi":"10.1109/ISMVL.2005.13","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.13","url":null,"abstract":"When communication is expensive, the important task of testing two binary strings for equality can be achieved by generating relatively short fingerprints of each string and comparing those fingerprints. Quantum fingerprinting, in which the fingerprint is encoded onto qubits (the quantum version of the bit), is significantly less expensive: exponentially better in the case of no shared randomness and potentially perfect for the case of shared entanglement. Single-qubit quantum fingerprinting is feasible, and we have demonstrated its advantages theoretically and experimentally","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116508239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For a monoid M of k-valued unary functions, the centralizer M* of M is the set of k-valued multi-variable functions which commute with every function in M. In this paper, we determine centralizers for all monoids, which contain the symmetric group. For most of such monoids the centralizer turns out to be the least clone. Secondly, we study the monoid M/sub n/ of linear unary functions on 2/sup n/, which emerged from the above research, and characterize its centralizer.
对于一个由k值一元函数组成的monooid M, M的中心化器M*是与M中所有函数交换的k值多变量函数的集合。对于大多数这样的单群，扶正器是最不具克隆性的。其次，我们研究了由上述研究产生的2/sup n/上的线性一元函数的单调函数M/ subn /，并对其扶正器进行了表征。
{"title":"Centralizers of monoids containing the symmetric group","authors":"Hajime Machida, I. Rosenberg","doi":"10.1109/ISMVL.2005.11","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.11","url":null,"abstract":"For a monoid M of k-valued unary functions, the centralizer M* of M is the set of k-valued multi-variable functions which commute with every function in M. In this paper, we determine centralizers for all monoids, which contain the symmetric group. For most of such monoids the centralizer turns out to be the least clone. Secondly, we study the monoid M/sub n/ of linear unary functions on 2/sup n/, which emerged from the above research, and characterize its centralizer.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131589494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Decision diagrams (DDs) are efficient data structures that are frequently used for formal verification, test or synthesis of circuits and systems. The main drawback of the data structure is the potential memory blow-up caused by certain functions. Therefore streaming has been proposed as a technique to efficiently evaluate operations on binary DDs (BDDs). The maximal memory usage can be controlled and therefore calculations can be carried out with a small amount of memory. In this paper we show how streaming can be extended to word-level decision diagrams (WLDDs) and for which type of diagrams streaming is applicable. A detailed description of streaming for multi-terminal BDDs (MTBDDs) is given. Experiments show the efficiency and the small memory needs for operations on MTBDDs.
{"title":"Controlling the memory during manipulation of word-level decision diagrams","authors":"S. Kinder, G. Fey, R. Drechsler","doi":"10.1109/ISMVL.2005.15","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.15","url":null,"abstract":"Decision diagrams (DDs) are efficient data structures that are frequently used for formal verification, test or synthesis of circuits and systems. The main drawback of the data structure is the potential memory blow-up caused by certain functions. Therefore streaming has been proposed as a technique to efficiently evaluate operations on binary DDs (BDDs). The maximal memory usage can be controlled and therefore calculations can be carried out with a small amount of memory. In this paper we show how streaming can be extended to word-level decision diagrams (WLDDs) and for which type of diagrams streaming is applicable. A detailed description of streaming for multi-terminal BDDs (MTBDDs) is given. Experiments show the efficiency and the small memory needs for operations on MTBDDs.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116545531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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