This paper discusses a new algebraic proof method for general sentential logics, which is particularly apt for finitely-many-valued logics and for PC, based on reducing polynomials over finite fields. The method can also be extended to cover certain non-finitely valued logics and non-truth-functional logics as well, provided they can be characterized by two-valued dyadic semantics. The resulting mechanizable proof method introduced here is of interest for automatic proof theory, and seems also to be appropriate for investigating questions on complexity.
{"title":"Polynomial ring calculus for many-valued logics","authors":"W. Carnielli","doi":"10.1109/ISMVL.2005.38","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.38","url":null,"abstract":"This paper discusses a new algebraic proof method for general sentential logics, which is particularly apt for finitely-many-valued logics and for PC, based on reducing polynomials over finite fields. The method can also be extended to cover certain non-finitely valued logics and non-truth-functional logics as well, provided they can be characterized by two-valued dyadic semantics. The resulting mechanizable proof method introduced here is of interest for automatic proof theory, and seems also to be appropriate for investigating questions on complexity.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"62 S285","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132228231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We consider properties of partially ordered sets with residuated t-norm and show that 1. If (X;T,0,1) is a bounded partially ordered set with residuated t-norm T, then (X;*,0/sub X/,1/sub X/) is a bounded BCK-algebra with condition (S); 2. Conversely, if (B;*,0/sub B/,1/sub B/) is a bounded BCK-algebra with (S), then (B;T,0,1) is the bounded partially ordered set with residuated t-norm. This means that the class of all bounded partially ordered sets with residuated t-norm coincides with the class of all bounded BCK-algebras with condition (S). Since the class of these algebras forms a variety, the class of partially ordered sets with residuated t-norm is represented by only equations.
{"title":"Partially ordered set with residuated t-norm","authors":"M. Kondo, M. Kawaguchi","doi":"10.1109/ISMVL.2005.37","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.37","url":null,"abstract":"We consider properties of partially ordered sets with residuated t-norm and show that 1. If (X;T,0,1) is a bounded partially ordered set with residuated t-norm T, then (X;*,0/sub X/,1/sub X/) is a bounded BCK-algebra with condition (S); 2. Conversely, if (B;*,0/sub B/,1/sub B/) is a bounded BCK-algebra with (S), then (B;T,0,1) is the bounded partially ordered set with residuated t-norm. This means that the class of all bounded partially ordered sets with residuated t-norm coincides with the class of all bounded BCK-algebras with condition (S). Since the class of these algebras forms a variety, the class of partially ordered sets with residuated t-norm is represented by only equations.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116215992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a design for signed-digit CMOS (SD-CMOS) basic circuits, such as a driver circuit, an inverter circuit, and a full-adder circuit, and describes a parallel multiplier circuit capable of high-speed operation with a time of about 10 nsec independent of the bit length. The proposed CMOS basic circuits utilize a multi-voltage power supply to enable dynamic operation with pre-charged output terminals at signal level 0 (VDD1). This design methodology is applicable to arithmetic circuits for highly accurate, high-speed processors.
{"title":"Signed-digit CMOS (SD-CMOS) logic circuits with dynamic operation","authors":"H. Fukuda","doi":"10.1109/ISMVL.2005.44","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.44","url":null,"abstract":"This paper proposes a design for signed-digit CMOS (SD-CMOS) basic circuits, such as a driver circuit, an inverter circuit, and a full-adder circuit, and describes a parallel multiplier circuit capable of high-speed operation with a time of about 10 nsec independent of the bit length. The proposed CMOS basic circuits utilize a multi-voltage power supply to enable dynamic operation with pre-charged output terminals at signal level 0 (VDD1). This design methodology is applicable to arithmetic circuits for highly accurate, high-speed processors.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122334037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Starting 2005, there will be a yearly award from the MVL Technical Committee for the outstanding contribution by a young researcher in the area of Multiple-Valued Logic. The award will be USD 200 and a commemorative plaque. The award will be open to graduate and undergraduate students and researchers who are within five years of receiving their terminal degrees. To be considered, the individual must be the first author of the paper and must present the paper at the symposium.
{"title":"Two New Awards","authors":"M. Perkowski","doi":"10.1109/ISMVL.2005.51","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.51","url":null,"abstract":"Starting 2005, there will be a yearly award from the MVL Technical Committee for the outstanding contribution by a young researcher in the area of Multiple-Valued Logic. The award will be USD 200 and a commemorative plaque. The award will be open to graduate and undergraduate students and researchers who are within five years of receiving their terminal degrees. To be considered, the individual must be the first author of the paper and must present the paper at the symposium.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122742616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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