In this paper we present a novel voltage mode non-inverting CMOS semi floating-gate (SFG) ternary switching element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35 /spl mu/m process parameters c35b4 is included.
{"title":"A novel ternary switching element using CMOS recharge semi floating-gate devices","authors":"H. Gundersen, R. Jensen, Y. Berg","doi":"10.1109/ISMVL.2005.5","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.5","url":null,"abstract":"In this paper we present a novel voltage mode non-inverting CMOS semi floating-gate (SFG) ternary switching element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35 /spl mu/m process parameters c35b4 is included.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132100906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Evolutionary optimization of fuzzy if-then rules for approximation is an area of research that has received much attention in the last years. The present paper adds a new possibility by proposing a method for data-driven reshaping or designing the uncertainty transitions of piecewise linear fuzzy sets representing the linguistic terms of the fuzzy rules.
{"title":"A new aspect for the optimization of fuzzy if-then rules","authors":"C. Moraga, Rodrigo F. Salas","doi":"10.1109/ISMVL.2005.3","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.3","url":null,"abstract":"Evolutionary optimization of fuzzy if-then rules for approximation is an area of research that has received much attention in the last years. The present paper adds a new possibility by proposing a method for data-driven reshaping or designing the uncertainty transitions of piecewise linear fuzzy sets representing the linguistic terms of the fuzzy rules.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125138178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We define a collection of mappings that transform many-valued clausal forms into satisfiability equivalent Boolean clausal forms, analyze their complexity and evaluate them empirically on a set of benchmarks with a SAT solver. Our results show that encoding combinatorial problems with the mappings defined here can lead to substantial performance improvements in complete SAT solvers.
{"title":"Mapping many-valued CNF formulas to Boolean CNF formulas","authors":"C. Ansótegui, F. Manyà","doi":"10.1109/ISMVL.2005.23","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.23","url":null,"abstract":"We define a collection of mappings that transform many-valued clausal forms into satisfiability equivalent Boolean clausal forms, analyze their complexity and evaluate them empirically on a set of benchmarks with a SAT solver. Our results show that encoding combinatorial problems with the mappings defined here can lead to substantial performance improvements in complete SAT solvers.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133767034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is believed that quantum computing will begin to have a practical impact in industry around year 2010. We propose an approach to test generation and fault localization for a wide category of fault models. While in general we follow the methods used in test of standard circuits, there are two significant differences: (2) we use both deterministic and probabilistic tests to detect faults, (2) we use special measurement gates to determine the internal states. A fault table is created that includes probabilistic information. "Probabilistic set covering" and "probabilistic adaptive trees" that generalize those known in standard circuits, are next used.
{"title":"Test generation and fault localization for quantum circuits","authors":"M. Perkowski, J. Biamonte, M. Lukac","doi":"10.1109/ISMVL.2005.46","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.46","url":null,"abstract":"It is believed that quantum computing will begin to have a practical impact in industry around year 2010. We propose an approach to test generation and fault localization for a wide category of fault models. While in general we follow the methods used in test of standard circuits, there are two significant differences: (2) we use both deterministic and probabilistic tests to detect faults, (2) we use special measurement gates to determine the internal states. A fault table is created that includes probabilistic information. \"Probabilistic set covering\" and \"probabilistic adaptive trees\" that generalize those known in standard circuits, are next used.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128285442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose three novel cache models using multiple-valued logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded systems. Multiple-valued caches have significant potential for compact and power-efficient cache array design. The cache models differ from each other depending on whether they store tag and data in binary, radix-r or a mix of both. Our analytical study of cache silicon area shows that an embedded system-on-a-chip (SoC) equipped with a multiple-valued cache model can reduce the cache data storage area up to 6% regardless of cache parameters. Also, our experiments on several embedded benchmarks demonstrate that dynamic cache energy consumption can be reduced up to 62% in a multiple-valued instruction cache in an embedded SoC.
{"title":"Multiple-valued caches for power-efficient embedded systems","authors":"E. Özer, Resit Sendag, David Gregg","doi":"10.1109/ISMVL.2005.28","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.28","url":null,"abstract":"In this paper, we propose three novel cache models using multiple-valued logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded systems. Multiple-valued caches have significant potential for compact and power-efficient cache array design. The cache models differ from each other depending on whether they store tag and data in binary, radix-r or a mix of both. Our analytical study of cache silicon area shows that an embedded system-on-a-chip (SoC) equipped with a multiple-valued cache model can reduce the cache data storage area up to 6% regardless of cache parameters. Also, our experiments on several embedded benchmarks demonstrate that dynamic cache energy consumption can be reduced up to 62% in a multiple-valued instruction cache in an embedded SoC.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121811895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One first defines the triangles of a lattice T, that is, the lattices /spl Delta//sup s/(T) of all decreasing sequences of s elements of T, and study some basic properties (modularity, distributivity, boundedness, atomisticity, inf-pseudo complementation, monotonic representations) of /spl Delta//sup s/(T). An important result is: if T is a Boolean algebra, then /spl Delta//sup s/(T) is a Post algebra (of order (s+1)); one specially discusses the case when T is the powerset P(/spl Omega/):/spl Delta//sup s/(T) is then isomorphic to the postian lattice P/sub s+1/(/spl Omega/) of the (s+1)-ordered partitions of Q, which is a multivalued genereralization of the powerset. Afterwards, one studies some cases where T is, in turn, a Post algebra, specially T=P/sub r/(/spl Omega/). One then exhibits some typical finite distributive lattices called leibnizians, denoted and also defines, with the help of triangulation, the lattices P/sub s, r/(/spl Omega/) which are called the postians of type (s, r) of a set /spl Omega/. Actually both structures (leibnizians as well as postians) turn out to be important algebraic condensations of Post multivalued logical conceptions.
{"title":"A note on triangulation of PostAlgebras and /spl Lt/leibnizian/spl Gt/ lattices","authors":"M. Serfati","doi":"10.1109/ISMVL.2005.4","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.4","url":null,"abstract":"One first defines the triangles of a lattice T, that is, the lattices /spl Delta//sup s/(T) of all decreasing sequences of s elements of T, and study some basic properties (modularity, distributivity, boundedness, atomisticity, inf-pseudo complementation, monotonic representations) of /spl Delta//sup s/(T). An important result is: if T is a Boolean algebra, then /spl Delta//sup s/(T) is a Post algebra (of order (s+1)); one specially discusses the case when T is the powerset P(/spl Omega/):/spl Delta//sup s/(T) is then isomorphic to the postian lattice P/sub s+1/(/spl Omega/) of the (s+1)-ordered partitions of Q, which is a multivalued genereralization of the powerset. Afterwards, one studies some cases where T is, in turn, a Post algebra, specially T=P/sub r/(/spl Omega/). One then exhibits some typical finite distributive lattices called leibnizians, denoted and also defines, with the help of triangulation, the lattices P/sub s, r/(/spl Omega/) which are called the postians of type (s, r) of a set /spl Omega/. Actually both structures (leibnizians as well as postians) turn out to be important algebraic condensations of Post multivalued logical conceptions.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"24 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130685468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2/sup n/) and O(n/sup 2//spl middot/2/sup n/), respectively. FPGA implementations show their feasibility up to n=14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n=14.
{"title":"Hardware to compute Walsh coefficients","authors":"Y. Iguchi, Tsutomu Sasao","doi":"10.1109/ISMVL.2005.19","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.19","url":null,"abstract":"This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2/sup n/) and O(n/sup 2//spl middot/2/sup n/), respectively. FPGA implementations show their feasibility up to n=14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n=14.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128133666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper the concept of a multi-valued non-deterministic (propositional) matrix, in which non-deterministic computations of truth values are allowed, is extended to languages with quantifiers. We describe the difficulties involved in applying the two main classical approaches to interpreting quantifiers, the objectual and the substitutional, and solve the difficulties in the case of the latter. Then we turn to the two-valued case, and explore the effects in this context of each of the four standard Gentzen-type rules for the classical quantifiers. As an example, a sound and complete two-valued non-deterministic semantics is provided for a family of first-order proof systems.
{"title":"Quantification in non-deterministic multi-valued structures","authors":"A. Avron, A. Zamansky","doi":"10.1109/ISMVL.2005.40","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.40","url":null,"abstract":"In this paper the concept of a multi-valued non-deterministic (propositional) matrix, in which non-deterministic computations of truth values are allowed, is extended to languages with quantifiers. We describe the difficulties involved in applying the two main classical approaches to interpreting quantifiers, the objectual and the substitutional, and solve the difficulties in the case of the latter. Then we turn to the two-valued case, and explore the effects in this context of each of the four standard Gentzen-type rules for the classical quantifiers. As an example, a sound and complete two-valued non-deterministic semantics is provided for a family of first-order proof systems.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129016218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Charles Elkan (1994) claimed that, despite the popularity of using fuzzy logic, it could only be used in controllers and would never be successfully used in expert systems. This claim forms the basis of Elkan's 'paradox' and relies on a distinction between fuzzy controllers and expert systems. Yet it is unclear whether this distinction even exists and if Elkan is justified in using it to support his claim. An examination of this distinction is undertaken where it is shown to be faulty and Elkan's 'paradox' is rejected. The correctness of using fuzzy logic to model different kinds of vagueness and uncertainty is then examined in an effort to determine the kinds of phenomena fuzzy logic can be successfully used to deal with.
Charles Elkan(1994)声称，尽管使用模糊逻辑很受欢迎，但它只能用于控制器，永远不会成功地用于专家系统。这种说法形成了Elkan“悖论”的基础，并依赖于模糊控制器和专家系统之间的区别。然而，目前尚不清楚这种区别是否存在，以及埃尔坎是否有理由利用这种区别来支持他的主张。对这一区别的检验被证明是错误的，Elkan的“悖论”被拒绝了。然后检验了用模糊逻辑对不同类型的模糊性和不确定性进行建模的正确性，以确定模糊逻辑可以成功地用于处理哪些现象。
{"title":"The alleged limitations of fuzzy control","authors":"Phil Serchuk","doi":"10.1109/ISMVL.2005.47","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.47","url":null,"abstract":"Charles Elkan (1994) claimed that, despite the popularity of using fuzzy logic, it could only be used in controllers and would never be successfully used in expert systems. This claim forms the basis of Elkan's 'paradox' and relies on a distinction between fuzzy controllers and expert systems. Yet it is unclear whether this distinction even exists and if Elkan is justified in using it to support his claim. An examination of this distinction is undertaken where it is shown to be faulty and Elkan's 'paradox' is rejected. The correctness of using fuzzy logic to model different kinds of vagueness and uncertainty is then examined in an effort to determine the kinds of phenomena fuzzy logic can be successfully used to deal with.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133535859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper researches the electronic characteristics of fullerenes as enabling multi-terminal carbon-based electronic nanodevices. The multi-valued I-V characteristics that can be uniquely utilized in novel three-dimensional (3D) computing architectures. This drastically improves the overall performance. Functionality, density, bandwidth, power losses and other critical performance characteristics of molecular electronic nanodevices significantly exceed the performance of conventional semiconductor devices. High-fidelity modeling, heterogeneous simulation and data-intensive analysis are performed utilizing the Green function formalism within the developed CAD software tools. The numerical studies favorably agree with the experimental results.
{"title":"Multi-valued nanoelectronics with fullerenes","authors":"S. Lyshevski","doi":"10.1109/ISMVL.2005.27","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.27","url":null,"abstract":"This paper researches the electronic characteristics of fullerenes as enabling multi-terminal carbon-based electronic nanodevices. The multi-valued I-V characteristics that can be uniquely utilized in novel three-dimensional (3D) computing architectures. This drastically improves the overall performance. Functionality, density, bandwidth, power losses and other critical performance characteristics of molecular electronic nanodevices significantly exceed the performance of conventional semiconductor devices. High-fidelity modeling, heterogeneous simulation and data-intensive analysis are performed utilizing the Green function formalism within the developed CAD software tools. The numerical studies favorably agree with the experimental results.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131763631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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