This paper describes a design of a fine-grain multiple-valued field-programmable VLSI (MV-FPVLSI) based on multiple-valued source-coupled logic (MVSCL). An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 2-variable binary logic operation is realized using threshold logic gates. Using 0.35 /spl mu/m standard CMOS design rule, a bit-serial adder is designed using the MV-FPVLSI. Using HSPICE simulation tools, a cell is evaluated and compared with corresponding binary implementation. Comparison results show that, under normalized power consumption better performance can be achieved if the linear summation with weight 1 of the input currents is possible. Moreover, the area of a cell can be reduced to 24% without any degradation in performance. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint.
{"title":"Implementation and evaluation of a fine-grain multiple-valued field programmable VLSI based on source-coupled logic","authors":"H. Munirul, Tomoaki Hasegawa, M. Kameyama","doi":"10.1109/ISMVL.2005.20","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.20","url":null,"abstract":"This paper describes a design of a fine-grain multiple-valued field-programmable VLSI (MV-FPVLSI) based on multiple-valued source-coupled logic (MVSCL). An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 2-variable binary logic operation is realized using threshold logic gates. Using 0.35 /spl mu/m standard CMOS design rule, a bit-serial adder is designed using the MV-FPVLSI. Using HSPICE simulation tools, a cell is evaluated and compared with corresponding binary implementation. Comparison results show that, under normalized power consumption better performance can be achieved if the linear summation with weight 1 of the input currents is possible. Moreover, the area of a cell can be reduced to 24% without any degradation in performance. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115368245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In digital signal processing, we often use higher radix system to achieve high-speed computation. In such cases, we require radix converters. This paper considers the design of LUT cascades that convert p-nary numbers to g-nary numbers. In particular, we derive several upper bounds on the column multiplicities of decomposition charts that represent radix converters. From these, we can estimate the size of LUT cascades to realize radix converters. These results are useful to design compact radix converters, since these bounds show strategies to partition the outputs into groups.
{"title":"Radix converters: complexity and implementation by LUT cascades","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.2005.41","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.41","url":null,"abstract":"In digital signal processing, we often use higher radix system to achieve high-speed computation. In such cases, we require radix converters. This paper considers the design of LUT cascades that convert p-nary numbers to g-nary numbers. In particular, we derive several upper bounds on the column multiplicities of decomposition charts that represent radix converters. From these, we can estimate the size of LUT cascades to realize radix converters. These results are useful to design compact radix converters, since these bounds show strategies to partition the outputs into groups.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130102801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in low-density parity-check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail codeword, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.
{"title":"Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders","authors":"N. Onizawa, A. Mochizuki, T. Hanyu","doi":"10.1109/ISMVL.2005.29","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.29","url":null,"abstract":"A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in low-density parity-check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail codeword, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123136194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biomolecules exhibit electronic properties that can be uniquely utilized in new generation of electronic nanodevices. Complex three-dimensional information processing, computing and memory architectures can be designed and fabricated using self-assembled biomolecules. Those biomolecules can be used as functional multi-terminal interconnected electronic nanobiodevices. We examine DNA-based transistors (DNA/sup T/) that can find the application in multi-valued logics. Though the considered solution may not have significant advantages compared with conventional CMOS MOSFETs, the performed research serves as a proof-of-concept platform. We provide the proof of feasibility with a significant implication and technological enhancements to complex biomolecular nanoelectronics. It is important to design and analyze functional high-performance electronic nanobiodevices comprehending basic phenomena and effects in biomolecule - junction/connect complexes. Electronic behavior and I-V characteristics of DNA/sup T/ are studied merging experimental and theoretical results.
{"title":"Multi-valued DNA-based electronic nanodevices","authors":"M. Lyshevski","doi":"10.1109/ISMVL.2005.26","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.26","url":null,"abstract":"Biomolecules exhibit electronic properties that can be uniquely utilized in new generation of electronic nanodevices. Complex three-dimensional information processing, computing and memory architectures can be designed and fabricated using self-assembled biomolecules. Those biomolecules can be used as functional multi-terminal interconnected electronic nanobiodevices. We examine DNA-based transistors (DNA/sup T/) that can find the application in multi-valued logics. Though the considered solution may not have significant advantages compared with conventional CMOS MOSFETs, the performed research serves as a proof-of-concept platform. We provide the proof of feasibility with a significant implication and technological enhancements to complex biomolecular nanoelectronics. It is important to design and analyze functional high-performance electronic nanobiodevices comprehending basic phenomena and effects in biomolecule - junction/connect complexes. Electronic behavior and I-V characteristics of DNA/sup T/ are studied merging experimental and theoretical results.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126591232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The variety of BL-algebras constitutes the algebraic semantic counterpart of Hajek's basic logic BL that is, the infinite-valued logic of all continuous t-norms and their residua. Montagna gives a concrete representation of the free BL-algebra BC/sub 1/ over one generator as an algebra of piecewise linear functions. In this paper we extend Mundici's approach to normal forms for the one-variable fragment of Lukasiewicz logic to the analogous fragment of BL, giving an algorithm to express any BL-formula with one variable as a conjunction of Schauder hats.
{"title":"Normal forms for the one-variable fragment of Hajek's basic logic","authors":"S. Aguzzoli, B. Gerla","doi":"10.1109/ISMVL.2005.32","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.32","url":null,"abstract":"The variety of BL-algebras constitutes the algebraic semantic counterpart of Hajek's basic logic BL that is, the infinite-valued logic of all continuous t-norms and their residua. Montagna gives a concrete representation of the free BL-algebra BC/sub 1/ over one generator as an algebra of piecewise linear functions. In this paper we extend Mundici's approach to normal forms for the one-variable fragment of Lukasiewicz logic to the analogous fragment of BL, giving an algorithm to express any BL-formula with one variable as a conjunction of Schauder hats.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126299025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We show by a purely relational method that the joint-endomorphism of Zadori's three equivalence relations on a set A, |A|>2 is the clone consisting only of trivial functions, i.e., of the projections and constant functions. We use a so called "Wheatstone bridge" which is a device to yield an equivalence relation /spl theta/=W(/spl alpha/,/spl beta/,/spl gamma/) from a triple /spl alpha/,/spl beta/,/spl gamma/ of equivalence relations such that if a function f:A/spl rarr/A preserves /spl alpha/,/spl beta/,/spl gamma/ jointly, then it preserves /spl theta/. We also present a notion of compositions of two semirigid systems which preserve semirigidity. As an application of the composition we give three families of systems of five equivalence relations that are semirigid on the set A with |A|=4i, |A|=3i+1, or |A|=3i+2 for i/spl ges/1.
{"title":"Semirigid equivalence relations - a new proof method","authors":"M. Miyakawa, I. Rosenberg, H. Tatsumi","doi":"10.1109/ISMVL.2005.43","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.43","url":null,"abstract":"We show by a purely relational method that the joint-endomorphism of Zadori's three equivalence relations on a set A, |A|>2 is the clone consisting only of trivial functions, i.e., of the projections and constant functions. We use a so called \"Wheatstone bridge\" which is a device to yield an equivalence relation /spl theta/=W(/spl alpha/,/spl beta/,/spl gamma/) from a triple /spl alpha/,/spl beta/,/spl gamma/ of equivalence relations such that if a function f:A/spl rarr/A preserves /spl alpha/,/spl beta/,/spl gamma/ jointly, then it preserves /spl theta/. We also present a notion of compositions of two semirigid systems which preserve semirigidity. As an application of the composition we give three families of systems of five equivalence relations that are semirigid on the set A with |A|=4i, |A|=3i+1, or |A|=3i+2 for i/spl ges/1.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133058762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, four classes of quaternary linearly independent transformations, which possess fastest forward and inverse transforms with the lowest computational cost have been presented. All the transform matrices are recursively defined and have consistent formulas relating forward and inverse matrices. Computational costs of the calculation for presented transforms have also been discussed.
{"title":"Classes of fastest quaternary linearly independent transformations","authors":"B. Falkowski, Cheng Fu","doi":"10.1109/ISMVL.2005.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.12","url":null,"abstract":"In this paper, four classes of quaternary linearly independent transformations, which possess fastest forward and inverse transforms with the lowest computational cost have been presented. All the transform matrices are recursively defined and have consistent formulas relating forward and inverse matrices. Computational costs of the calculation for presented transforms have also been discussed.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115400785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An ultrahigh-speed continuous-time delta-sigma modulator using a 4-level resonant-tunneling quantizer has been investigated. The quantizer consists of four resonant-tunneling diodes (RTDs) and a source-coupled high-electron-mobility transistor (HEMT) pair, and operates in the fully-differential mode. Circuit simulation shows that the present first-order delta-sigma modulator has a signal-to-noise ratio (SNR) of 49.4 dB at a sampling frequency of 10 GHz and an input bandwidth of 100 MHz. An improvement in the SNR by 5.6 dB is obtained by increasing the number of quantization level from two to four.
{"title":"A design of 10-GHz delta-sigma modulator using a 4-level differential resonant-tunneling quantizer","authors":"K. Eguchi, Masaru Chibashi, T. Waho","doi":"10.1109/ISMVL.2005.2","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.2","url":null,"abstract":"An ultrahigh-speed continuous-time delta-sigma modulator using a 4-level resonant-tunneling quantizer has been investigated. The quantizer consists of four resonant-tunneling diodes (RTDs) and a source-coupled high-electron-mobility transistor (HEMT) pair, and operates in the fully-differential mode. Circuit simulation shows that the present first-order delta-sigma modulator has a signal-to-noise ratio (SNR) of 49.4 dB at a sampling frequency of 10 GHz and an input bandwidth of 100 MHz. An improvement in the SNR by 5.6 dB is obtained by increasing the number of quantization level from two to four.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127122249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In spectral representations of discrete functions, the main optimization goal is to reduce the number of non-zero spectral coefficients of the function that is represented as a linear combination of a set of basis functions. Fourier transform for matrix-valued functions provides a deterministic way to redistribute the complexity of a spectral representation into a small set of matrix-valued coefficients.
{"title":"Remarks on the structure of matrix-valued spectral transforms on finite non-Abelian groups","authors":"R. Stankovic, C. Moraga, J. Astola","doi":"10.1109/ISMVL.2005.42","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.42","url":null,"abstract":"In spectral representations of discrete functions, the main optimization goal is to reduce the number of non-zero spectral coefficients of the function that is represented as a linear combination of a set of basis functions. Fourier transform for matrix-valued functions provides a deterministic way to redistribute the complexity of a spectral representation into a small set of matrix-valued coefficients.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125636459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Novel three-dimensional (3D) nanoscale integrated circuits (nanoICs) are examined in this paper. These nanoICs are synthesized utilizing aggregated 3D neuronal-hypercells (/spl aleph/-hypercells) with multi-terminal electronic nanodevices. The proposed nanodevices ensure multi-valued input-output characteristic that lead to a direct technological solution of multi-valued logic synthesis problem. Super-high-performance computing architectures and memories can be devised (synthesized), designed and optimized. At the system-level, we examine nanoICs as networked aggregated 3D /spl aleph/-hypercells. In particular, scalable 3D /spl aleph/-hypercell topologies are under consideration. These /spl aleph/-hypercells integrate interconnected functional multi-terminal electronic nanodevices that implement logic functions. The proposed nanoICs platform suits the envisioned cognizant computing ensuring preeminent information processing and immense memory.
{"title":"Three dimensional multi-valued design in nanoscale integrated circuits","authors":"S. Lyshevski","doi":"10.1109/ISMVL.2005.49","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.49","url":null,"abstract":"Novel three-dimensional (3D) nanoscale integrated circuits (nanoICs) are examined in this paper. These nanoICs are synthesized utilizing aggregated 3D neuronal-hypercells (/spl aleph/-hypercells) with multi-terminal electronic nanodevices. The proposed nanodevices ensure multi-valued input-output characteristic that lead to a direct technological solution of multi-valued logic synthesis problem. Super-high-performance computing architectures and memories can be devised (synthesized), designed and optimized. At the system-level, we examine nanoICs as networked aggregated 3D /spl aleph/-hypercells. In particular, scalable 3D /spl aleph/-hypercell topologies are under consideration. These /spl aleph/-hypercells integrate interconnected functional multi-terminal electronic nanodevices that implement logic functions. The proposed nanoICs platform suits the envisioned cognizant computing ensuring preeminent information processing and immense memory.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130036419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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