Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241785
L. Zhang, Y. Mitani, A. Kinoshita, S. Takeno, K. Suguro, I. Mizushima, S. Mori, K. Yamamoto, J. Koga, K. Hara, Y. Hayase, S. Ogata
For the first time, we observed the discrete distribution and fluctuation of active B dopants in scaled n-type MOSFETs (nFETs) and in various B-doped epilayers by the site-specific scanning spreading resistance microscopy (SSRM). The non-uniform B distribution observed in narrow and short-channel length nFETs may be the origin of threshold voltage fluctuations in nFETs. Significant B fluctuation at doping levels less than 2×1019 cm-3 was found in Si:B and Si:B/Si:P epilayers prepared at intermediate temperatures, indicating that this phenomenon is a particular characteristic of B dopants. The B fluctuation is attributed to segregation of B dopant, which depends on thermal diffusion and occurs even under thermal equivalent conditions without structural stress. Site-specific SSRM is demonstrated to be capable of observing discrete dopants in silicon.
{"title":"Direct observation of boron dopant fluctuation by site-specific scanning spreading resistance microscopy","authors":"L. Zhang, Y. Mitani, A. Kinoshita, S. Takeno, K. Suguro, I. Mizushima, S. Mori, K. Yamamoto, J. Koga, K. Hara, Y. Hayase, S. Ogata","doi":"10.1109/IRPS.2012.6241785","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241785","url":null,"abstract":"For the first time, we observed the discrete distribution and fluctuation of active B dopants in scaled n-type MOSFETs (nFETs) and in various B-doped epilayers by the site-specific scanning spreading resistance microscopy (SSRM). The non-uniform B distribution observed in narrow and short-channel length nFETs may be the origin of threshold voltage fluctuations in nFETs. Significant B fluctuation at doping levels less than 2×1019 cm-3 was found in Si:B and Si:B/Si:P epilayers prepared at intermediate temperatures, indicating that this phenomenon is a particular characteristic of B dopants. The B fluctuation is attributed to segregation of B dopant, which depends on thermal diffusion and occurs even under thermal equivalent conditions without structural stress. Site-specific SSRM is demonstrated to be capable of observing discrete dopants in silicon.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115398846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241919
An Chen
Low switching current is required for low-power operation of resistive switching memories. Current overshoot during set switching is caused by parasitic capacitance, which may be minimized by effective switching control and reduction of parasitic effects. A different form of current overshoot is also observed during reset switching, where devices go through a transient resistance-reduction process before the reset switching occurs. Reset current overshoot increases actual reset power. Current overshoot has significant impact on the reliability and switching power of resistive switching memories.
{"title":"Current overshoot during set and reset operations of resistive switching memories","authors":"An Chen","doi":"10.1109/IRPS.2012.6241919","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241919","url":null,"abstract":"Low switching current is required for low-power operation of resistive switching memories. Current overshoot during set switching is caused by parasitic capacitance, which may be minimized by effective switching control and reduction of parasitic effects. A different form of current overshoot is also observed during reset switching, where devices go through a transient resistance-reduction process before the reset switching occurs. Reset current overshoot increases actual reset power. Current overshoot has significant impact on the reliability and switching power of resistive switching memories.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131577444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241776
V. Cherman, J. Messemaeker, K. Croes, Biljana Dimcic, G. V. D. Plas, I. D. Wolf, Gerald Beyer, B. Swinnen, E. Beyne
The effect of thermal cycling, accelerated thermal storage and long-term storage at room temperature on the performance of FEOL devices integrated together with through silicon vias (TSVs) is studied. The transistor performance is used as monitor of stress induced in the Si by the TSV. It is observed that storage at high temperatures increases the stress in the Si induced by the TSV while thermal cycling and long- term storage at room temperature decreases this stress. These stress variations are hypothesized to be due to creep of copper in the TSV.
{"title":"Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage","authors":"V. Cherman, J. Messemaeker, K. Croes, Biljana Dimcic, G. V. D. Plas, I. D. Wolf, Gerald Beyer, B. Swinnen, E. Beyne","doi":"10.1109/IRPS.2012.6241776","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241776","url":null,"abstract":"The effect of thermal cycling, accelerated thermal storage and long-term storage at room temperature on the performance of FEOL devices integrated together with through silicon vias (TSVs) is studied. The transistor performance is used as monitor of stress induced in the Si by the TSV. It is observed that storage at high temperatures increases the stress in the Si induced by the TSV while thermal cycling and long- term storage at room temperature decreases this stress. These stress variations are hypothesized to be due to creep of copper in the TSV.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"150 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130862762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241814
J. Autran, S. Serre, D. Munteanu, S. Martinie, S. Semikh, S. Sauze, S. Uznanski, G. Gasiot, P. Roche
This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.
{"title":"Real-time Soft-Error testing of 40nm SRAMs","authors":"J. Autran, S. Serre, D. Munteanu, S. Martinie, S. Semikh, S. Sauze, S. Uznanski, G. Gasiot, P. Roche","doi":"10.1109/IRPS.2012.6241814","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241814","url":null,"abstract":"This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128754778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241845
I. Chatterjee, B. Bhuva, peixiong zhao, B. Narasimham, J. K. Wang, B. Bartz, E. Pitta, M. Buer
Heavy-ion induced upsets are compared in dual-well and triple-well 40 nm CMOS SRAMs. Charge confinement in triple-well structures triggers the single-event upset reversal mechanism for high LET particles. Due to upset reversal, high LET ion-hits incident at off-normal angles show a decrease in SER compared to normally-incident ions for triple-well SRAM cells.
{"title":"Effects of charge confinement and angular strikes in 40 nm dual- and triple-well bulk CMOS SRAMs","authors":"I. Chatterjee, B. Bhuva, peixiong zhao, B. Narasimham, J. K. Wang, B. Bartz, E. Pitta, M. Buer","doi":"10.1109/IRPS.2012.6241845","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241845","url":null,"abstract":"Heavy-ion induced upsets are compared in dual-well and triple-well 40 nm CMOS SRAMs. Charge confinement in triple-well structures triggers the single-event upset reversal mechanism for high LET particles. Due to upset reversal, high LET ion-hits incident at off-normal angles show a decrease in SER compared to normally-incident ions for triple-well SRAM cells.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"490 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123948031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241870
T. Kirimura, K. Croes, Yunlong Li, S. Demuynck, C. Wilson, M. Lofrano, Z. Tokei
Small EM voids in 30nm wide polycrystalline Cu lines which are formed earlier than full voids are characterized using local sense EM test structure. The growth of these initial voids is stopped after a rapid 1-10 Ohm resistance increase. The void mechanism follows a proposed model of polycrystalline Cu grain depletion. It is also shown that by detecting the initial voids, simple and cost effective single level Cu lines can be a promising test method to assess EM reliability in the early stages of process development for scaled Cu interconnects.
{"title":"Initial void chacterization in 30nm wide polycrystalline Cu line using a local sense EM test structure","authors":"T. Kirimura, K. Croes, Yunlong Li, S. Demuynck, C. Wilson, M. Lofrano, Z. Tokei","doi":"10.1109/IRPS.2012.6241870","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241870","url":null,"abstract":"Small EM voids in 30nm wide polycrystalline Cu lines which are formed earlier than full voids are characterized using local sense EM test structure. The growth of these initial voids is stopped after a rapid 1-10 Ohm resistance increase. The void mechanism follows a proposed model of polycrystalline Cu grain depletion. It is also shown that by detecting the initial voids, simple and cost effective single level Cu lines can be a promising test method to assess EM reliability in the early stages of process development for scaled Cu interconnects.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115164707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241932
T. Aichinger, P. Lenahan, T. Grasser, G. Pobegen, M. Nelhiebel
We study deep level defects at the Si/SiO2 interface of 30nm and 5nm SiO2 PMOS devices after negative bias temperature stress (NBTS). Electrical characterization using the direct-current current-voltage (DCIV) technique reveals two defects with different energy levels, recovery and degradation dynamics. To investigate their micro-physical nature, we perform spin dependent recombination (SDR). Besides conventional Pb centers we also find evidence for Pb center-hydrogen complexes.
{"title":"Evidence for Pb center-hydrogen complexes after subjecting PMOS devices to NBTI stress - A combined DCIV/SDR study","authors":"T. Aichinger, P. Lenahan, T. Grasser, G. Pobegen, M. Nelhiebel","doi":"10.1109/IRPS.2012.6241932","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241932","url":null,"abstract":"We study deep level defects at the Si/SiO2 interface of 30nm and 5nm SiO2 PMOS devices after negative bias temperature stress (NBTS). Electrical characterization using the direct-current current-voltage (DCIV) technique reveals two defects with different energy levels, recovery and degradation dynamics. To investigate their micro-physical nature, we perform spin dependent recombination (SDR). Besides conventional Pb centers we also find evidence for Pb center-hydrogen complexes.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122546852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241855
Jiaqi Yang, M. Masuduzzaman, K. Joshi, S. Mukhopadhyay, Jinfeng Kang, S. Mahapatra, M. Alam
We develop a phenomenological theory of PBTI/TDDB reliability of HK/MG gate stack based on heterogeneous trap generation (TG) and structural relaxation in interfacial (IL) and HK layers. With independently measured parameters, we affirm that for typical HK/MG dielectrics (~1nm IL/3nm HK), significantly higher TG in HK dictates the features of positive bias temperature instability (PBTI) and induces dual-Weibull time dependent dielectric breakdown (TDDB). We also verify that larger relaxation energy in HK suppresses the contribution of HK to the stress induced leakage current (SILC). This framework helps us resolve broad range of puzzling PBTI, TDDB and SILC experiments regarding time evolution, voltage dependence and temperature activation, and establish an intrinsic correlation between SILC performance and PBTI/TDDB degradations in nMOS HK/MG dielectrics. We use this model to explore the trade-off between IL scaling and dielectric reliability, a discussion that will eventually be useful in optimizing the performance-reliability of CMOS technology with HK/MG stack.
{"title":"Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics","authors":"Jiaqi Yang, M. Masuduzzaman, K. Joshi, S. Mukhopadhyay, Jinfeng Kang, S. Mahapatra, M. Alam","doi":"10.1109/IRPS.2012.6241855","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241855","url":null,"abstract":"We develop a phenomenological theory of PBTI/TDDB reliability of HK/MG gate stack based on heterogeneous trap generation (TG) and structural relaxation in interfacial (IL) and HK layers. With independently measured parameters, we affirm that for typical HK/MG dielectrics (~1nm IL/3nm HK), significantly higher TG in HK dictates the features of positive bias temperature instability (PBTI) and induces dual-Weibull time dependent dielectric breakdown (TDDB). We also verify that larger relaxation energy in HK suppresses the contribution of HK to the stress induced leakage current (SILC). This framework helps us resolve broad range of puzzling PBTI, TDDB and SILC experiments regarding time evolution, voltage dependence and temperature activation, and establish an intrinsic correlation between SILC performance and PBTI/TDDB degradations in nMOS HK/MG dielectrics. We use this model to explore the trade-off between IL scaling and dielectric reliability, a discussion that will eventually be useful in optimizing the performance-reliability of CMOS technology with HK/MG stack.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123272358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241846
T. Uemura, R. Tanabe, H. Matusyama
In this work, we propose a technique for mitigating multi-bit-upset (MBU) which cannot be corrected by Error-Correction-Code (ECC) with using bit-line alternation and narrow deep-N-well. This technique mitigates MBU without area, performance and power overhead. The mitigation efficiency is evaluated with alpha and neutron acceleration experiments. The experimental results show excellent mitigation efficiency of the proposed technique.
{"title":"Mitigation technique against multi-bit-upset without area, performance and power overhead","authors":"T. Uemura, R. Tanabe, H. Matusyama","doi":"10.1109/IRPS.2012.6241846","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241846","url":null,"abstract":"In this work, we propose a technique for mitigating multi-bit-upset (MBU) which cannot be corrected by Error-Correction-Code (ECC) with using bit-line alternation and narrow deep-N-well. This technique mitigates MBU without area, performance and power overhead. The mitigation efficiency is evaluated with alpha and neutron acceleration experiments. The experimental results show excellent mitigation efficiency of the proposed technique.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130287973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241899
Ming-Yi Lee, A. Teng, C. Tu, Li-Kuang Kuo, Sheng-Qian Dai, Chia-Chien Shine, Te-Chi Yen, Hong-Ji Lee, Chih-Yuan Lu
For the first time, both reliability assessment and physical failure analysis of nanoscale hard-mask-etching Al interconnect were done. The activation energy Ea of electromigration (EM) is 0.8 eV (interfacial activation energy of the most robust electromigration failure) and current density exponent is 1.71 (close to mechanism of void nucleation). For the stressmigration (SM) tests, the resistance degradation of all splits was no more than 5 % after 1000H bake. The good reliability shows feasible extension of hard-mask-etching process to nanowires.
{"title":"Reliability assessment and physical failure analysis of nanoscale hard-mask-etching Al interconnect","authors":"Ming-Yi Lee, A. Teng, C. Tu, Li-Kuang Kuo, Sheng-Qian Dai, Chia-Chien Shine, Te-Chi Yen, Hong-Ji Lee, Chih-Yuan Lu","doi":"10.1109/IRPS.2012.6241899","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241899","url":null,"abstract":"For the first time, both reliability assessment and physical failure analysis of nanoscale hard-mask-etching Al interconnect were done. The activation energy Ea of electromigration (EM) is 0.8 eV (interfacial activation energy of the most robust electromigration failure) and current density exponent is 1.71 (close to mechanism of void nucleation). For the stressmigration (SM) tests, the resistance degradation of all splits was no more than 5 % after 1000H bake. The good reliability shows feasible extension of hard-mask-etching process to nanowires.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121429252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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