Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241789
A. Lucero, Guanghai Xu, D. Huitink
Traditional packaging materials and reliability standards are evolving as low-κ die - package integration challenges increase. The dielectric constants of low-κ die interlayer dielectric (ILD) materials are expected to continue to reduce to manage Resistance/Capacitance, RC, delay as interconnect and cell geometries are reduced. Mechanical strength is also reduced with the improvement in dielectric constant. The scaling of mechanical strength properties must be considered when designing packaging and selecting materials for packaging and assembly. Die-package integration challenges are most often observed when placing large die on flipchip packages where the differences of the coefficient of thermal expansion, CTE, between the package and die become more pronounced. In particular the underfill material and Si backend must be designed to mitigate the CTE difference by having adequate strength to carry or buffer the interfacial loads without exerting enough force to pull off the die stack films, bump interconnect or package films while at use temperatures. Properties like viscosity must also be managed for successful assembly processing. Underfill materials properties are typically coupled with the glass transition temperature, Tg, which means that the CTE and modulus properties that are required for successful assembly, use performance and reliability of the die-package system are fixed to narrow ranges. Traditional reliability standard testing and requirements do no comprehend the new reality where the Tg often falls below the traditional reliability stress test temperature. New stress test standards released by JEDEC show that lower reliability test levels with longer durations can be used to insure end user reliability in the customer use conditions. New standards have not yet been adopted by many parts of the industry, resulting in false failures and inaccurate risk assessments when the accelerated reliability test temperature ranges cause constituent materials to be artificially tested at conditions where materials properties are non-linear. Fortunately, there are many reliability characterization, analysis and reliability estimation methods that can be used to protect the end user. This paper summarizes the die-package integration challenges and trends that the industry is starting to experience along with options to select, evaluate and qualify reliable products.
{"title":"Low-к - package integration challenges and options for reliability qualification","authors":"A. Lucero, Guanghai Xu, D. Huitink","doi":"10.1109/IRPS.2012.6241789","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241789","url":null,"abstract":"Traditional packaging materials and reliability standards are evolving as low-κ die - package integration challenges increase. The dielectric constants of low-κ die interlayer dielectric (ILD) materials are expected to continue to reduce to manage Resistance/Capacitance, RC, delay as interconnect and cell geometries are reduced. Mechanical strength is also reduced with the improvement in dielectric constant. The scaling of mechanical strength properties must be considered when designing packaging and selecting materials for packaging and assembly. Die-package integration challenges are most often observed when placing large die on flipchip packages where the differences of the coefficient of thermal expansion, CTE, between the package and die become more pronounced. In particular the underfill material and Si backend must be designed to mitigate the CTE difference by having adequate strength to carry or buffer the interfacial loads without exerting enough force to pull off the die stack films, bump interconnect or package films while at use temperatures. Properties like viscosity must also be managed for successful assembly processing. Underfill materials properties are typically coupled with the glass transition temperature, Tg, which means that the CTE and modulus properties that are required for successful assembly, use performance and reliability of the die-package system are fixed to narrow ranges. Traditional reliability standard testing and requirements do no comprehend the new reality where the Tg often falls below the traditional reliability stress test temperature. New stress test standards released by JEDEC show that lower reliability test levels with longer durations can be used to insure end user reliability in the customer use conditions. New standards have not yet been adopted by many parts of the industry, resulting in false failures and inaccurate risk assessments when the accelerated reliability test temperature ranges cause constituent materials to be artificially tested at conditions where materials properties are non-linear. Fortunately, there are many reliability characterization, analysis and reliability estimation methods that can be used to protect the end user. This paper summarizes the die-package integration challenges and trends that the industry is starting to experience along with options to select, evaluate and qualify reliable products.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116285249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/ETS.2012.6232999
S. Nassif, V. Kleeberger, Ulf Schlichtmann
It is well known that circuits fail when one or more of the constituent components fails, due -for example- to phenomena such as electromigration in wires. Such hard failures, typically due to topological changes in circuit connectivity, are treated distinctly from soft failures which could be due to components drifting out of spec over time. However, in certain types of circuits, such as memory, the distinction between soft and hard failures is not clearly defined. The primary cause of the blurring between these two phenomena is manufacturing variability, which can make a topologically correct circuit behave as if it had a short or an open. This paper will show the linkage between these two failure types, and show how increasing variability in future technologies will likely exacerbate this problem further.
{"title":"Goldilocks failures: Not too soft, not too hard","authors":"S. Nassif, V. Kleeberger, Ulf Schlichtmann","doi":"10.1109/ETS.2012.6232999","DOIUrl":"https://doi.org/10.1109/ETS.2012.6232999","url":null,"abstract":"It is well known that circuits fail when one or more of the constituent components fails, due -for example- to phenomena such as electromigration in wires. Such hard failures, typically due to topological changes in circuit connectivity, are treated distinctly from soft failures which could be due to components drifting out of spec over time. However, in certain types of circuits, such as memory, the distinction between soft and hard failures is not clearly defined. The primary cause of the blurring between these two phenomena is manufacturing variability, which can make a topologically correct circuit behave as if it had a short or an open. This paper will show the linkage between these two failure types, and show how increasing variability in future technologies will likely exacerbate this problem further.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115784234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241909
Kyongtaek Lee, H. Kim, Junekyun Park, Jongwoo Park
The effects of IL (interfacial layer) thickness and nitrogen concentration of high-k layer on TDDB are comprehensively investigated for HK/MG nMOSFETs. Comparison of the TDDB characteristics based on IL thickness splits manifests that thick IL device exhibits longer failure time and lower SILC augment due to reduction of IL tunneling rate of electron. However, the gate leakage current of thick IL device is aggravated by decrease of total physical oxide thickness even for the same EOT due mainly to thinner HK thickness. Since SILC behavior is attributed to the bulk transient charge trapping by pre-existing defects in HK, the process optimization to reduce bulk defects in HK is a critical solution to improve TDDB in HK/MG nMOSFETs. In addition, nitridation process after HK deposition contributes to passivate oxygen vacancies in the gate dielectrics and removes electron leakage path driven by oxygen vacancies. Hence, nMOSFET with higher nitrogen concentration shows improved TDDB reliability without compromise in DC characteristics and the power law voltage acceleration factor.
{"title":"Gate stack process optimization for TDDB improvement in 28nm high-k/metal gate nMOSFETs","authors":"Kyongtaek Lee, H. Kim, Junekyun Park, Jongwoo Park","doi":"10.1109/IRPS.2012.6241909","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241909","url":null,"abstract":"The effects of IL (interfacial layer) thickness and nitrogen concentration of high-k layer on TDDB are comprehensively investigated for HK/MG nMOSFETs. Comparison of the TDDB characteristics based on IL thickness splits manifests that thick IL device exhibits longer failure time and lower SILC augment due to reduction of IL tunneling rate of electron. However, the gate leakage current of thick IL device is aggravated by decrease of total physical oxide thickness even for the same EOT due mainly to thinner HK thickness. Since SILC behavior is attributed to the bulk transient charge trapping by pre-existing defects in HK, the process optimization to reduce bulk defects in HK is a critical solution to improve TDDB in HK/MG nMOSFETs. In addition, nitridation process after HK deposition contributes to passivate oxygen vacancies in the gate dielectrics and removes electron leakage path driven by oxygen vacancies. Hence, nMOSFET with higher nitrogen concentration shows improved TDDB reliability without compromise in DC characteristics and the power law voltage acceleration factor.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125781790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241864
M. Saitoh, K. Ota, C. Tanaka, Y. Nakabayashi, K. Uchida, T. Numata
We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (RSD) reduction. <;100>;-oriented NW channel further improves on-current as compared to <;110>; NW channel. In Pelgrom plot of σVth of NW Tr., there exists a universal line whose Avt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σVth universal line is eliminated by suppressing RSD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.
我们系统地研究了硅三栅极纳米线晶体管(NW Tr.)的短沟道性能、阈值电压可变性和负偏置温度不稳定性。通过引入带薄栅极间隔的外接S/D，由于寄生电阻(RSD)降低，NW tr的导通电流在相同的关断电流下显着提高。定向NW沟道与;西北通道。在NW Tr. σVth的Pelgrom图中，由于栅极晶粒走向，存在一条Avt小于平面Tr的通用线。通过抑制RSD消除了最窄tr与σVth通用线的偏差。负偏置温度应力在狭窄的NW tr中增强降解可归因于NW角的电场浓度。
{"title":"Performance, variability and reliability of silicon tri-gate nanowire MOSFETs","authors":"M. Saitoh, K. Ota, C. Tanaka, Y. Nakabayashi, K. Uchida, T. Numata","doi":"10.1109/IRPS.2012.6241864","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241864","url":null,"abstract":"We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (RSD) reduction. <;100>;-oriented NW channel further improves on-current as compared to <;110>; NW channel. In Pelgrom plot of σVth of NW Tr., there exists a universal line whose Avt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σVth universal line is eliminated by suppressing RSD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"47 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120857289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241773
C. Yoshida, T. Sugii
We examined the breakdown characteristics of naturally oxidized MgO barriers using a time dependent dielectric breakdown (TDDB) technique. We found that the positive bias dependence of the breakdown time can be explained using the E-model and negative bias dependence can be explained using the power-law model. This asymmetric nature of the oxidized MgO barrier was due to unoxidized Mg metal at the reference/barrier interface. We also estimated the lifetime expansion under pulse voltage stress by taking the Joule heating effects into account.
{"title":"Reliability study of magnetic tunnel junction with naturally oxidized MgO barrier","authors":"C. Yoshida, T. Sugii","doi":"10.1109/IRPS.2012.6241773","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241773","url":null,"abstract":"We examined the breakdown characteristics of naturally oxidized MgO barriers using a time dependent dielectric breakdown (TDDB) technique. We found that the positive bias dependence of the breakdown time can be explained using the E-model and negative bias dependence can be explained using the power-law model. This asymmetric nature of the oxidized MgO barrier was due to unoxidized Mg metal at the reference/barrier interface. We also estimated the lifetime expansion under pulse voltage stress by taking the Joule heating effects into account.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"53 36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130568714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241905
H. Lin, J. Ma
Thermal laser stimulation (TLS) implemented under testing has become an important failure analysis technique for System-on-Chip (SoCs). This technique ensures that devices under testing (DUT) can enter particular modes, which turn on certain circuit blocks when performing TLS. However, from foundry's perspective, TLS operated under testing may not be a cost-effective solution as numerous design and test resources are required. This paper proposes a novel dual source heating system which can localize defects without utilizing any vectors by using a thermal laser in combination with a heating plate connected to a temperature controller. In this study, a defective SoC was globally heated using the heating plate to enhance the leakage path by changing the properties of the chip. Meanwhile, active or passive devices inside the defective SoC were locally heated using the thermal laser to enhance the defect detection capability by changing the electrical behaviors of the active or passive devices. Using this technique, a silicon defect located in an embedded functional circuit block of the defective SoC was successfully isolated without pausing the sample at any certain vectors.
{"title":"Enhancing a current leakage path using a novel dual source heating system","authors":"H. Lin, J. Ma","doi":"10.1109/IRPS.2012.6241905","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241905","url":null,"abstract":"Thermal laser stimulation (TLS) implemented under testing has become an important failure analysis technique for System-on-Chip (SoCs). This technique ensures that devices under testing (DUT) can enter particular modes, which turn on certain circuit blocks when performing TLS. However, from foundry's perspective, TLS operated under testing may not be a cost-effective solution as numerous design and test resources are required. This paper proposes a novel dual source heating system which can localize defects without utilizing any vectors by using a thermal laser in combination with a heating plate connected to a temperature controller. In this study, a defective SoC was globally heated using the heating plate to enhance the leakage path by changing the properties of the chip. Meanwhile, active or passive devices inside the defective SoC were locally heated using the thermal laser to enhance the defect detection capability by changing the electrical behaviors of the active or passive devices. Using this technique, a silicon defect located in an embedded functional circuit block of the defective SoC was successfully isolated without pausing the sample at any certain vectors.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131728854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241900
J. Bae, K. Hwang, K. H. Park, S. Jeon, J. Choi, J. Ahn, S. Kim, D. Ahn, H. Jeong, S. Nam, G. Jeong, H. Cho, D. Jang, Cg Park
Endurance failures are classified into three groups, all of which originate from the atomic transport of GST due to electromigration in molten phase. Based on the analysis, cell structure insusceptible to the atomic transport and for better cycling performance was proposed.
{"title":"Investigation on physical origins of endurance failures in PRAM","authors":"J. Bae, K. Hwang, K. H. Park, S. Jeon, J. Choi, J. Ahn, S. Kim, D. Ahn, H. Jeong, S. Nam, G. Jeong, H. Cho, D. Jang, Cg Park","doi":"10.1109/IRPS.2012.6241900","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241900","url":null,"abstract":"Endurance failures are classified into three groups, all of which originate from the atomic transport of GST due to electromigration in molten phase. Based on the analysis, cell structure insusceptible to the atomic transport and for better cycling performance was proposed.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133534911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241784
N. Yamaguchiya, Y. Hirose, N. Nakanishi, H. Maeda, E. Yoshida, T. Katayama, T. Koyama
We propose an approach to visualize the impurity diffusion layer at a specific site in sub-100 nm CMOS devices using the porous silicon phenomena. This technique is based on electron microscope observations of samples which have been wet treated using self-aligned anodic oxidation in aqueous hydrofluoric acid. This can be applied to both NMOS transistors and PMOS transistors using the same procedure simultaneously in sub-100 nm CMOS transistors. A clear dopant distribution of source/drain and lightly doped drain (LDD) diffusion layers was obtained with not only transmission electron microscope, but also scanning electron microscope. This technique shows excellent reproducibility and stability, which have been critical issues with wet processing methods. In addition, a failure involving the highly-resistive electrical characteristics in the 90 nm-node transistor was analyzed. As a result, it was found that the failure was caused by a local block of LDD ion implantation. Our analysis revealed that visualizing the impurity diffusion layer using this technique can be applied to the fine CMOS devices at a specific site.
{"title":"A simple visualizing technique of impurity diffusion layer using porous silicon phenomena","authors":"N. Yamaguchiya, Y. Hirose, N. Nakanishi, H. Maeda, E. Yoshida, T. Katayama, T. Koyama","doi":"10.1109/IRPS.2012.6241784","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241784","url":null,"abstract":"We propose an approach to visualize the impurity diffusion layer at a specific site in sub-100 nm CMOS devices using the porous silicon phenomena. This technique is based on electron microscope observations of samples which have been wet treated using self-aligned anodic oxidation in aqueous hydrofluoric acid. This can be applied to both NMOS transistors and PMOS transistors using the same procedure simultaneously in sub-100 nm CMOS transistors. A clear dopant distribution of source/drain and lightly doped drain (LDD) diffusion layers was obtained with not only transmission electron microscope, but also scanning electron microscope. This technique shows excellent reproducibility and stability, which have been critical issues with wet processing methods. In addition, a failure involving the highly-resistive electrical characteristics in the 90 nm-node transistor was analyzed. As a result, it was found that the failure was caused by a local block of LDD ion implantation. Our analysis revealed that visualizing the impurity diffusion layer using this technique can be applied to the fine CMOS devices at a specific site.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132739901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241792
T. Frank, C. Chappaz, L. Arnaud, X. Federspiel, F. Colella, E. Petitprez, L. Anghel
This paper focuses on electromigration of SnAgCu interconnects of Fanout embedded Wafer Level Ball Grid Array (FO-eWLB) technology. Black's parameters are analyzed regarding stage of degradation through approaches based on resistance slope modeling and on Failure Criterion (FC).
{"title":"Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package","authors":"T. Frank, C. Chappaz, L. Arnaud, X. Federspiel, F. Colella, E. Petitprez, L. Anghel","doi":"10.1109/IRPS.2012.6241792","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241792","url":null,"abstract":"This paper focuses on electromigration of SnAgCu interconnects of Fanout embedded Wafer Level Ball Grid Array (FO-eWLB) technology. Black's parameters are analyzed regarding stage of degradation through approaches based on resistance slope modeling and on Failure Criterion (FC).","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132193305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241915
A. Jain, A. Islam, M. Alam
In this article, we identify and evaluate the major reliability issues (Negative Bias Temperature Instability, Hot Carrier Injection, and Creep) of Nano-Electro-Mechanical Field Effect Transistor (NEMFET) when used as an analog or digital switch. We use Euler-Bernoulli equation to model the static and dynamic behavior of NEMFET and couple it with classical theories of NBTI, HCI and creep to predict the associated lifetime of the device. Since NBTI and HCI are regularly observed in classical Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), we compare NBTI and HCI induced degradation in NEMFET with that of a MOSFET. We find that, NBTI time-evolution in NEMFET is comparable to that of a MOSFET. In spite of this similarity, while NBTI causes only parametric degradation in MOSFET, it changes the pull-in/pull-out voltage of NEMFET that could lead to catastrophic failure due to stiction. Next, we study HCI, which is a persistent reliability concern for MOSFET, and find that NEMFET may be immune to HCI degradation due to NEMFET's intrinsic pull-in and release dynamics. Finally, we study time dependent mechanical creep in NEMFET for below pull-in operation and find that a time dependent increase in the off-state capacitance and power consumption may negate one of the major advantages of NEMFET as a replacement for MOSFET.
{"title":"On the electro-mechanical reliability of NEMFET as an analog/digital switch","authors":"A. Jain, A. Islam, M. Alam","doi":"10.1109/IRPS.2012.6241915","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241915","url":null,"abstract":"In this article, we identify and evaluate the major reliability issues (Negative Bias Temperature Instability, Hot Carrier Injection, and Creep) of Nano-Electro-Mechanical Field Effect Transistor (NEMFET) when used as an analog or digital switch. We use Euler-Bernoulli equation to model the static and dynamic behavior of NEMFET and couple it with classical theories of NBTI, HCI and creep to predict the associated lifetime of the device. Since NBTI and HCI are regularly observed in classical Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), we compare NBTI and HCI induced degradation in NEMFET with that of a MOSFET. We find that, NBTI time-evolution in NEMFET is comparable to that of a MOSFET. In spite of this similarity, while NBTI causes only parametric degradation in MOSFET, it changes the pull-in/pull-out voltage of NEMFET that could lead to catastrophic failure due to stiction. Next, we study HCI, which is a persistent reliability concern for MOSFET, and find that NEMFET may be immune to HCI degradation due to NEMFET's intrinsic pull-in and release dynamics. Finally, we study time dependent mechanical creep in NEMFET for below pull-in operation and find that a time dependent increase in the off-state capacitance and power consumption may negate one of the major advantages of NEMFET as a replacement for MOSFET.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115218860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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