Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241880
David Horton, F. Ren, Liu Lu, M. Law
An electro-mechanical simulation of the degradation of AlGaN/GaN HEMT's in the Off-state. Strain driven diffusion of impurities from the gate into the AlGaN layer increases trap density which leads to unrecoverable decreases in drain current.
{"title":"An electro-mechanical simulation of off state AlGaN/GaN device degradation","authors":"David Horton, F. Ren, Liu Lu, M. Law","doi":"10.1109/IRPS.2012.6241880","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241880","url":null,"abstract":"An electro-mechanical simulation of the degradation of AlGaN/GaN HEMT's in the Off-state. Strain driven diffusion of impurities from the gate into the AlGaN layer increases trap density which leads to unrecoverable decreases in drain current.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133740775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241832
R. Wong, B. Bhuva, A. Evans, S. Wen
System-level Mean Time Between Failures (MTBF) is usually evaluated using individual component-level reliability metrics. System-level failures are categorized by Reliability, Availability and Serviceability (RAS) metrics. However, RAS evaluation at the system-level requires precise mapping between component failure modes, their system failure signatures and system reliability requirements. In this paper, RAS analysis carried out on internet switches in a top-down hierarchical fashion is presented. Results show availability of failure classification at a lower-level of design allows for better fault management and improved RAS metrics at the system-level. A hierarchical modeling format is proposed to standardize the reporting of component failure modes to improve the system level modeling of RAS.
{"title":"System-level reliability using component-level failure signatures","authors":"R. Wong, B. Bhuva, A. Evans, S. Wen","doi":"10.1109/IRPS.2012.6241832","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241832","url":null,"abstract":"System-level Mean Time Between Failures (MTBF) is usually evaluated using individual component-level reliability metrics. System-level failures are categorized by Reliability, Availability and Serviceability (RAS) metrics. However, RAS evaluation at the system-level requires precise mapping between component failure modes, their system failure signatures and system reliability requirements. In this paper, RAS analysis carried out on internet switches in a top-down hierarchical fashion is presented. Results show availability of failure classification at a lower-level of design allows for better fault management and improved RAS metrics at the system-level. A hierarchical modeling format is proposed to standardize the reporting of component failure modes to improve the system level modeling of RAS.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133751441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241818
N. Wrachien, A. Cester, D. Bari, E. Zanoni, G. Meneghesso, Y. Q. Wu, P. Ye
We performed channel hot carrier stress on enhancement-mode, inversion-type III-V MOSFETs with Al2O3 gate dielectric. The stress induces subthreshold swing degradation, increase on the threshold voltage and reduction of drain saturation current. Nonetheless, no appreciable transconductance degradation can be observed at least with a stress time as long as 105 s.
{"title":"Effects of channel hot carrier stress on III–V bulk planar MOSFETs","authors":"N. Wrachien, A. Cester, D. Bari, E. Zanoni, G. Meneghesso, Y. Q. Wu, P. Ye","doi":"10.1109/IRPS.2012.6241818","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241818","url":null,"abstract":"We performed channel hot carrier stress on enhancement-mode, inversion-type III-V MOSFETs with Al2O3 gate dielectric. The stress induces subthreshold swing degradation, increase on the threshold voltage and reduction of drain saturation current. Nonetheless, no appreciable transconductance degradation can be observed at least with a stress time as long as 105 s.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128280371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241808
D. J. Wu, D. Maji, J. Shih, Y. Lee, C. C. Liu, Y. H. Huang, R. Ranjan, K. Wu
Hot-carrier-injection (HCI) induced effects in the electrical characteristics of high voltage n-type Lateral-Diffused-MOSFET (NLDMOS) have been studied extensively under various stress conditions. Width (W) dependent HCI induced appearance/disappearance of kink in linear drain current (IDLIN) of NLDMOS, (i.e. kink appears after stress in large W, but it disappears after stress in narrow W, which presents initially in fresh device IDLIN) is observed under high gate voltage (VG) and drain voltage (VD) stress condition. Such interesting phenomenon has never been seen during maximum substrate current (ISUBMAX) HCI stress. TCAD simulation results revealed that enhancement in interface state generation and localized electron trapping in the gate oxide along the source side drift region are the main root causes of the appearance/disappearance of IDLIN kink under high VG and VD stress. It is suspected that HCI induced IDLIN kink may cause device reliability modeling/prediction concern, if model target is based on IDLIN degradation.
{"title":"Understanding of hot-carrier-injection induced IDLIN kink effect in sub-100nm HV NLDMOS","authors":"D. J. Wu, D. Maji, J. Shih, Y. Lee, C. C. Liu, Y. H. Huang, R. Ranjan, K. Wu","doi":"10.1109/IRPS.2012.6241808","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241808","url":null,"abstract":"Hot-carrier-injection (HCI) induced effects in the electrical characteristics of high voltage n-type Lateral-Diffused-MOSFET (NLDMOS) have been studied extensively under various stress conditions. Width (W) dependent HCI induced appearance/disappearance of kink in linear drain current (IDLIN) of NLDMOS, (i.e. kink appears after stress in large W, but it disappears after stress in narrow W, which presents initially in fresh device IDLIN) is observed under high gate voltage (VG) and drain voltage (VD) stress condition. Such interesting phenomenon has never been seen during maximum substrate current (ISUBMAX) HCI stress. TCAD simulation results revealed that enhancement in interface state generation and localized electron trapping in the gate oxide along the source side drift region are the main root causes of the appearance/disappearance of IDLIN kink under high VG and VD stress. It is suspected that HCI induced IDLIN kink may cause device reliability modeling/prediction concern, if model target is based on IDLIN degradation.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128403707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241791
G. Leatherman, J. Xu, J. Hicks, B. Kilic, D. Pantuso
Shifts in transistor performance due to mechanical stress resulting from interaction of die, packaging, test socketing, and board mount are discussed. Mechanical stress induced transistor drive current shifts are measured indirectly using ring oscillator frequencies. P and N effects are extracted independently using appropriately weighted oscillators, and P/N shifts in opposite directions agree with numerical models, which also predict significant differences between stress states associated with packaged-die test and the final usage configuration. The shifts show systematic variation across the die, raising concerns for predictable circuit performance. An example is SRAM caches, where die-package interactions may degrade VCCmin. The results highlight the need to fully characterize these stress effects in both the test and final usage configurations. These shifts, while significant, can be managed through a combination of package technology, circuit techniques, process optimization, and strategic product floor planning.
{"title":"Die-package stress interaction impact on transistor performance","authors":"G. Leatherman, J. Xu, J. Hicks, B. Kilic, D. Pantuso","doi":"10.1109/IRPS.2012.6241791","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241791","url":null,"abstract":"Shifts in transistor performance due to mechanical stress resulting from interaction of die, packaging, test socketing, and board mount are discussed. Mechanical stress induced transistor drive current shifts are measured indirectly using ring oscillator frequencies. P and N effects are extracted independently using appropriately weighted oscillators, and P/N shifts in opposite directions agree with numerical models, which also predict significant differences between stress states associated with packaged-die test and the final usage configuration. The shifts show systematic variation across the die, raising concerns for predictable circuit performance. An example is SRAM caches, where die-package interactions may degrade VCCmin. The results highlight the need to fully characterize these stress effects in both the test and final usage configurations. These shifts, while significant, can be managed through a combination of package technology, circuit techniques, process optimization, and strategic product floor planning.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129332404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241906
L. Saury, S. Cany
Localization of parametric defects on Analog / Mixed Signal and RF devices remains a challenge today. A very promising dynamic technique to address this issue is the parametric Variation Mapping (xVM) under Thermal Laser Stimulation (TLS). In this paper, we stress the importance of high-speed integrated solution for an efficient xVM implementation, which leads to the concept of Real-Time Variation Mapping (RTVM). Two concrete FPGA-based RTVM solutions are described and validated on Analog and RF case studies. Detailed results are presented and new developments are introduced.
{"title":"Real-Time Variation Mapping for parametric defect localization on ICs. Proof of concept, improvements, and application to new parameters","authors":"L. Saury, S. Cany","doi":"10.1109/IRPS.2012.6241906","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241906","url":null,"abstract":"Localization of parametric defects on Analog / Mixed Signal and RF devices remains a challenge today. A very promising dynamic technique to address this issue is the parametric Variation Mapping (xVM) under Thermal Laser Stimulation (TLS). In this paper, we stress the importance of high-speed integrated solution for an efficient xVM implementation, which leads to the concept of Real-Time Variation Mapping (RTVM). Two concrete FPGA-based RTVM solutions are described and validated on Analog and RF case studies. Detailed results are presented and new developments are introduced.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116104968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241941
S. Aresu, R. Vollertsen, R. Rudolf, C. Schlunder, H. Reisinger, W. Gustin
Hot carrier injection, inducing source-drain current (IDS) increase in p-channel LDMOS transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the on-resistance (RON) is observed [1, 5]. However, it has never been observed before, that the RON drift becomes constant after long stress time and the device resistance is not increased further afterwards. As soon as the RON almost reaches its constant level, the threshold voltage shift begins. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at room temperature is reported.
{"title":"Physical understanding and modelling of new hot-carrier degradation effect on PLDMOS transistor","authors":"S. Aresu, R. Vollertsen, R. Rudolf, C. Schlunder, H. Reisinger, W. Gustin","doi":"10.1109/IRPS.2012.6241941","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241941","url":null,"abstract":"Hot carrier injection, inducing source-drain current (IDS) increase in p-channel LDMOS transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the on-resistance (RON) is observed [1, 5]. However, it has never been observed before, that the RON drift becomes constant after long stress time and the device resistance is not increased further afterwards. As soon as the RON almost reaches its constant level, the threshold voltage shift begins. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at room temperature is reported.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122266444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241889
S. Ighilahriz, F. Cacho, L. Moquillon, S. Razafimandimby, F. Blanchet, J. Morelle, N. Corrao, V. Huard, P. Garcia, C. Arnaud, J. Fournier, P. Benech
A reliability study under DC stress has been conducted on a low noise amplifier (LNA), a mixer and a voltage controlled oscillator (VCO). Both mmW blocks were designed with heterojunction bipolar transistor (HBT) 0.13μm SiGe process from STMicroelectronics. Regarding simulations and HBT degradation studies, DC stresses were defined to provide HBT degradation within the mmW blocks. S parameters were characterized for the LNA; conversion gain and low frequency noise (LFN) were measured for the mixer; oscillation frequency and phase noise were respectively characterized and simulated. LNA and mixer are designed for 77 GHz automotive radar applications and the VCO is designed for 60 GHz wHDMI standard. Limited degradations on mmW blocks characteristics were observed for significant stress conditions covering a time to fail (TTF) of 10years.
{"title":"Reliability study under DC stress on mmW LNA, Mixer and VCO","authors":"S. Ighilahriz, F. Cacho, L. Moquillon, S. Razafimandimby, F. Blanchet, J. Morelle, N. Corrao, V. Huard, P. Garcia, C. Arnaud, J. Fournier, P. Benech","doi":"10.1109/IRPS.2012.6241889","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241889","url":null,"abstract":"A reliability study under DC stress has been conducted on a low noise amplifier (LNA), a mixer and a voltage controlled oscillator (VCO). Both mmW blocks were designed with heterojunction bipolar transistor (HBT) 0.13μm SiGe process from STMicroelectronics. Regarding simulations and HBT degradation studies, DC stresses were defined to provide HBT degradation within the mmW blocks. S parameters were characterized for the LNA; conversion gain and low frequency noise (LFN) were measured for the mixer; oscillation frequency and phase noise were respectively characterized and simulated. LNA and mixer are designed for 77 GHz automotive radar applications and the VCO is designed for 60 GHz wHDMI standard. Limited degradations on mmW blocks characteristics were observed for significant stress conditions covering a time to fail (TTF) of 10years.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127417517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241916
M. Koutsoureli, L. Michalas, G. Papaioannou
The present paper investigates the effect of stressing bias magnitude and stressing time on the discharging process in MEMS capacitive switches. The calculation of discharge current through the dielectric film is based on monitoring the rate of shift of bias for up-state minimum capacitance. The data analysis shows that the discharge current lies in the range of femto-Amperes and the calculated discharge time constant depends directly on the time window of observation and on the stressing conditions. Moreover the analysis reveals an increase of trapped charge that remains in the bulk of the dielectric film for very long time as the stressing bias increases. The dominant discharge process, taking place under an intrinsic field of about 103 V/cm, is found to be the hopping effect.
{"title":"Charge collection mechanism in MEMS capacitive switches","authors":"M. Koutsoureli, L. Michalas, G. Papaioannou","doi":"10.1109/IRPS.2012.6241916","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241916","url":null,"abstract":"The present paper investigates the effect of stressing bias magnitude and stressing time on the discharging process in MEMS capacitive switches. The calculation of discharge current through the dielectric film is based on monitoring the rate of shift of bias for up-state minimum capacitance. The data analysis shows that the discharge current lies in the range of femto-Amperes and the calculated discharge time constant depends directly on the time window of observation and on the stressing conditions. Moreover the analysis reveals an increase of trapped charge that remains in the bulk of the dielectric film for very long time as the stressing bias increases. The dominant discharge process, taking place under an intrinsic field of about 103 V/cm, is found to be the hopping effect.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126459737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241836
S. Kostylev, S. Yatsunenko, A. Yatsunenko
Bioimpedance-information-puncture monitoring and diagnostics technology consists of measurement and comparison of the amplitude and phase of active and reactive components of RF-admittance of biologically active points (BAP), together with spectrum analysis of pulse-wave distortions. These signals are providing instantaneous information on the functional state of 20 basic organs and systems of the human body. High information volume, accuracy, reliability and reproducibility of data were supported by parallel clinical diagnostics.
{"title":"New technology of in-vivo monitoring of functional state of organs and systems of human body","authors":"S. Kostylev, S. Yatsunenko, A. Yatsunenko","doi":"10.1109/IRPS.2012.6241836","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241836","url":null,"abstract":"Bioimpedance-information-puncture monitoring and diagnostics technology consists of measurement and comparison of the amplitude and phase of active and reactive components of RF-admittance of biologically active points (BAP), together with spectrum analysis of pulse-wave distortions. These signals are providing instantaneous information on the functional state of 20 basic organs and systems of the human body. High information volume, accuracy, reliability and reproducibility of data were supported by parallel clinical diagnostics.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121332363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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