Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565972
Pardeep Singh
Cloud computing is an ideal way for large-scale distributed computing and parallel processing. Cloud computing supports a vast number of services which covers a large number of consumer services like the cloud backup of the images, videos in the smartphone, etc. The performance and efficiency of services provided by cloud computing are dependent on the execution time of user tasks presented to the cloud system. Efficient scheduling of user tasks plays a significant role in managing the physical and virtual resources with a better performance in cloud services. Task Scheduling is one of the main types of scheduling performed in a cloud environment that aim to minimize the makespan for the task processing. Makespan means the total time taken by the virtual machines to complete the tasks allocated to them. In heterogeneous system scheduling the different size tasks of different significance is a complex problem that has been tried to resolve with various approaches e.g. FCFS, SJF, Min-Min, Max-Min, etc. In this work, the Branch and Bound (B&B) algorithm has been implemented and tested for assigning these heterogeneous tasks to virtual machines to reduce the makespan. It has configured the environment in the CloudSim simulator and obtained the results mainly about makespan. Results are compared with other general scheduling algorithms i.e. FCFS, MIN-MIN, MAX-MIN, and SJF.
{"title":"Scheduling tasks based on branch and bound algorithm in cloud computing environment","authors":"Pardeep Singh","doi":"10.1109/SPIN52536.2021.9565972","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565972","url":null,"abstract":"Cloud computing is an ideal way for large-scale distributed computing and parallel processing. Cloud computing supports a vast number of services which covers a large number of consumer services like the cloud backup of the images, videos in the smartphone, etc. The performance and efficiency of services provided by cloud computing are dependent on the execution time of user tasks presented to the cloud system. Efficient scheduling of user tasks plays a significant role in managing the physical and virtual resources with a better performance in cloud services. Task Scheduling is one of the main types of scheduling performed in a cloud environment that aim to minimize the makespan for the task processing. Makespan means the total time taken by the virtual machines to complete the tasks allocated to them. In heterogeneous system scheduling the different size tasks of different significance is a complex problem that has been tried to resolve with various approaches e.g. FCFS, SJF, Min-Min, Max-Min, etc. In this work, the Branch and Bound (B&B) algorithm has been implemented and tested for assigning these heterogeneous tasks to virtual machines to reduce the makespan. It has configured the environment in the CloudSim simulator and obtained the results mainly about makespan. Results are compared with other general scheduling algorithms i.e. FCFS, MIN-MIN, MAX-MIN, and SJF.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128315521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566035
Harshit Yadav, Abdul Qadir Khan, Paurush Bhulania
Planning a smaller, effective in power the Ring configuration of the VCO having high recurrence in millimeter wave applications like the L-band applicable in the present-day remote correspondence framework, has been like a concern area for years. In this article, a force viable arrangement in millimeter wave-based Ring Oscillator had been carried out in 45 nm technology innovation utilizing completely differential engineering, along these lines accomplishing rail to rail yield swing value of 1.2 Vpp & normal force dispersal of 320 x 10-6 W, which is exceptionally considerable for a differential design. Preferring the simple execution of the sub module in little bite the dust size, a 5-stage CMOS differential VCRO has been received with devoted predisposition control block, which helps in broadening the segment of the plan & giving huge swing at the yield. The ring configuration of VCO had been approved on TSPICE stage which affirms the greatest tuning recurrence of 1850 MHz with 29% all out symphonious contortion & a total tuning scope of 500 - 1850 MHz.
在当前远程通信框架中的l波段等毫米波应用中，规划一个更小、功率更有效、具有高复发性的压控振荡器环配置多年来一直是一个关注的领域。在本文中，在45纳米技术创新中，利用完全差分工程，在基于毫米波的环形振荡器中进行了力可行安排，沿着这些线路实现了轨到轨的产生摆动值1.2 Vpp和320 x 10-6 W的法向力分散，这对于差分设计来说是非常可观的。更喜欢子模块的简单执行，在很小的尺寸上，5级CMOS差分VCRO已经收到了专门的倾向控制块，这有助于扩大计划的部分并在产量上给予巨大的波动。VCO的环形结构已在TSPICE舞台上获得批准，确认了1850 MHz的最大调谐复发率为29%，总调谐范围为500 - 1850 MHz。
{"title":"A Low Power Fully Differential Ring-VCO Design in 45-nm CMOS Technology for Digital Applications","authors":"Harshit Yadav, Abdul Qadir Khan, Paurush Bhulania","doi":"10.1109/SPIN52536.2021.9566035","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566035","url":null,"abstract":"Planning a smaller, effective in power the Ring configuration of the VCO having high recurrence in millimeter wave applications like the L-band applicable in the present-day remote correspondence framework, has been like a concern area for years. In this article, a force viable arrangement in millimeter wave-based Ring Oscillator had been carried out in 45 nm technology innovation utilizing completely differential engineering, along these lines accomplishing rail to rail yield swing value of 1.2 Vpp & normal force dispersal of 320 x 10-6 W, which is exceptionally considerable for a differential design. Preferring the simple execution of the sub module in little bite the dust size, a 5-stage CMOS differential VCRO has been received with devoted predisposition control block, which helps in broadening the segment of the plan & giving huge swing at the yield. The ring configuration of VCO had been approved on TSPICE stage which affirms the greatest tuning recurrence of 1850 MHz with 29% all out symphonious contortion & a total tuning scope of 500 - 1850 MHz.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128602590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566062
Hrutvik Dhaigude, Vibhati, J. Sinha, J. K. Jain
The brisk development in technology is being observed throughout the world and in every aspect of life. Thus, the demand for a highly efficient, maneuverable with high-speed aircraft is rising for the military sector. Delta wings are the most palpable choice right now and a lot of work has been devoted by many distinguished people in this area. This paper covers the unique characteristics exhibited by a delta wing with a forebody at various angles of attack. A Double Delta wing of 75/40 configuration has been designed and incorporated with a forebody to observe the effect of the whole solid aircraft. Flow separation, vortex generation, primary and secondary vortex lines have been shown through simulations to understand the aerodynamic characteristics and the effect of fore-body in this paper.
{"title":"Aerodynamic Characteristics of a Double Delta Wing with Fore-body","authors":"Hrutvik Dhaigude, Vibhati, J. Sinha, J. K. Jain","doi":"10.1109/SPIN52536.2021.9566062","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566062","url":null,"abstract":"The brisk development in technology is being observed throughout the world and in every aspect of life. Thus, the demand for a highly efficient, maneuverable with high-speed aircraft is rising for the military sector. Delta wings are the most palpable choice right now and a lot of work has been devoted by many distinguished people in this area. This paper covers the unique characteristics exhibited by a delta wing with a forebody at various angles of attack. A Double Delta wing of 75/40 configuration has been designed and incorporated with a forebody to observe the effect of the whole solid aircraft. Flow separation, vortex generation, primary and secondary vortex lines have been shown through simulations to understand the aerodynamic characteristics and the effect of fore-body in this paper.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127465998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566106
C. Chaudhary, Saurabh Mishra, U. Nangia
The intent of paper is to deal with the design of onboard battery charger by interleaved Luo converter topology cascaded with flyback converter to charge a battery. As per this configuration two Luo converters are interleaved and connected in parallel so that the current at input gets divided into them to ensure reliable operation of charger in discontinuous conduction mode. The charger efficiency gets improved because of the reduced stresses of current in the system moreover system works well due to inclusion of less ripple in current at input and output due to the cancellation in ripple within the circuit. Control technique involves closed loop control of cascaded PL in flyback to gain better and controlled results. Distortions in the circuit are reduced to a larger extent and THD is reduced within TEC 61000-3-2 standards. Prototype simulation is validated in MATLAB SIMULINK.
{"title":"Unidirectional Onboard Battery Charging for Electric Vehicle using Interleaved Luo Converter","authors":"C. Chaudhary, Saurabh Mishra, U. Nangia","doi":"10.1109/SPIN52536.2021.9566106","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566106","url":null,"abstract":"The intent of paper is to deal with the design of onboard battery charger by interleaved Luo converter topology cascaded with flyback converter to charge a battery. As per this configuration two Luo converters are interleaved and connected in parallel so that the current at input gets divided into them to ensure reliable operation of charger in discontinuous conduction mode. The charger efficiency gets improved because of the reduced stresses of current in the system moreover system works well due to inclusion of less ripple in current at input and output due to the cancellation in ripple within the circuit. Control technique involves closed loop control of cascaded PL in flyback to gain better and controlled results. Distortions in the circuit are reduced to a larger extent and THD is reduced within TEC 61000-3-2 standards. Prototype simulation is validated in MATLAB SIMULINK.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129973899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566012
Ankit Kumar Dhaikar, S. T. Nagarajan
A procedure of approximating extent of state along with voltage angle built on measurements that have been agreed for every bus of system only at the buses is the Power System State Estimation. The power system state cannot be estimated only by using PMU measurements as PMUs are expensive. Along with the old measurement methods, to estimate the power system's state, phasor measurements are being used as additional measurement. A MATLAB program coded, PMU measurements described along with a simulation has been carried out on bus system's IEEE-30 and IEEE-14 for the technique's verification. A unique estimator model is used in the technique. The technique sets the estimate in current measurements, through post procession in the PMU voltage as well as for the state from the Weight Least Square (WLS) method. Using the measurements which are traditional, the estimation is done by the model in polar coordinates using WLS state estimation. The system's final state is estimated by expressing the PMU measurements along with the states in rectangular coordinates.
{"title":"State Estimation Along WLS-Phasor Measurements in Power System","authors":"Ankit Kumar Dhaikar, S. T. Nagarajan","doi":"10.1109/SPIN52536.2021.9566012","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566012","url":null,"abstract":"A procedure of approximating extent of state along with voltage angle built on measurements that have been agreed for every bus of system only at the buses is the Power System State Estimation. The power system state cannot be estimated only by using PMU measurements as PMUs are expensive. Along with the old measurement methods, to estimate the power system's state, phasor measurements are being used as additional measurement. A MATLAB program coded, PMU measurements described along with a simulation has been carried out on bus system's IEEE-30 and IEEE-14 for the technique's verification. A unique estimator model is used in the technique. The technique sets the estimate in current measurements, through post procession in the PMU voltage as well as for the state from the Weight Least Square (WLS) method. Using the measurements which are traditional, the estimation is done by the model in polar coordinates using WLS state estimation. The system's final state is estimated by expressing the PMU measurements along with the states in rectangular coordinates.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566102
Priya Shukla, Madhurjya Pegu, G. Nandi
Developing behavior based robotic manipulation is a very challenging but necessary task to be solved, especially for humanoid and social robots. Fundamental robotic tasks such as grasping, pick and place, trajectory following are at present solved using conventional forward and inverse kinematics (IK), dynamics and trajectory planning, whereas we learn these complex tasks using past experiences. In this paper, we explore developing behavior based robotic manipulation using reinforcement learning, more specifically learning directly from experiences through interactions with the real world and without knowing the transition model of the environment. Here, we propose a multi agent paradigm to gather experiences from multiple environments in parallel along with a model for populating new generation of agents using Evolutionary Actor-Critic Algorithm (EACA). The agents are of actor-critic architecture and both of them comprises of general purpose neural networks. The actor-critic architecture enables the model to perform well both in high dimensional state space and high dimensional action space which is very crucial for all robotic applications. The proposed algorithm is benchmarked with respect to different multi agent paradigm but keeping the agent’s architecture same. Reinforcement learning, being highly data intensive, requires the use of the CPU and GPU cores to be done judiciously for sampling the environment as well as for training, the details of which have been described here. We have run rigorous experiments for learning joint trajectories on the open gym based KUKA arm manipulator, where our proposed method achieves learning stability within 300 episodes, as compared to the state-of-the-art actor-critic and Advanced Asynchronous Actor-Critic (A3C) algorithms both of which take more than 1000 episodes for learning the same task, showing the effectiveness of our proposed model.
{"title":"Development of Behavior based Robot manipulation using Actor-Critic architecture","authors":"Priya Shukla, Madhurjya Pegu, G. Nandi","doi":"10.1109/SPIN52536.2021.9566102","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566102","url":null,"abstract":"Developing behavior based robotic manipulation is a very challenging but necessary task to be solved, especially for humanoid and social robots. Fundamental robotic tasks such as grasping, pick and place, trajectory following are at present solved using conventional forward and inverse kinematics (IK), dynamics and trajectory planning, whereas we learn these complex tasks using past experiences. In this paper, we explore developing behavior based robotic manipulation using reinforcement learning, more specifically learning directly from experiences through interactions with the real world and without knowing the transition model of the environment. Here, we propose a multi agent paradigm to gather experiences from multiple environments in parallel along with a model for populating new generation of agents using Evolutionary Actor-Critic Algorithm (EACA). The agents are of actor-critic architecture and both of them comprises of general purpose neural networks. The actor-critic architecture enables the model to perform well both in high dimensional state space and high dimensional action space which is very crucial for all robotic applications. The proposed algorithm is benchmarked with respect to different multi agent paradigm but keeping the agent’s architecture same. Reinforcement learning, being highly data intensive, requires the use of the CPU and GPU cores to be done judiciously for sampling the environment as well as for training, the details of which have been described here. We have run rigorous experiments for learning joint trajectories on the open gym based KUKA arm manipulator, where our proposed method achieves learning stability within 300 episodes, as compared to the state-of-the-art actor-critic and Advanced Asynchronous Actor-Critic (A3C) algorithms both of which take more than 1000 episodes for learning the same task, showing the effectiveness of our proposed model.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116723894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566088
G. Ganesh
This Article presents a dual comb shaped patch antenna with defected grounds for wireless communications. With the event of wireless communication technology, a conformal patch MIMO antenna with dual comb shaped structure are presented on patch with DGS (defected ground structure). The MIMO (multiple-input multiple-output) technology is implanted anticipated to be one among the key technologies within the field of wireless communications for 5G applications. The proposed MIMO antenna has resonated at 9.49 GHz and 11.8GHz, the return loss is less than -10dB. The proposed antennas have good gain and radiations characteristics observed. The dual bands are used at X-band for wireless applications.
{"title":"Design of Dual Band Comb Shaped Patch Antenna with Strip Defected Ground for Wireless Communications","authors":"G. Ganesh","doi":"10.1109/SPIN52536.2021.9566088","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566088","url":null,"abstract":"This Article presents a dual comb shaped patch antenna with defected grounds for wireless communications. With the event of wireless communication technology, a conformal patch MIMO antenna with dual comb shaped structure are presented on patch with DGS (defected ground structure). The MIMO (multiple-input multiple-output) technology is implanted anticipated to be one among the key technologies within the field of wireless communications for 5G applications. The proposed MIMO antenna has resonated at 9.49 GHz and 11.8GHz, the return loss is less than -10dB. The proposed antennas have good gain and radiations characteristics observed. The dual bands are used at X-band for wireless applications.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122640533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566099
Ahona Ghosh, Sripama Saha
With the rapid increase in the application areas of Machine Learning and the requirement of cognitive ability detection, the use of Electroencephalogram has become a very effective tool to detect and record electrical activities in our brain. The visual inspection of the conventional methods of neurology can be a bit time consuming and affected by artifacts, which lead to inconsistent results later. The novelty in this idea behind cognitive ability analysis using mental arithmetic tasks lies here. In this paper, after collecting EEG data during mental arithmetic tasks performed by forty subjects, we have extracted features using a novel combination of power spectral density and correntropy spectral density method. The identification of cognitive ability using recurrent neural network has been carried out by classifying the subjects into two classes, i.e., good calculator and bad calculator. The bad calculators get asked to practice more for improving their performance in the next trial. The proposed approach outperforms the existing ones in the concerned domain in terms of its performance and it is well suited as it is flexible for all and the privacy of the user is also maintained.
{"title":"Recurrent Neural Network Based Cognitive Ability Analysis In Mental Arithmetic Task Using Electroencephalogram","authors":"Ahona Ghosh, Sripama Saha","doi":"10.1109/SPIN52536.2021.9566099","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566099","url":null,"abstract":"With the rapid increase in the application areas of Machine Learning and the requirement of cognitive ability detection, the use of Electroencephalogram has become a very effective tool to detect and record electrical activities in our brain. The visual inspection of the conventional methods of neurology can be a bit time consuming and affected by artifacts, which lead to inconsistent results later. The novelty in this idea behind cognitive ability analysis using mental arithmetic tasks lies here. In this paper, after collecting EEG data during mental arithmetic tasks performed by forty subjects, we have extracted features using a novel combination of power spectral density and correntropy spectral density method. The identification of cognitive ability using recurrent neural network has been carried out by classifying the subjects into two classes, i.e., good calculator and bad calculator. The bad calculators get asked to practice more for improving their performance in the next trial. The proposed approach outperforms the existing ones in the concerned domain in terms of its performance and it is well suited as it is flexible for all and the privacy of the user is also maintained.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134519564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565948
Kartikeya Khullar, Sarthak Kathuria, Nishant Chahar, Prince Gupta, Preeti Kaur
In this paper, we present a comparison of the performance of two state-of-the-art model architectures under Adversarial attacks. These are attacks that are designed to trick trained machine learning models. The models compared in this paper perform commendable on the popular image classification dataset CIFAR-10. To generate these adversarial examples for the attack, we are using two strategies, the first one being a very popular attack based on the L∞ metric. And the other one is a relatively new technique that covers fundamentally different types of adversarial examples generated using the Wasserstein distance. We will also be applying two adversarial defenses, preprocessing the input and adversarial training. The comparative results show that even these new state-of-the-art techniques are susceptible to adversarial attacks. Also, we concluded that more studies on adversarial defences are required and current defence techniques must be adopted in real-world applications.
{"title":"A Quantitative Comparison of Image Classification Models under Adversarial Attacks and Defenses","authors":"Kartikeya Khullar, Sarthak Kathuria, Nishant Chahar, Prince Gupta, Preeti Kaur","doi":"10.1109/SPIN52536.2021.9565948","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565948","url":null,"abstract":"In this paper, we present a comparison of the performance of two state-of-the-art model architectures under Adversarial attacks. These are attacks that are designed to trick trained machine learning models. The models compared in this paper perform commendable on the popular image classification dataset CIFAR-10. To generate these adversarial examples for the attack, we are using two strategies, the first one being a very popular attack based on the L∞ metric. And the other one is a relatively new technique that covers fundamentally different types of adversarial examples generated using the Wasserstein distance. We will also be applying two adversarial defenses, preprocessing the input and adversarial training. The comparative results show that even these new state-of-the-art techniques are susceptible to adversarial attacks. Also, we concluded that more studies on adversarial defences are required and current defence techniques must be adopted in real-world applications.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133830685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566135
Sumit Pahuja, Gurjit Kaur
In today’s technology, Parallel Prefix Adders is widely used in VLSI to get higher delay performance. The demand for adders that use reversible logic gates is growing every day as technology advances. However, since reversible logic gates have no information loss, reversible circuits consume less heat than conventional circuits. Reversible logic gates along with extra characteristics that input parity and output parity are equal is termed as PPRLG (parity preserving reversible logic gates). This characteristic allows any device to function normally even if any intermediary nodes fail. The Brent-Kung adder offers a faster response time as compared to many adders. As a consequence, designing an extremely fast, fault-tolerable, and low-power adder immediately results in increased device speed for quicker computing purposes, so Brent Kung adder with the help of PPRLG is presented in our work. The suggested Adder implementation is done using Verilog programming language in the Xilinx software with version 14.7. For the purpose of demonstration of its quality, presented Parity Preserving Reversible Adder, including many sub-parts, we used a number of parameters like Quantum-Cost, CI, GC, and Unused Output, including the schematic (Register Transfer Level) of the Brent-Kung Adder and its sub-parts. So yet, no Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge.
{"title":"A Novel Low Power Design of Brent Kung Adder Having Fault Tolerant Capability","authors":"Sumit Pahuja, Gurjit Kaur","doi":"10.1109/SPIN52536.2021.9566135","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566135","url":null,"abstract":"In today’s technology, Parallel Prefix Adders is widely used in VLSI to get higher delay performance. The demand for adders that use reversible logic gates is growing every day as technology advances. However, since reversible logic gates have no information loss, reversible circuits consume less heat than conventional circuits. Reversible logic gates along with extra characteristics that input parity and output parity are equal is termed as PPRLG (parity preserving reversible logic gates). This characteristic allows any device to function normally even if any intermediary nodes fail. The Brent-Kung adder offers a faster response time as compared to many adders. As a consequence, designing an extremely fast, fault-tolerable, and low-power adder immediately results in increased device speed for quicker computing purposes, so Brent Kung adder with the help of PPRLG is presented in our work. The suggested Adder implementation is done using Verilog programming language in the Xilinx software with version 14.7. For the purpose of demonstration of its quality, presented Parity Preserving Reversible Adder, including many sub-parts, we used a number of parameters like Quantum-Cost, CI, GC, and Unused Output, including the schematic (Register Transfer Level) of the Brent-Kung Adder and its sub-parts. So yet, no Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115555233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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