Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566026
T. Lokhande, S. Sonekar, Aachal Wani
Information Security is a unified piece of information technology that has emerged as vibrant technology in the last two decades. To manage security, authentication assumes a significant part. Biometric is the physical unique identification as well as authentication for the third party. We have proposed the security model for preventing many attacks so we are used the innermost layer as a 3DES (Triple Encryption standard) cryptography algorithm that is providing 3- key protection as 64-bit and the outermost layer used the MD5 (Message Digest) algorithm. i. e. providing 128-bit protection as well as we is using fingerprint identification as physical security that is used in third-party remote integrity auditing. Remote data integrity auditing is proposed to ensure the uprightness of the information put away in the cloud. Data Storage of cloud services has expanded paces of acknowledgment because of their adaptability and the worry of the security and privacy levels. The large number of integrity and security issues that arise depends on the difference between the customer and the service provider in the sense of an external auditor. The remote data integrity auditing is at this point prepared to be viably executed. In the meantime, the proposed scheme is depending on identity-based cryptography, which works on the convoluted testament of the executives. The safety investigation and the exhibition assessment show that the planned property is safe and productive.
{"title":"Development of an Algorithmic Approach for Hiding Sensitive Data and Recovery of Data based on Fingerprint Identification for Secure Cloud Storage","authors":"T. Lokhande, S. Sonekar, Aachal Wani","doi":"10.1109/SPIN52536.2021.9566026","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566026","url":null,"abstract":"Information Security is a unified piece of information technology that has emerged as vibrant technology in the last two decades. To manage security, authentication assumes a significant part. Biometric is the physical unique identification as well as authentication for the third party. We have proposed the security model for preventing many attacks so we are used the innermost layer as a 3DES (Triple Encryption standard) cryptography algorithm that is providing 3- key protection as 64-bit and the outermost layer used the MD5 (Message Digest) algorithm. i. e. providing 128-bit protection as well as we is using fingerprint identification as physical security that is used in third-party remote integrity auditing. Remote data integrity auditing is proposed to ensure the uprightness of the information put away in the cloud. Data Storage of cloud services has expanded paces of acknowledgment because of their adaptability and the worry of the security and privacy levels. The large number of integrity and security issues that arise depends on the difference between the customer and the service provider in the sense of an external auditor. The remote data integrity auditing is at this point prepared to be viably executed. In the meantime, the proposed scheme is depending on identity-based cryptography, which works on the convoluted testament of the executives. The safety investigation and the exhibition assessment show that the planned property is safe and productive.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124587512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565990
Sahajpreet Singh, Sai Chandra Kumar Chintalacheruvu, Saksham Garg, Yash Giri, M. Kumar
Digitalization has been on the rise in the professional, educational, commercial, financial, and basically every major relevant field of the world for much of this century. As every institution race towards ensuring an online presence and accessibility, people have become reliant on digital utilities, sometimes more so than their physical versions. Among the many facilities that are being digitalized, one of them is very relevant to students, employees and organizations which handle mass numbers of people, the attendance system. This is one facility that is still plagued by many errors and loopholes despite its recent development. There is a lack of a secure, robust, userfriendly, automated, and live attendance collection system. This research paper aims to capitalize on this problem and provide a possible solution that addresses these issues.Method: Face recognition system is one such model, which is used to detect real-time human faces. These are used to look for front and side-looking faces and detect them using some technique. They are functioned on the basis of different algorithms. One such algorithm is the LBPH algorithm which this research paper will be talking about. It was earlier used only for text-recognition. But with time, it has evolved and now is able to detect faces with the help of some linking algorithms.Results: This research paper helped us to get an overview on how face recognition system which is in every way a robust, secure and contact-less system can be made. Also, how LBPH algorithm best suits in making such model can be seen through this paper.
{"title":"Efficient Face Identification and Authentication Tool for Biometric Attendance System","authors":"Sahajpreet Singh, Sai Chandra Kumar Chintalacheruvu, Saksham Garg, Yash Giri, M. Kumar","doi":"10.1109/SPIN52536.2021.9565990","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565990","url":null,"abstract":"Digitalization has been on the rise in the professional, educational, commercial, financial, and basically every major relevant field of the world for much of this century. As every institution race towards ensuring an online presence and accessibility, people have become reliant on digital utilities, sometimes more so than their physical versions. Among the many facilities that are being digitalized, one of them is very relevant to students, employees and organizations which handle mass numbers of people, the attendance system. This is one facility that is still plagued by many errors and loopholes despite its recent development. There is a lack of a secure, robust, userfriendly, automated, and live attendance collection system. This research paper aims to capitalize on this problem and provide a possible solution that addresses these issues.Method: Face recognition system is one such model, which is used to detect real-time human faces. These are used to look for front and side-looking faces and detect them using some technique. They are functioned on the basis of different algorithms. One such algorithm is the LBPH algorithm which this research paper will be talking about. It was earlier used only for text-recognition. But with time, it has evolved and now is able to detect faces with the help of some linking algorithms.Results: This research paper helped us to get an overview on how face recognition system which is in every way a robust, secure and contact-less system can be made. Also, how LBPH algorithm best suits in making such model can be seen through this paper.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114337295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566143
Asha Singh, P. K. Nayak, R. Ruchira, P. Choudekar
Multilevel inverters are capable of attaining a staircase output voltage waveform with reduced harmonic content. In this paper, cascaded H bridge 5 level and 7 level inverters are simulated in MATLAB/SIMULINK. The power quality analysis has been carried out for both the designs with and without filters. Filters used at the output of the inverters are low pass filters and second order filters. The amount of deviation of output waveforms from the pure sinusoidal waveforms has been measured as total harmonic distortion. Comparison of both the inverter topologies with and without filters has been done on the basis of Total Harmonic Distortion (THD).
{"title":"Power Quality Enhancement of Cascaded H Bridge 5 Level and 7 Level Inverters","authors":"Asha Singh, P. K. Nayak, R. Ruchira, P. Choudekar","doi":"10.1109/SPIN52536.2021.9566143","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566143","url":null,"abstract":"Multilevel inverters are capable of attaining a staircase output voltage waveform with reduced harmonic content. In this paper, cascaded H bridge 5 level and 7 level inverters are simulated in MATLAB/SIMULINK. The power quality analysis has been carried out for both the designs with and without filters. Filters used at the output of the inverters are low pass filters and second order filters. The amount of deviation of output waveforms from the pure sinusoidal waveforms has been measured as total harmonic distortion. Comparison of both the inverter topologies with and without filters has been done on the basis of Total Harmonic Distortion (THD).","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"59 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114107311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566055
Trupti G. Kamod, P. Rege, S. Kulkarni
Synthetic aperture radar (SAR) images can pass through cloud cover, dry particles, and haze except for heavy rainfall. Therefore, they are available in all climates, all the time. However, the SAR images are corrupted by speckle noise generated by coherent processing of SAR signal. In this paper, the denoise auto-encoder model is proposed to reduce the speckle noise in SAR images, and the performance of the auto-encoder model is compared with different spatial-domain adaptive filters viz. Lee, Frost, Enhanced Lee, Enhanced Frost. The performance of the proposed denoising encoder is assessed using visual analysis, and quantitative evaluation using metrics, viz. equivalent number of looks (ENL), speckle suppression index (SSI) and speckle suppression and mean preservation index (SMPI). The evaluation of the denoise auto-encoder reveals that its performance is better than spatial- domain adaptive filters.
{"title":"Denoise Auto-Encoder Based Speckle Reduction for RISAT-1 SAR Imagery","authors":"Trupti G. Kamod, P. Rege, S. Kulkarni","doi":"10.1109/SPIN52536.2021.9566055","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566055","url":null,"abstract":"Synthetic aperture radar (SAR) images can pass through cloud cover, dry particles, and haze except for heavy rainfall. Therefore, they are available in all climates, all the time. However, the SAR images are corrupted by speckle noise generated by coherent processing of SAR signal. In this paper, the denoise auto-encoder model is proposed to reduce the speckle noise in SAR images, and the performance of the auto-encoder model is compared with different spatial-domain adaptive filters viz. Lee, Frost, Enhanced Lee, Enhanced Frost. The performance of the proposed denoising encoder is assessed using visual analysis, and quantitative evaluation using metrics, viz. equivalent number of looks (ENL), speckle suppression index (SSI) and speckle suppression and mean preservation index (SMPI). The evaluation of the denoise auto-encoder reveals that its performance is better than spatial- domain adaptive filters.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566019
Roosefert Mohan T, Preetha Roselyn J, Annie Uthra R
Achieving the customer demand in manufacturing industries during Covid-19 situation is a challenging task since the industry needs to stick on to the local government policies such as high safety, work from home, man power reduction for the purpose of social distance, travelling in transport etc. If the machines produce quality products without any interruption, minor stoppages or breakdown, then the industry can achieve its production demand satisfying the customer need along with Covid-19 restrictions. By implementing autonomous maintenance called Jisu Hazen (JH) pillar of Total Productive Maintenance, around 70% of breakdown caused due to forced deterioration can be eliminated. Data centric digitalization through Industry 4.0 and Industrial Internet of Things, manpower and manmade errors are reduced which intern eliminate breakdown, defects and increase productivity. Using smart sensors, the signature parameters related to Clean Lubricate Inspection and Tightening CLIT are digitalized and a smart JH is followed. Through smart JH, operators working hours, number of employees are reduced, work from home situation is made for maintenance engineers to maintain Covid-19 rules.
{"title":"Autonomous Maintenance in Industrial Revolution 4.0 during Covid-19–A Real Time Approach","authors":"Roosefert Mohan T, Preetha Roselyn J, Annie Uthra R","doi":"10.1109/SPIN52536.2021.9566019","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566019","url":null,"abstract":"Achieving the customer demand in manufacturing industries during Covid-19 situation is a challenging task since the industry needs to stick on to the local government policies such as high safety, work from home, man power reduction for the purpose of social distance, travelling in transport etc. If the machines produce quality products without any interruption, minor stoppages or breakdown, then the industry can achieve its production demand satisfying the customer need along with Covid-19 restrictions. By implementing autonomous maintenance called Jisu Hazen (JH) pillar of Total Productive Maintenance, around 70% of breakdown caused due to forced deterioration can be eliminated. Data centric digitalization through Industry 4.0 and Industrial Internet of Things, manpower and manmade errors are reduced which intern eliminate breakdown, defects and increase productivity. Using smart sensors, the signature parameters related to Clean Lubricate Inspection and Tightening CLIT are digitalized and a smart JH is followed. Through smart JH, operators working hours, number of employees are reduced, work from home situation is made for maintenance engineers to maintain Covid-19 rules.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565992
B. Dhananjay, N. Venkatesh, Arya Bhardwaj, J. Sivaraman
The challenging aspect of diagnosing cardiac abnormalities is the accurate classification of cardiac signals. Classifying cardiac abnormalities having similar wave morphologies by manual measurements is a herculean task. The main aim of this work is to classify Sinus Rhythm (SR), Sinus Tachycardia (ST) under physical stress, and Atrial Tachycardia (AT), by developing a machine learning model, Extra Trees (ET). The input feature set of the developed ET model consist of clinical morphologies of the cardiac signal. The clinical morphologies include durations (in ms) of P wave, PR Interval (PRI), QRS complex, T wave, QT Interval (QTI), PP Interval (PPI), and amplitudes (μV) of P, R, and T waves. Apart from classifying, the ET model has also ranked the essential clinical features required to diagnose SR, ST and AT signals. According to the ET model, P (ms), PPI (ms), and P (μV) are the crucial features to classify signals. The precision, recall, and F1 scores of the developed ET model in SR are 0.99, 0.929, and 0.963, respectively, in ST is 0.99 and in AT are 0.947, 0.99, and 0.973, respectively. The advantage of ET model over other classifiers is that, being an ensemble-based classifier developed from a decision tree classifier, it prevents over fitting.
诊断心脏异常最具挑战性的方面是心脏信号的准确分类。通过人工测量对具有相似波形的心脏异常进行分类是一项艰巨的任务。这项工作的主要目的是通过开发机器学习模型Extra Trees (ET)，对生理压力下的窦性心律(SR)、窦性心动过速(ST)和房性心动过速(AT)进行分类。所开发的ET模型的输入特征集由心脏信号的临床形态学组成。临床形态学包括P波持续时间(ms)、PR间期(PRI)、QRS复合体、T波、QT间期(QTI)、PP间期(PPI)和P波、R波、T波振幅(μV)。除了分类之外，ET模型还对诊断SR、ST和AT信号所需的基本临床特征进行了排序。根据ET模型，P (ms)、PPI (ms)和P (μV)是信号分类的关键特征。所建立的ET模型在SR上的精密度、召回率和F1分数分别为0.99、0.929和0.963，在ST上为0.99，在AT上分别为0.947、0.99和0.973。ET模型相对于其他分类器的优势在于，作为一个从决策树分类器发展而来的基于集成的分类器，它可以防止过度拟合。
{"title":"Cardiac signals classification based on Extra Trees model","authors":"B. Dhananjay, N. Venkatesh, Arya Bhardwaj, J. Sivaraman","doi":"10.1109/SPIN52536.2021.9565992","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565992","url":null,"abstract":"The challenging aspect of diagnosing cardiac abnormalities is the accurate classification of cardiac signals. Classifying cardiac abnormalities having similar wave morphologies by manual measurements is a herculean task. The main aim of this work is to classify Sinus Rhythm (SR), Sinus Tachycardia (ST) under physical stress, and Atrial Tachycardia (AT), by developing a machine learning model, Extra Trees (ET). The input feature set of the developed ET model consist of clinical morphologies of the cardiac signal. The clinical morphologies include durations (in ms) of P wave, PR Interval (PRI), QRS complex, T wave, QT Interval (QTI), PP Interval (PPI), and amplitudes (μV) of P, R, and T waves. Apart from classifying, the ET model has also ranked the essential clinical features required to diagnose SR, ST and AT signals. According to the ET model, P (ms), PPI (ms), and P (μV) are the crucial features to classify signals. The precision, recall, and F1 scores of the developed ET model in SR are 0.99, 0.929, and 0.963, respectively, in ST is 0.99 and in AT are 0.947, 0.99, and 0.973, respectively. The advantage of ET model over other classifiers is that, being an ensemble-based classifier developed from a decision tree classifier, it prevents over fitting.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126518434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566007
G. Dewangan, G. Prasad, Bipin Chandra Mandi
MIPS-based RISC processor has a wide range of applications because of its low power consumption and high-speed performance. Here a design of Pipeline based MIPS processor is proposed using the forwarding and stalling process. A pipeline is used to improve each stage’s utilization factor and improve the overall performance of MIPS. A pipeline-based MIPS processor is presented here and has different five processing stages instruction fetch (IF), instruction decode (ID), execution (EXE), memory (MEM), and write back(WB). The data hazard solving technique is achieved by using the method as mentioned above. The design had been synthesized and simulated with the help of the Xilinx Vivado tool and implemented in the Virtex ultra scale board, and the total consumption power of 0.999 W is measured.
{"title":"Design and Implementation of 32 bit MIPS based RISC Processor","authors":"G. Dewangan, G. Prasad, Bipin Chandra Mandi","doi":"10.1109/SPIN52536.2021.9566007","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566007","url":null,"abstract":"MIPS-based RISC processor has a wide range of applications because of its low power consumption and high-speed performance. Here a design of Pipeline based MIPS processor is proposed using the forwarding and stalling process. A pipeline is used to improve each stage’s utilization factor and improve the overall performance of MIPS. A pipeline-based MIPS processor is presented here and has different five processing stages instruction fetch (IF), instruction decode (ID), execution (EXE), memory (MEM), and write back(WB). The data hazard solving technique is achieved by using the method as mentioned above. The design had been synthesized and simulated with the help of the Xilinx Vivado tool and implemented in the Virtex ultra scale board, and the total consumption power of 0.999 W is measured.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130197238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566149
Dhirendra Kumar, Himanshu Kesarwani, Kavindra Kandpal, P. K. Misra, M. Goswami
The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. The current starved inverter-based RO is used in place of the power-hungry comparator to save a significant amount of power dissipation observed in the existing design. The metastable circuit is used for providing randomness in the design. The proposed design had resulted in the generation of approximately 40Mbps speed, the power dissipation of 730μW, and energy efficiency of 18.25pJ/bit when designed at 1.1V. The design is fully validated by NIST 800.22 statistical test suite. The proposed design is thus highly suitable for random number generation.
{"title":"Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach","authors":"Dhirendra Kumar, Himanshu Kesarwani, Kavindra Kandpal, P. K. Misra, M. Goswami","doi":"10.1109/SPIN52536.2021.9566149","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566149","url":null,"abstract":"The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. The current starved inverter-based RO is used in place of the power-hungry comparator to save a significant amount of power dissipation observed in the existing design. The metastable circuit is used for providing randomness in the design. The proposed design had resulted in the generation of approximately 40Mbps speed, the power dissipation of 730μW, and energy efficiency of 18.25pJ/bit when designed at 1.1V. The design is fully validated by NIST 800.22 statistical test suite. The proposed design is thus highly suitable for random number generation.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131441598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566148
Neelu Tiwari, Pankaj Gupta
The ion sensitive field effect transistor (ISFET) are being utilized in pH sensor technology to sense pH values. However, it is highly sensitive to temperature and may introduce variations in the output resulting into errors in the reading. This paper proposes a readout integrated circuit (ROIC) for temperature compensation of an ISFET based pH sensor. The resistor present in the bridge works as a thermistor and helps in stabilizing the output. The test circuit is simulated using LTSpice. The analysis is done for a temperature range of 0 − 50°C and pH range of 5.5 to 14 respectively. The performance analysis has been presented with four different type of sensing films i.e. SiO2, Al2O3, Ta2O3 and Si3N4. The proposed circuit gave optimum results, wherein a constant output voltage is achieved throughout the temperature range 0 − 50°C with sensitivity less than 56.33mV/pH. The proposed circuit has been briefly compared with the existing circuits.
{"title":"Temperature Compensation Circuit for ISFET based pH Sensor","authors":"Neelu Tiwari, Pankaj Gupta","doi":"10.1109/SPIN52536.2021.9566148","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566148","url":null,"abstract":"The ion sensitive field effect transistor (ISFET) are being utilized in pH sensor technology to sense pH values. However, it is highly sensitive to temperature and may introduce variations in the output resulting into errors in the reading. This paper proposes a readout integrated circuit (ROIC) for temperature compensation of an ISFET based pH sensor. The resistor present in the bridge works as a thermistor and helps in stabilizing the output. The test circuit is simulated using LTSpice. The analysis is done for a temperature range of 0 − 50°C and pH range of 5.5 to 14 respectively. The performance analysis has been presented with four different type of sensing films i.e. SiO2, Al2O3, Ta2O3 and Si3N4. The proposed circuit gave optimum results, wherein a constant output voltage is achieved throughout the temperature range 0 − 50°C with sensitivity less than 56.33mV/pH. The proposed circuit has been briefly compared with the existing circuits.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"15 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566082
Vishal Sharma, A. Roy, T. Raj
Now a days, Internet of Things (IoT) technology is becoming popular worldwide due to the increasing awareness to connect multifarious objects via internet in a pragmatic manner. IoT technology is constantly playing a key role in effective and pragmatic management of numerous assets of smart city as demanded in modern world. The principal objective of this investigation is to examine the scalability as well as performance measurement of LoRa (Long Range) network for the smart city using IoT. Furthermore, this research contributes to determine maximum sensors that are integrated in smart city model to control and mange various assets in less power consumption. The motive behind this investigation was to measure LoRa networks scalability, considering multifarious factors namely packets payload sizes, spreading factors, total nodes as well as parameters of the duty cycle. The investigational outcomes disclose that highest LoRa sensors which may converse on same network are 1600.
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