Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565978
Vijendra Kumar Singh, Y. Sharma
A marine vessel platform is fitted with sensors and equipments of diverse origin which are required to work in tandem in order to enhance its operation capability. However, due to incompatibilities in the data formats and protocols that are used, these equipments/ sensors cannot be integrated directly. As the systems available are a mixture of digital and analog types, this paper details the design and development of Embedded Interfacing Solution for interfacing of Digital and Resolver type systems for transmission of An embedded interfacing board was using Cadence OrCAD proprietary subsequently implemented using 8051, Digital to Resolver converter modules, low power operational amplifiers and other required components. This electronic embedded interfacing board converts the digital input containing heading angle into Analog Resolver type of output. This was tested using simulated heading angle created with the help of COM Port Toolkit software application and the output of this embedded interfacing solution was measured on Angle Position Indicator (API) and with the help of Oscilloscope.
为了提高船舶平台的运行能力，船舶平台上安装了各种来源的传感器和设备，这些传感器和设备需要串联工作。然而，由于所使用的数据格式和协议不兼容，这些设备/传感器不能直接集成。由于现有的系统是数字和模拟类型的混合，本文详细介绍了用于数字和解析器类型系统的传输接口的嵌入式接口解决方案的设计和开发。嵌入式接口板使用Cadence OrCAD专有技术，随后使用8051实现，数字到解析器转换模块，低功率运算放大器和其他所需组件。该电子嵌入式接口板将包含航向角的数字输入转换为模拟解析器类型的输出。利用COM Port Toolkit软件创建的模拟航向角对其进行了测试，并在角度位置指示器(API)和示波器的帮助下测量了该嵌入式接口方案的输出。
{"title":"Interfacing of Digital and Resolver Type Systems for Transmission of Heading Angle","authors":"Vijendra Kumar Singh, Y. Sharma","doi":"10.1109/SPIN52536.2021.9565978","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565978","url":null,"abstract":"A marine vessel platform is fitted with sensors and equipments of diverse origin which are required to work in tandem in order to enhance its operation capability. However, due to incompatibilities in the data formats and protocols that are used, these equipments/ sensors cannot be integrated directly. As the systems available are a mixture of digital and analog types, this paper details the design and development of Embedded Interfacing Solution for interfacing of Digital and Resolver type systems for transmission of An embedded interfacing board was using Cadence OrCAD proprietary subsequently implemented using 8051, Digital to Resolver converter modules, low power operational amplifiers and other required components. This electronic embedded interfacing board converts the digital input containing heading angle into Analog Resolver type of output. This was tested using simulated heading angle created with the help of COM Port Toolkit software application and the output of this embedded interfacing solution was measured on Angle Position Indicator (API) and with the help of Oscilloscope.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133246183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566111
Aishwarya Tripathy, M. M. Kar
With the increasing rise in global power demand, it is becoming necessary to integrate renewable energy sources into conventional radial distribution systems (RDS). IEEE 33 bus RDS is considered in this study, with solar PV sources incorporated for power loss reduction, voltage fluctuation, and improve the system efficiency. For the purpose of charging and discharging, some electric vehicles (EV) are incorporated into the test system. The objective of the study is to analyze how EVs and Renewable energy sources (RES) affect the voltage profile in the RDS. As RES is introduced in the test system, the voltage profile is improved. To decrease voltage fluctuations, the usage of the hull moving average (HMA) is recommended, which avoids the lag problem associated with the commonly used moving average approaches. The genetic algorithm (GA) is used to solve the optimization problem accurately. The simulation results show that the suggested strategy is effective at smoothing voltage fluctuations while taking into account EV battery degradation and charging plans.
{"title":"Voltage Profile Enhancement of a 33 Bus System Integrated with Renewable Energy Sources and Electric Vehicle","authors":"Aishwarya Tripathy, M. M. Kar","doi":"10.1109/SPIN52536.2021.9566111","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566111","url":null,"abstract":"With the increasing rise in global power demand, it is becoming necessary to integrate renewable energy sources into conventional radial distribution systems (RDS). IEEE 33 bus RDS is considered in this study, with solar PV sources incorporated for power loss reduction, voltage fluctuation, and improve the system efficiency. For the purpose of charging and discharging, some electric vehicles (EV) are incorporated into the test system. The objective of the study is to analyze how EVs and Renewable energy sources (RES) affect the voltage profile in the RDS. As RES is introduced in the test system, the voltage profile is improved. To decrease voltage fluctuations, the usage of the hull moving average (HMA) is recommended, which avoids the lag problem associated with the commonly used moving average approaches. The genetic algorithm (GA) is used to solve the optimization problem accurately. The simulation results show that the suggested strategy is effective at smoothing voltage fluctuations while taking into account EV battery degradation and charging plans.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"145 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565952
R. Dohare, Mainuddin, G. Singhal
Present paper focuses upon development of thermal stabilization scheme based on pulse width modulation (PWM) controller used for iodine evaporation in flowing chemical laser. Iodine acts a lasing medium in chemical oxygen iodine laser (COIL). In COIL, iodine crystals are put in iodine chambers and needs to be continuously evaporated in order to get vapor iodine. For efficient COIL operation, stabilized iodine evaporation is one of the prime needs. In addition, iodine transportation lines are also required to be heated to ~ 75°C-85°C in order to restrict the iodine deposition during transport. Iodine being hazardous to human beings, the said thermal operation has to be continuously monitored and controlled to provide uniform flow of iodine during safe laser operation. Thermal actions are performed by using several rod heaters and belt heaters. A PWM controller based in house thermal stabilization scheme has been developed using feedback mechanism for iodine evaporation with an accuracy of ±0.5°C instead of using commercially available controllers. It comprises of Operational Amplifier LF 356, Instrumentation Amplifier (IA) AD 620, LM 339 Comparator ICs, K type thermocouple and solid state relay (SSR).The developed hardware has been interfaced with data acquisition system (DAS) and all the temperatures were monitored and recorded online.
{"title":"Pulse Width Modulation controller based Thermal Stabilization for Iodine evaporation inflowing chemical laser","authors":"R. Dohare, Mainuddin, G. Singhal","doi":"10.1109/SPIN52536.2021.9565952","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565952","url":null,"abstract":"Present paper focuses upon development of thermal stabilization scheme based on pulse width modulation (PWM) controller used for iodine evaporation in flowing chemical laser. Iodine acts a lasing medium in chemical oxygen iodine laser (COIL). In COIL, iodine crystals are put in iodine chambers and needs to be continuously evaporated in order to get vapor iodine. For efficient COIL operation, stabilized iodine evaporation is one of the prime needs. In addition, iodine transportation lines are also required to be heated to ~ 75°C-85°C in order to restrict the iodine deposition during transport. Iodine being hazardous to human beings, the said thermal operation has to be continuously monitored and controlled to provide uniform flow of iodine during safe laser operation. Thermal actions are performed by using several rod heaters and belt heaters. A PWM controller based in house thermal stabilization scheme has been developed using feedback mechanism for iodine evaporation with an accuracy of ±0.5°C instead of using commercially available controllers. It comprises of Operational Amplifier LF 356, Instrumentation Amplifier (IA) AD 620, LM 339 Comparator ICs, K type thermocouple and solid state relay (SSR).The developed hardware has been interfaced with data acquisition system (DAS) and all the temperatures were monitored and recorded online.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"33 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116391613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566130
Arpan Gupta, Amit Kumar, Tarun Chaudhary, Alka Leekha
In this fast-developing world digital dependency has taken up great heights. With its immense usage comes the concept of revealing false information of an image to feed the dreadful intention which is called nothing but Image Forgery. The duplicated or forged image is operated in a way that detecting the tampered regions can be an exhaustible task. The paper exactly deals with such alterations in the structure of the image. It offers a Hashing technique, which as best described, helps to detect and locate the tampered regions of the image. A comparison of various Hash Functions like MD5 and SHA-2, in particular, is put into effect with its implementation highlighting the desired tampered region of the image which is facilitated by the sliding window approach.
{"title":"Detection and Localization of Tampered Image using Hash Functions*","authors":"Arpan Gupta, Amit Kumar, Tarun Chaudhary, Alka Leekha","doi":"10.1109/SPIN52536.2021.9566130","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566130","url":null,"abstract":"In this fast-developing world digital dependency has taken up great heights. With its immense usage comes the concept of revealing false information of an image to feed the dreadful intention which is called nothing but Image Forgery. The duplicated or forged image is operated in a way that detecting the tampered regions can be an exhaustible task. The paper exactly deals with such alterations in the structure of the image. It offers a Hashing technique, which as best described, helps to detect and locate the tampered regions of the image. A comparison of various Hash Functions like MD5 and SHA-2, in particular, is put into effect with its implementation highlighting the desired tampered region of the image which is facilitated by the sliding window approach.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115595451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566135
Sumit Pahuja, Gurjit Kaur
In today’s technology, Parallel Prefix Adders is widely used in VLSI to get higher delay performance. The demand for adders that use reversible logic gates is growing every day as technology advances. However, since reversible logic gates have no information loss, reversible circuits consume less heat than conventional circuits. Reversible logic gates along with extra characteristics that input parity and output parity are equal is termed as PPRLG (parity preserving reversible logic gates). This characteristic allows any device to function normally even if any intermediary nodes fail. The Brent-Kung adder offers a faster response time as compared to many adders. As a consequence, designing an extremely fast, fault-tolerable, and low-power adder immediately results in increased device speed for quicker computing purposes, so Brent Kung adder with the help of PPRLG is presented in our work. The suggested Adder implementation is done using Verilog programming language in the Xilinx software with version 14.7. For the purpose of demonstration of its quality, presented Parity Preserving Reversible Adder, including many sub-parts, we used a number of parameters like Quantum-Cost, CI, GC, and Unused Output, including the schematic (Register Transfer Level) of the Brent-Kung Adder and its sub-parts. So yet, no Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge.
{"title":"A Novel Low Power Design of Brent Kung Adder Having Fault Tolerant Capability","authors":"Sumit Pahuja, Gurjit Kaur","doi":"10.1109/SPIN52536.2021.9566135","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566135","url":null,"abstract":"In today’s technology, Parallel Prefix Adders is widely used in VLSI to get higher delay performance. The demand for adders that use reversible logic gates is growing every day as technology advances. However, since reversible logic gates have no information loss, reversible circuits consume less heat than conventional circuits. Reversible logic gates along with extra characteristics that input parity and output parity are equal is termed as PPRLG (parity preserving reversible logic gates). This characteristic allows any device to function normally even if any intermediary nodes fail. The Brent-Kung adder offers a faster response time as compared to many adders. As a consequence, designing an extremely fast, fault-tolerable, and low-power adder immediately results in increased device speed for quicker computing purposes, so Brent Kung adder with the help of PPRLG is presented in our work. The suggested Adder implementation is done using Verilog programming language in the Xilinx software with version 14.7. For the purpose of demonstration of its quality, presented Parity Preserving Reversible Adder, including many sub-parts, we used a number of parameters like Quantum-Cost, CI, GC, and Unused Output, including the schematic (Register Transfer Level) of the Brent-Kung Adder and its sub-parts. So yet, no Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115555233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565965
Sandeep Tiwari, Nitesh Gupta, Pranay Yadav
Type 2 diabetes is a long-lived condition that prevents the insulin human system properly using. Insulin sensitivity is a condition that affects patients with type 2 diabetes. This type of diabetes seems to be more common among people in their early and middle years of life. In the proposed hybrid model is the combination of cascaded feed forward neural network (CFFNN) and Lasso Regression method. Lasso regression has always been a kind of regression in deep learning, which participate in training with the decision of functions. The absolute magnitude of the regression coefficient is prohibited. For the simulation of proposed method utilize MATlab (r2018b). For the analysis Diabetes Type2 Patient use Pima Indian and UCI data sets. The proposed hybrid approach shows better outcomes as compare to other recently presented methods in terms of accuracy and other performance parameters.
{"title":"Diabetes Type2 Patient Detection Using LASSO Based CFFNN Machine Learning Approach","authors":"Sandeep Tiwari, Nitesh Gupta, Pranay Yadav","doi":"10.1109/SPIN52536.2021.9565965","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565965","url":null,"abstract":"Type 2 diabetes is a long-lived condition that prevents the insulin human system properly using. Insulin sensitivity is a condition that affects patients with type 2 diabetes. This type of diabetes seems to be more common among people in their early and middle years of life. In the proposed hybrid model is the combination of cascaded feed forward neural network (CFFNN) and Lasso Regression method. Lasso regression has always been a kind of regression in deep learning, which participate in training with the decision of functions. The absolute magnitude of the regression coefficient is prohibited. For the simulation of proposed method utilize MATlab (r2018b). For the analysis Diabetes Type2 Patient use Pima Indian and UCI data sets. The proposed hybrid approach shows better outcomes as compare to other recently presented methods in terms of accuracy and other performance parameters.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124994370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9565966
Abdul Qadir Khan, Harshit Yadav, Paurush Bhulania
Design of two stage Complementry Metal Oxide Semiconductor Operational amplifier has presented in this work, where the OpAmp is designed on T-SPICE with the help of 180 nm technology, also with miller compensation technique for large gain and PSRR. On incorporating the components of external feedback deployment, the op-amp can be utilized for a many applications e.g. in amplifications in ac & dc signals, oscillators, filters, regulators, comparators & other circuits. In this work, emphasis is given for achieving product of a large gain & also higher gain bandwidth. Work has been for obtaining a higher stability value in terms of Phase Margin & less dissipating power. Number of simulations had been presented for testing the targeted parameters, confirming a 72 dB gain with 51 MHz GBW. The phase margin of 57° have attained along with a slew rate value of 24 V/μs. The design & various simulations had carried out for validating the performance of power dissipation having value 290 μW & value of PSRR as 94.66 dB. With all results, the proposed Op-Amp provides a good use in comparator & other data converting services.
{"title":"Miller Compensated Op-Amp Design for High PSRR & High Gain of 72dB in 180-nm CMOS Process","authors":"Abdul Qadir Khan, Harshit Yadav, Paurush Bhulania","doi":"10.1109/SPIN52536.2021.9565966","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565966","url":null,"abstract":"Design of two stage Complementry Metal Oxide Semiconductor Operational amplifier has presented in this work, where the OpAmp is designed on T-SPICE with the help of 180 nm technology, also with miller compensation technique for large gain and PSRR. On incorporating the components of external feedback deployment, the op-amp can be utilized for a many applications e.g. in amplifications in ac & dc signals, oscillators, filters, regulators, comparators & other circuits. In this work, emphasis is given for achieving product of a large gain & also higher gain bandwidth. Work has been for obtaining a higher stability value in terms of Phase Margin & less dissipating power. Number of simulations had been presented for testing the targeted parameters, confirming a 72 dB gain with 51 MHz GBW. The phase margin of 57° have attained along with a slew rate value of 24 V/μs. The design & various simulations had carried out for validating the performance of power dissipation having value 290 μW & value of PSRR as 94.66 dB. With all results, the proposed Op-Amp provides a good use in comparator & other data converting services.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121988318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566024
Narendra Pal, J. Maurya, Y. Prajapati
In this work, LRSPR sensor for detection of macro biomolecules in near infrared range is presented. Using a buffer layer of dielectric with low refractive index between the prism and metal, a long-range surface plasmon resonance (LRSPR) biosensor that exhibits large detection accuracy as well as high figure of merit is proposed. Two-dimensional (2D) material graphene is used to attach biomolecules through carbon-carbon pi-stacking forces. First, the theoretical simulations for optimizing the thicknesses of dielectric buffer layer (Cytop) and gold (Au) metal layer has been carried out. Then, performance parameters DA and FOM were analyzed. The highest FOM of 847.4 RIU−1 is accomplished for the proposed LRSPR sensor with the use of 1500nm thickness of Cytop. We believe that the proposed LRSPR sensor with high DA and FOM could provide potential applications in medical and biosensing field.
{"title":"Figure of Merit Analysis of LRSPR Sensor using Graphene in NIR Regime","authors":"Narendra Pal, J. Maurya, Y. Prajapati","doi":"10.1109/SPIN52536.2021.9566024","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566024","url":null,"abstract":"In this work, LRSPR sensor for detection of macro biomolecules in near infrared range is presented. Using a buffer layer of dielectric with low refractive index between the prism and metal, a long-range surface plasmon resonance (LRSPR) biosensor that exhibits large detection accuracy as well as high figure of merit is proposed. Two-dimensional (2D) material graphene is used to attach biomolecules through carbon-carbon pi-stacking forces. First, the theoretical simulations for optimizing the thicknesses of dielectric buffer layer (Cytop) and gold (Au) metal layer has been carried out. Then, performance parameters DA and FOM were analyzed. The highest FOM of 847.4 RIU−1 is accomplished for the proposed LRSPR sensor with the use of 1500nm thickness of Cytop. We believe that the proposed LRSPR sensor with high DA and FOM could provide potential applications in medical and biosensing field.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114649157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566006
Vishank Makhe, Vinay S. Palaparthy, Yash Agrawal
In this paper, novel reduced graphene oxide (rGO) interconnects for printed circuit boards (PCBs) designs are investigated using experimental analysis. rGO is a newly investigated and prominent material owing to its good electrical, thermal, mechanical and chemical properties. The prospective rGO is benchmarked with respect to conventional copper (Cu) based interconnects. Multiple interconnect device samples are fabricated physically by using FR4 copper clad for the analysis. The current-voltage (I-V) characteristics of these rGO and Cu interconnects are observed for linearity. The parasitic extraction of these interconnects is carried out using inductance-capacitance-resistance (LCR) meter. The characteristics of parasitic elements with respect to varying frequency range from 100 Hz to 10 MHz has been determined and analyzed in detail with the help of LCR meter. The attenuation and slew rate performance parameters are also determined with the help of digital storage oscilloscope (DSO).
{"title":"Parasitic Extraction and Performance Assessment using Experimental Analysis of rGO Interconnects for PCB Designs","authors":"Vishank Makhe, Vinay S. Palaparthy, Yash Agrawal","doi":"10.1109/SPIN52536.2021.9566006","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566006","url":null,"abstract":"In this paper, novel reduced graphene oxide (rGO) interconnects for printed circuit boards (PCBs) designs are investigated using experimental analysis. rGO is a newly investigated and prominent material owing to its good electrical, thermal, mechanical and chemical properties. The prospective rGO is benchmarked with respect to conventional copper (Cu) based interconnects. Multiple interconnect device samples are fabricated physically by using FR4 copper clad for the analysis. The current-voltage (I-V) characteristics of these rGO and Cu interconnects are observed for linearity. The parasitic extraction of these interconnects is carried out using inductance-capacitance-resistance (LCR) meter. The characteristics of parasitic elements with respect to varying frequency range from 100 Hz to 10 MHz has been determined and analyzed in detail with the help of LCR meter. The attenuation and slew rate performance parameters are also determined with the help of digital storage oscilloscope (DSO).","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"2 5‐6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120836488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-26DOI: 10.1109/SPIN52536.2021.9566103
Sheetal Chauhan, M. A. Ansari, O. Singh
The process that is responsible for changing a particular DC voltage to another DC voltage is termed as DC- to-DC voltage conversion. There are three types of DC-to-DC power converters. They are Buck Converter, Boost Converter and Buck-Boost Converter. Buck converter steps down voltage from its input to its output while a buck-boost converter maintains higher or lower output, which depends on the source voltage. A boost converter is a system where voltage at the output terminal is higher than the source voltage. It is generally referred by the name "step-up" converter because of its source voltage stepping up capability. Since, power must always be conserved; current at the output terminal is lower than the current at the input terminal. Power requirement for the boost converter can be fulfilled using some efficient DC source, such as batteries, PV panels and DC generators. Boost converter finds application in consumer electronics, DC motor drives, photovoltaic systems and so on. This paper presents a detailed analysis of DC-to-DC boost converter voltages for renewable electrolysis. The paper presents two circuit topologies of the boost converter viz. one with transformer and the other without transformer. A comparative analysis of these circuit topologies is done and MATLAB simulation results are obtained. It has been proved that the topology using a voltage-matching transformer of high frequency is better. In the analysis, the topology with transformer is proved better for renewable electrolysis due to its regulated output voltage and ripple-free characteristic.
{"title":"A Comparative Analysis of DC - DC Boost Converter Voltages for Renewable Electrolysis","authors":"Sheetal Chauhan, M. A. Ansari, O. Singh","doi":"10.1109/SPIN52536.2021.9566103","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566103","url":null,"abstract":"The process that is responsible for changing a particular DC voltage to another DC voltage is termed as DC- to-DC voltage conversion. There are three types of DC-to-DC power converters. They are Buck Converter, Boost Converter and Buck-Boost Converter. Buck converter steps down voltage from its input to its output while a buck-boost converter maintains higher or lower output, which depends on the source voltage. A boost converter is a system where voltage at the output terminal is higher than the source voltage. It is generally referred by the name \"step-up\" converter because of its source voltage stepping up capability. Since, power must always be conserved; current at the output terminal is lower than the current at the input terminal. Power requirement for the boost converter can be fulfilled using some efficient DC source, such as batteries, PV panels and DC generators. Boost converter finds application in consumer electronics, DC motor drives, photovoltaic systems and so on. This paper presents a detailed analysis of DC-to-DC boost converter voltages for renewable electrolysis. The paper presents two circuit topologies of the boost converter viz. one with transformer and the other without transformer. A comparative analysis of these circuit topologies is done and MATLAB simulation results are obtained. It has been proved that the topology using a voltage-matching transformer of high frequency is better. In the analysis, the topology with transformer is proved better for renewable electrolysis due to its regulated output voltage and ripple-free characteristic.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123505294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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