Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813785
P. Maistri
Dependability of embedded systems is becoming a serious concern even for mass-market systems. Usually, designs are verified by means of fault injection campaigns, but the length of a thorough test often collides with the severe requirements about design cycle times. The number of fault injection experiments is thus usually reduced by performing random fault injections, or by focusing on selected fault models, or on components that depend on specific architectures and workloads. This forces to begin the validation campaign only when the system is fully designed, since specific details about the implementation or the workload are required. In this work, we propose to perform early fault pruning analysis on a formal model of the system, in order to identify the most critical components and computation cycles as soon as possible.
{"title":"Pruning single event upset faults with petri nets","authors":"P. Maistri","doi":"10.1109/LATW.2009.4813785","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813785","url":null,"abstract":"Dependability of embedded systems is becoming a serious concern even for mass-market systems. Usually, designs are verified by means of fault injection campaigns, but the length of a thorough test often collides with the severe requirements about design cycle times. The number of fault injection experiments is thus usually reduced by performing random fault injections, or by focusing on selected fault models, or on components that depend on specific architectures and workloads. This forces to begin the validation campaign only when the system is fully designed, since specific details about the implementation or the workload are required. In this work, we propose to perform early fault pruning analysis on a formal model of the system, in order to identify the most critical components and computation cycles as soon as possible.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124718675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813799
S. Devadze, A. Jutman, I. Aleksejev, R. Ubar
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.
{"title":"Turning JTAG inside out for fast extended test access","authors":"S. Devadze, A. Jutman, I. Aleksejev, R. Ubar","doi":"10.1109/LATW.2009.4813799","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813799","url":null,"abstract":"This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125308230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813790
F. Leite, T. Balen, Marcos Herve, M. Lubaszewski, G. Wirth
This work presents the application of a recomputing-based correction technique to mitigate radiation effects on integrated processors. The recomputing process is associated to Bulk Built-In Current Sensors (BICS) capable of detecting variations in the bulk current due to a particle strike in the circuit silicon area. An 8051 microprocessor is considered as case study. This work focuses on the mitigation of Single Event Transient (SET) faults affecting the execution of the microcontroller instructions. VHDL descriptions of the microcontroller and of the bulk-BICS are simulated and results show that recomputing the instruction, when the BICS indicates a particle strike, is an efficient way to prevent processing errors. The resulting SET-resistant microcontroller presents low area and performance overheads.
{"title":"Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors","authors":"F. Leite, T. Balen, Marcos Herve, M. Lubaszewski, G. Wirth","doi":"10.1109/LATW.2009.4813790","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813790","url":null,"abstract":"This work presents the application of a recomputing-based correction technique to mitigate radiation effects on integrated processors. The recomputing process is associated to Bulk Built-In Current Sensors (BICS) capable of detecting variations in the bulk current due to a particle strike in the circuit silicon area. An 8051 microprocessor is considered as case study. This work focuses on the mitigation of Single Event Transient (SET) faults affecting the execution of the microcontroller instructions. VHDL descriptions of the microcontroller and of the bulk-BICS are simulated and results show that recomputing the instruction, when the BICS indicates a particle strike, is an efficient way to prevent processing errors. The resulting SET-resistant microcontroller presents low area and performance overheads.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115690602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813795
Maurício Banaszeski da Silva, V. Camargo, L. Brusamarello, G. Wirth, Roberto da Silva
NBTI imposes a challenge for the design of circuits in DSM technologies. NBTI causes increase of Vt of the PMOS transistors, thus leading to timing degradation of CMOS circuits over time. This manuscript presents a NBTI-aware transistor sizing technique for high-performance CMOS gates, which improves the cell reliability with minimum area penalty. The delay of an inverter designed on a 32nm technology using our methodology presents 6% delay reduction at year 3 compared to a traditional sizing methodology, both using the same area. For a NAND gate we achieved a delay improvement up to 11%. The methodology here proposed can be extended to other CMOS logic gates, including complex gates.
{"title":"NBTI-aware technique for transistor sizing of high-performance CMOS gates","authors":"Maurício Banaszeski da Silva, V. Camargo, L. Brusamarello, G. Wirth, Roberto da Silva","doi":"10.1109/LATW.2009.4813795","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813795","url":null,"abstract":"NBTI imposes a challenge for the design of circuits in DSM technologies. NBTI causes increase of Vt of the PMOS transistors, thus leading to timing degradation of CMOS circuits over time. This manuscript presents a NBTI-aware transistor sizing technique for high-performance CMOS gates, which improves the cell reliability with minimum area penalty. The delay of an inverter designed on a 32nm technology using our methodology presents 6% delay reduction at year 3 compared to a traditional sizing methodology, both using the same area. For a NAND gate we achieved a delay improvement up to 11%. The methodology here proposed can be extended to other CMOS logic gates, including complex gates.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813792
M. Jenihhin, J. Raik, A. Chepurov, U. Reinsalu, R. Ubar
The paper proposes High-Level Decision Diagrams (HLDDs) model based structural coverage metrics that are applicable to, both, verification and high-level test. Previous works have shown that HLDDs are an efficient model for simulation and test generation. However, the coverage properties of HLDDs against Hardware Description Languages (HDL) have not been studied in detail before. In this paper we show that the proposed methodology allows more stringent structural coverage analysis than traditional VHDL code coverage. Furthermore, the main new contribution of the paper is a hierarchical approach for condition coverage metric analysis that is based on HLDDs with expansion graphs for conditional nodes. Experiments on ITC99 benchmarks show that up to 14% increase in coverage accuracy can be achieved by the proposed methodology.
{"title":"High-Level Decision Diagrams based coverage metrics for verification and test","authors":"M. Jenihhin, J. Raik, A. Chepurov, U. Reinsalu, R. Ubar","doi":"10.1109/LATW.2009.4813792","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813792","url":null,"abstract":"The paper proposes High-Level Decision Diagrams (HLDDs) model based structural coverage metrics that are applicable to, both, verification and high-level test. Previous works have shown that HLDDs are an efficient model for simulation and test generation. However, the coverage properties of HLDDs against Hardware Description Languages (HDL) have not been studied in detail before. In this paper we show that the proposed methodology allows more stringent structural coverage analysis than traditional VHDL code coverage. Furthermore, the main new contribution of the paper is a hierarchical approach for condition coverage metric analysis that is based on HLDDs with expansion graphs for conditional nodes. Experiments on ITC99 benchmarks show that up to 14% increase in coverage accuracy can be achieved by the proposed methodology.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129232017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813811
S. Sondon, P. Mandolesi, P. Julián, F. Palumbo, M. Alurralde, A. Filevich
A set of gates and registers was fabricated on a submicron CMOS process using radiation hardening by design techniques. The circuits were irradiated in a TANDEM accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum shifts on the electrical parameters of transistors. Noise margins and gain of combinational logic gates were unchanged and no increase on leakage current was observed. This work suggests that considerable tolerance to this kind of radiation damage can be reached when accurate design techniques are used together with modern integrated circuits technologies.
{"title":"Radiation damage characterization of digital integrated circuits","authors":"S. Sondon, P. Mandolesi, P. Julián, F. Palumbo, M. Alurralde, A. Filevich","doi":"10.1109/LATW.2009.4813811","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813811","url":null,"abstract":"A set of gates and registers was fabricated on a submicron CMOS process using radiation hardening by design techniques. The circuits were irradiated in a TANDEM accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum shifts on the electrical parameters of transistors. Noise margins and gain of combinational logic gates were unchanged and no increase on leakage current was observed. This work suggests that considerable tolerance to this kind of radiation damage can be reached when accurate design techniques are used together with modern integrated circuits technologies.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132713902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813786
A. Solino, S. Vergilio
Web Services (WS) have been largely used in the development of Web applications. Because of this and die to their importance and inherent characteristics, there is a crescent demand for WS testing techniques and tools. Different testing approaches have been proposed, however most of them do not offer a criterion to be used to evaluate the generated test data. To allow this, the present work explores mutation operators, specific for WSDL documents. The idea is to consider semantic aspects of those documents and to reveal different kind of faults. A supporting tool is also described and evaluation results of a study case are discussed, which allow comparison with other approaches.
{"title":"Mutation based testing of Web Services","authors":"A. Solino, S. Vergilio","doi":"10.1109/LATW.2009.4813786","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813786","url":null,"abstract":"Web Services (WS) have been largely used in the development of Web applications. Because of this and die to their importance and inherent characteristics, there is a crescent demand for WS testing techniques and tools. Different testing approaches have been proposed, however most of them do not offer a criterion to be used to evaluate the generated test data. To allow this, the present work explores mutation operators, specific for WSDL documents. The idea is to consider semantic aspects of those documents and to reveal different kind of faults. A supporting tool is also described and evaluation results of a study case are discussed, which allow comparison with other approaches.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126183696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813793
T. Siqueira, B. Fiss, R. Weber, S. Cechin, T. Weber
How to apply a fault injector to evaluate the dependability of a network protocol implementation is the main focus of this paper. In the last years, we have been developing FIRMAMENT, a tool to inject faults directly into messages that pass through the kernel protocol stack. SCTP is a promising new protocol over IP that, due its enhanced reliability, is competing with TCP where dependability has to be guaranteed. Using FIRMAMENT we evaluate the error coverage and the performance degradation of SCTP under faults. Performing a complete fault injection campaign over a third party software give us a deep insight about the additional test strategies that are needed to reach significant dependability measures.
{"title":"Applying FIRMAMENT to test the SCTP communication protocol under network faults","authors":"T. Siqueira, B. Fiss, R. Weber, S. Cechin, T. Weber","doi":"10.1109/LATW.2009.4813793","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813793","url":null,"abstract":"How to apply a fault injector to evaluate the dependability of a network protocol implementation is the main focus of this paper. In the last years, we have been developing FIRMAMENT, a tool to inject faults directly into messages that pass through the kernel protocol stack. SCTP is a promising new protocol over IP that, due its enhanced reliability, is competing with TCP where dependability has to be guaranteed. Using FIRMAMENT we evaluate the error coverage and the performance degradation of SCTP under faults. Performing a complete fault injection campaign over a third party software give us a deep insight about the additional test strategies that are needed to reach significant dependability measures.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129753788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813796
Alex D. B. Alberto, A. Simão
Many generation methods are available for deriving a test suite from reduced finite state machines. When the machine in question is not reduced, what happens on several situations, those methods cannot be directly applied, requiring first the minimization of the machine. However, the minimization of incompletely specified finite state machines is a known NP-complete problem. Due to the usefulness of such models in systems development and test, the search for heuristics to obtain feasible solutions to the problem has received great attention. Improvements in this area bring clear benefits to model based testing approaches, since it allows the usage of many generation methods that can only be applied to reduced machines. In this paper, we propose an approach to minimize partial finite state machines based on the selection of compatible states using maximum cliques on the distinction graph. We empirically measured the performance of our method against two previous methods and the data show that our new approach generates good results in less time.
{"title":"Minimization of incompletely specified finite state machines based on distinction graphs","authors":"Alex D. B. Alberto, A. Simão","doi":"10.1109/LATW.2009.4813796","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813796","url":null,"abstract":"Many generation methods are available for deriving a test suite from reduced finite state machines. When the machine in question is not reduced, what happens on several situations, those methods cannot be directly applied, requiring first the minimization of the machine. However, the minimization of incompletely specified finite state machines is a known NP-complete problem. Due to the usefulness of such models in systems development and test, the search for heuristics to obtain feasible solutions to the problem has received great attention. Improvements in this area bring clear benefits to model based testing approaches, since it allows the usage of many generation methods that can only be applied to reduced machines. In this paper, we propose an approach to minimize partial finite state machines based on the selection of compatible states using maximum cliques on the distinction graph. We empirically measured the performance of our method against two previous methods and the data show that our new approach generates good results in less time.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"443 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122724118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813813
C. Lisbôa, C. Grando, Álvaro Freitas Moreira, L. Carro
Software based error detection techniques usually imply modification of the algorithms to be hardened, and almost certainly also demand a huge memory footprint and/or execution time overhead. In the software engineering field, program invariants have been proposed as a means to check program correctness during the development cycle. In this work we discuss the use of software invariants verification as a low cost alternative to detect soft errors after the execution of a given algorithm. A clear advantage is that this approach does not require any change in the algorithm to be hardened, and in case its computational cost and memory overhead are proven to be much smaller than duplication for a given algorithm, it may become a feasible option for hardening that algorithm against soft errors. The results of fault injection experiments performed with different algorithms are analyzed and some guidelines for future research concerning this technique are proposed.
{"title":"Using software invariants for dynamic detection of transient errors","authors":"C. Lisbôa, C. Grando, Álvaro Freitas Moreira, L. Carro","doi":"10.1109/LATW.2009.4813813","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813813","url":null,"abstract":"Software based error detection techniques usually imply modification of the algorithms to be hardened, and almost certainly also demand a huge memory footprint and/or execution time overhead. In the software engineering field, program invariants have been proposed as a means to check program correctness during the development cycle. In this work we discuss the use of software invariants verification as a low cost alternative to detect soft errors after the execution of a given algorithm. A clear advantage is that this approach does not require any change in the algorithm to be hardened, and in case its computational cost and memory overhead are proven to be much smaller than duplication for a given algorithm, it may become a feasible option for hardening that algorithm against soft errors. The results of fault injection experiments performed with different algorithms are analyzed and some guidelines for future research concerning this technique are proposed.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124106090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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