Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813817
J. Semião, J. Freijedo, M. Moraes, M. Mallmann, C. Antunes, J. Benfica, F. Vargas, Marcelino B. Santos, I. Teixeira, J. Rodríguez-Andina, João Paulo Teixeira, D. Lupi, E. Gatti, L. Garcia, F. Hernandez
As IC technology scales down, signal integrity issues such as power supply noise and clock skews are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Considering that one of the most important mechanisms to degrade signal integrity is electromagnetic interference (EMI), this paper analyzes the effectiveness of a clock duty-cycle (CDC) modulation technique to enhance SoC signal integrity with respect to power/ground voltage transients induced by EMI. The technique is based on a clock stretching logic (CSL) block, which monitors abnormal power grid activity and increases CDC accordingly. Practical experiments based on the implementation of a 32-bit soft-core pipeline processor in an FPGA IC were performed and illustrate the circuit robustness enhancement to power line fluctuations while maintaining at-speed clock rate. These experiments were conducted according to the IEC 62.132-2. Normative for measurement of radiated electromagnetic immunity (TEM-cell method).
{"title":"Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment","authors":"J. Semião, J. Freijedo, M. Moraes, M. Mallmann, C. Antunes, J. Benfica, F. Vargas, Marcelino B. Santos, I. Teixeira, J. Rodríguez-Andina, João Paulo Teixeira, D. Lupi, E. Gatti, L. Garcia, F. Hernandez","doi":"10.1109/LATW.2009.4813817","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813817","url":null,"abstract":"As IC technology scales down, signal integrity issues such as power supply noise and clock skews are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Considering that one of the most important mechanisms to degrade signal integrity is electromagnetic interference (EMI), this paper analyzes the effectiveness of a clock duty-cycle (CDC) modulation technique to enhance SoC signal integrity with respect to power/ground voltage transients induced by EMI. The technique is based on a clock stretching logic (CSL) block, which monitors abnormal power grid activity and increases CDC accordingly. Practical experiments based on the implementation of a 32-bit soft-core pipeline processor in an FPGA IC were performed and illustrate the circuit robustness enhancement to power line fluctuations while maintaining at-speed clock rate. These experiments were conducted according to the IEC 62.132-2. Normative for measurement of radiated electromagnetic immunity (TEM-cell method).","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122963862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813801
Marcos Herve, É. Cota, F. Kastensmidt, M. Lubaszewski
Test sequences for interconnection testing in network-on-chips (NoC) are usually small. However, to ensure a good fault coverage, the sequence is usually re-applied for a number of paths configurations in the network. In this paper we first analyze the test configuration time required for a functional test strategy devised for mesh NoCs and we show that this time, specially for BIST-based solutions, may become the main bottleneck for overall test time reduction. We then analyze, in terms of area overhead and resulting test time, three alternatives for the implementation of the configuration logic for the test infrastructure. We conclude that boundary scan can be a very interesting solution for test configuration also in NoC testing, leading to a reduced test time and a programmable and reusable strategy.
{"title":"NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time","authors":"Marcos Herve, É. Cota, F. Kastensmidt, M. Lubaszewski","doi":"10.1109/LATW.2009.4813801","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813801","url":null,"abstract":"Test sequences for interconnection testing in network-on-chips (NoC) are usually small. However, to ensure a good fault coverage, the sequence is usually re-applied for a number of paths configurations in the network. In this paper we first analyze the test configuration time required for a functional test strategy devised for mesh NoCs and we show that this time, specially for BIST-based solutions, may become the main bottleneck for overall test time reduction. We then analyze, in terms of area overhead and resulting test time, three alternatives for the implementation of the configuration logic for the test infrastructure. We conclude that boundary scan can be a very interesting solution for test configuration also in NoC testing, leading to a reduced test time and a programmable and reusable strategy.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813806
R. Ubar, S. Kostin, J. Raik
The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) facilities is discussed. A conception for diagnosis of digital circuits, which does not use fault models, and methods for calculating the diagnosibility of the given circuit are presented. The proposed measures of diagnosibility can be used for redesign of the circuit to improve the exactness of locating the faults or faulty regions in digital circuits. Experimental results provide the data which characterize the diagnosibility of circuits for the ISCAS benchmark family.
{"title":"Investigations of the diagnosibility of digital networks with BIST","authors":"R. Ubar, S. Kostin, J. Raik","doi":"10.1109/LATW.2009.4813806","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813806","url":null,"abstract":"The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) facilities is discussed. A conception for diagnosis of digital circuits, which does not use fault models, and methods for calculating the diagnosibility of the given circuit are presented. The proposed measures of diagnosibility can be used for redesign of the circuit to improve the exactness of locating the faults or faulty regions in digital circuits. Experimental results provide the data which characterize the diagnosibility of circuits for the ISCAS benchmark family.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126699550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813802
Ellen Souza, C. Gusmão, Keldjan Alves, Julio Venancio, R. Melo
Risk-based testing is an approach that consists of a set of activities regarding risk factors identification related to software requirements. Once identified, the risks are prioritized according to its likelihood and impact, and the test cases are projected based on the strategies for treatment of the identified risk factors. Then, test efforts are continuously adjusted according the risk monitoring. Most risk-based testing approaches focuses on activities related to risk identification, analysis and prioritizing. However, metrics are fundamental as they quantify characteristics of a process or product and support software project management activities. In this light, this paper proposes and discusses risk-based testing metrics to measure and control test cases and test activities progress, efforts and costs.
{"title":"Measurement and control for risk-based test cases and activities","authors":"Ellen Souza, C. Gusmão, Keldjan Alves, Julio Venancio, R. Melo","doi":"10.1109/LATW.2009.4813802","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813802","url":null,"abstract":"Risk-based testing is an approach that consists of a set of activities regarding risk factors identification related to software requirements. Once identified, the risks are prioritized according to its likelihood and impact, and the test cases are projected based on the strategies for treatment of the identified risk factors. Then, test efforts are continuously adjusted according the risk monitoring. Most risk-based testing approaches focuses on activities related to risk identification, analysis and prioritizing. However, metrics are fundamental as they quantify characteristics of a process or product and support software project management activities. In this light, this paper proposes and discusses risk-based testing metrics to measure and control test cases and test activities progress, efforts and costs.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126103453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813814
E. Brac, P. Ferreyra, R. Velazco, C. Marqués
This work presents a Fault Tolerant FPGA based Active Antenna system intended to be used in the space environment. The proposed design can control the electromagnetic radiation pattern emitted by an antenna array in real time with high reliability levels. The FPGA is a Commercial of the Shelf (COTS) device based on the Anti fuse technology. The design is optimized to reduce the area overhead allowing the control of multiple antennas by means of a single FPGA. The Fault Tolerance and high reliability achieved with the design is shown by means of a new test methodology.
本文提出了一种基于FPGA的容错有源天线系统，用于空间环境。该设计能够实时控制天线阵发射的电磁辐射方向图，具有较高的可靠性。FPGA是基于Anti - fuse技术的COTS (Commercial of The Shelf)器件。该设计经过优化，以减少面积开销，允许通过单个FPGA控制多个天线。通过一种新的测试方法，证明了该设计具有良好的容错性和高可靠性。
{"title":"Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications","authors":"E. Brac, P. Ferreyra, R. Velazco, C. Marqués","doi":"10.1109/LATW.2009.4813814","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813814","url":null,"abstract":"This work presents a Fault Tolerant FPGA based Active Antenna system intended to be used in the space environment. The proposed design can control the electromagnetic radiation pattern emitted by an antenna array in real time with high reliability levels. The FPGA is a Commercial of the Shelf (COTS) device based on the Anti fuse technology. The design is optimized to reduce the area overhead allowing the control of multiple antennas by means of a single FPGA. The Fault Tolerance and high reliability achieved with the design is shown by means of a new test methodology.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"95 33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114156891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813800
Eduardo Ribeiro da Silva, F. Costa, F. Behrens, Remerson Stein Kickhofel, R. Maltione
The crescent complexity of Mixed Signal Integrated Circuits designed for small die size and limited pin count applications in key areas such as embedded applications, introduces a challenge on the IC testability, for debug, production test and field issue control. Traditional analog test approaches based on the existing standards do not completely address the problem due to constraints in architecture complexity, need of dedicated test control interfaces and pin limitations, resulting in expressive test cost impact. This work discuss a cost effective, small die size area Analog Test Bus Interface implemented for small and medium complexity ICs improving its mixed mode interface and reducing the test time. This architecture was implemented in a silicon test vehicle, 0.25u BiCMOS technology, where measurements and results are presented and discussed. An improvement of around 70% in the testability was obtained with this approach, regarding the analog blocks, allowing a powerful real time debug channel.
{"title":"Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis","authors":"Eduardo Ribeiro da Silva, F. Costa, F. Behrens, Remerson Stein Kickhofel, R. Maltione","doi":"10.1109/LATW.2009.4813800","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813800","url":null,"abstract":"The crescent complexity of Mixed Signal Integrated Circuits designed for small die size and limited pin count applications in key areas such as embedded applications, introduces a challenge on the IC testability, for debug, production test and field issue control. Traditional analog test approaches based on the existing standards do not completely address the problem due to constraints in architecture complexity, need of dedicated test control interfaces and pin limitations, resulting in expressive test cost impact. This work discuss a cost effective, small die size area Analog Test Bus Interface implemented for small and medium complexity ICs improving its mixed mode interface and reducing the test time. This architecture was implemented in a silicon test vehicle, 0.25u BiCMOS technology, where measurements and results are presented and discussed. An improvement of around 70% in the testability was obtained with this approach, regarding the analog blocks, allowing a powerful real time debug channel.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117144598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813807
Dieison Antonello Deprá, B. Zatt, S. Bampi
This work presents a new method for hardware functional verification through parallel co-simulation within complex systems using PLI as a mechanism of interface between hardware (HW) and software (SW). This method consists in the HW/SW parallel simulation using a transparent communication between these modules provided by a handshake mechanism that ensure the synchronism between the parts. The discussion about challenges, viability and validity of the presented proposal is based on the results of the case study carried through the application of this method to an H.264/AVC decoder.
{"title":"A method for HW functional verification through HW/SW co-simulation in complex systems: H.264/AVC decoder as case study","authors":"Dieison Antonello Deprá, B. Zatt, S. Bampi","doi":"10.1109/LATW.2009.4813807","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813807","url":null,"abstract":"This work presents a new method for hardware functional verification through parallel co-simulation within complex systems using PLI as a mechanism of interface between hardware (HW) and software (SW). This method consists in the HW/SW parallel simulation using a transparent communication between these modules provided by a handshake mechanism that ensure the synchronism between the parts. The discussion about challenges, viability and validity of the presented proposal is based on the results of the case study carried through the application of this method to an H.264/AVC decoder.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124770609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813803
M. Cappelletti, A. Cédola, S. Baron, G. Casas, E. Y. Blancá
In the present work, a complete numerical analysis of the influence of deep-trap levels on the dark current of silicon PIN photodiodes under 1 MeV neutron radiation was done. Results corroborate that energy levels near the mid-gap affect to a great extent the dark current. Radiation tolerances of undoped and gold-doped devices were compared through simulations. It has been concluded that gold in silicon reduces the neutron-induced damage. Finally, a model to calculate the dark current of irradiated devices doped with deep-impurities is presented.
{"title":"Study of radiation effects on PIN photodiodes with deep-trap levels using computer modeling","authors":"M. Cappelletti, A. Cédola, S. Baron, G. Casas, E. Y. Blancá","doi":"10.1109/LATW.2009.4813803","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813803","url":null,"abstract":"In the present work, a complete numerical analysis of the influence of deep-trap levels on the dark current of silicon PIN photodiodes under 1 MeV neutron radiation was done. Results corroborate that energy levels near the mid-gap affect to a great extent the dark current. Radiation tolerances of undoped and gold-doped devices were compared through simulations. It has been concluded that gold in silicon reduces the neutron-induced damage. Finally, a model to calculate the dark current of irradiated devices doped with deep-impurities is presented.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115936516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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