Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813816
C. Meinhardt, R. Reis, M. Violante, M. Reorda
The checkpoint and rollback recovery techniques enable a system to survive failures by periodically saving a known good snapshot of the system's state, and rolling back to it in case a failure is detected. The approach is particularly interesting for developing critical systems on programmable chips that today offers multiple embedded processor cores, as well as configurable fabric that can be used to implement error detection and correction mechanisms. This paper presents an approach that aims at developing a safety- or mission-critical systems on programmable chip able to tolerate soft errors by exploiting processor duplication to implement error detection, as well as checkpoint and rollback recovery to correct errors in a cost-efficient manner. We developed a prototypical implementation of the proposed approach targeting the Leon processor core, and we collected preliminary results that outline the capability of the technique to tolerate soft errors affecting the processor's internal registers. This paper is the first step toward the definition of an automatic design flow for hardening processor cores (either hard of soft) embedded in programmable chips, like for example SRAM-based FPGAs.
{"title":"Recovery scheme for hardening system on programmable chips","authors":"C. Meinhardt, R. Reis, M. Violante, M. Reorda","doi":"10.1109/LATW.2009.4813816","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813816","url":null,"abstract":"The checkpoint and rollback recovery techniques enable a system to survive failures by periodically saving a known good snapshot of the system's state, and rolling back to it in case a failure is detected. The approach is particularly interesting for developing critical systems on programmable chips that today offers multiple embedded processor cores, as well as configurable fabric that can be used to implement error detection and correction mechanisms. This paper presents an approach that aims at developing a safety- or mission-critical systems on programmable chip able to tolerate soft errors by exploiting processor duplication to implement error detection, as well as checkpoint and rollback recovery to correct errors in a cost-efficient manner. We developed a prototypical implementation of the proposed approach targeting the Leon processor core, and we collected preliminary results that outline the capability of the technique to tolerate soft errors affecting the processor's internal registers. This paper is the first step toward the definition of an automatic design flow for hardening processor cores (either hard of soft) embedded in programmable chips, like for example SRAM-based FPGAs.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127948348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813784
T. Iwagaki, M. Kaneko
This paper discusses a test generation method to derive high quality transition tests for combinational circuits. It is known that, for a transition fault, a test set which propagates the errors (late transitions) to all the primary outputs reachable from the fault site can enhance the detectability of unmodeled defects. In this paper, to generate a minimum test set that meets the above property, the test generation problem is formulated as a problem of integer linear programming. The proposed formulation guarantees that minimum two-pattern tests for a transition fault are generated so that the errors will be observed at all the primary outputs reachable from the fault site. A case study using a benchmark circuit is presented to show the feasibility of the proposed method.
{"title":"On the derivation of a minimum test set in high quality transition testing","authors":"T. Iwagaki, M. Kaneko","doi":"10.1109/LATW.2009.4813784","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813784","url":null,"abstract":"This paper discusses a test generation method to derive high quality transition tests for combinational circuits. It is known that, for a transition fault, a test set which propagates the errors (late transitions) to all the primary outputs reachable from the fault site can enhance the detectability of unmodeled defects. In this paper, to generate a minimum test set that meets the above property, the test generation problem is formulated as a problem of integer linear programming. The proposed formulation guarantees that minimum two-pattern tests for a transition fault are generated so that the errors will be observed at all the primary outputs reachable from the fault site. A case study using a benchmark circuit is presented to show the feasibility of the proposed method.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116984580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813787
H. Chamorro, C. Bustos, L. A. Lopez
The proposal of this paper is demonstrating the simplicity to develop a real control position action over a platform on mobile vehicle using two different discrete controllers. The mechanical structure is depicted and the range of work operation. The characterization is based on an accelerometer in the X axis. The mathematical analysis of these controllers, classic control discrete PID and the second is a non linear position control with deadbeat response method is showed and its simulation. Finally the algorithms implemented in a microcontroller of each controller are depicted in a flowchart and the results are evaluated with the error index.
{"title":"Adaptive position digital control with deadbeat response for a platform on a mobile vehicle","authors":"H. Chamorro, C. Bustos, L. A. Lopez","doi":"10.1109/LATW.2009.4813787","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813787","url":null,"abstract":"The proposal of this paper is demonstrating the simplicity to develop a real control position action over a platform on mobile vehicle using two different discrete controllers. The mechanical structure is depicted and the range of work operation. The characterization is based on an accelerometer in the X axis. The mathematical analysis of these controllers, classic control discrete PID and the second is a non linear position control with deadbeat response method is showed and its simulation. Finally the algorithms implemented in a microcontroller of each controller are depicted in a flowchart and the results are evaluated with the error index.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116881814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813808
Ashkan Eghbal, H. Zarandi, Pooria M. Yaghini
In this paper the fault tolerance behavior of a PIC micro-controller has been concerned by fault injection method. This experiment is based on injection of 70 different transient faults in various points. The faults have been injected into a structural-level VHDL model. Repeating each experiment for 200 times, result in 14000 transient fault injections into model of this microcontroller. The experimental results have been compared in different aspects. Up to 50% of the injected faults cause system failure and also about 50% are recovered before changing into errors. Less than 1% of injected faults treat as latent errors. Program counter is distinguished as the most infected components after simulated comparisons. The failure rate of this part is near to 90%. Moreover, the controller and file register stand on the second and third status by the failure rates of 68% and 64%, respectively.
{"title":"Fault tolerance assessment of PIC microcontroller based on fault injection","authors":"Ashkan Eghbal, H. Zarandi, Pooria M. Yaghini","doi":"10.1109/LATW.2009.4813808","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813808","url":null,"abstract":"In this paper the fault tolerance behavior of a PIC micro-controller has been concerned by fault injection method. This experiment is based on injection of 70 different transient faults in various points. The faults have been injected into a structural-level VHDL model. Repeating each experiment for 200 times, result in 14000 transient fault injections into model of this microcontroller. The experimental results have been compared in different aspects. Up to 50% of the injected faults cause system failure and also about 50% are recovered before changing into errors. Less than 1% of injected faults treat as latent errors. Program counter is distinguished as the most infected components after simulated comparisons. The failure rate of this part is near to 90%. Moreover, the controller and file register stand on the second and third status by the failure rates of 68% and 64%, respectively.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115598677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813819
G. D. Natale, M. Flottes, B. Rouzeyre
Cryptographic devices can be subject to side-channel attacks that consist in retrieving secret data by observing physical properties of the device. Among those attacks, Differential Power Analysis (DPA) has proven to be very effective and easy to perform. Several countermeasures have been proposed in the literature and one of the most promising is based on power balanced design. There are still not known methods for manufacturing test of power balanced circuits, aside from performing full DPA. This paper proposes a novel method that allows to drastically reduce the number of input vectors used for the DPA, thus reducing the overall test time.
{"title":"Execution time reduction of Differential Power Analysis experiments","authors":"G. D. Natale, M. Flottes, B. Rouzeyre","doi":"10.1109/LATW.2009.4813819","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813819","url":null,"abstract":"Cryptographic devices can be subject to side-channel attacks that consist in retrieving secret data by observing physical properties of the device. Among those attacks, Differential Power Analysis (DPA) has proven to be very effective and easy to perform. Several countermeasures have been proposed in the literature and one of the most promising is based on power balanced design. There are still not known methods for manufacturing test of power balanced circuits, aside from performing full DPA. This paper proposes a novel method that allows to drastically reduce the number of input vectors used for the DPA, thus reducing the overall test time.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124803577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813815
Cristiano Rodrigues
eTPU is a state-of-the-art timing co-processor unit that aims to relief I/O processing in new advanced microcontroller units. It has characteristics of both a peripheral and a processor, which are tightly integrated, requiring a verification strategy that covers equally well both of these roles. This paper discusses the formal verification effort of some specific eTPU features. For newer versions of eTPU, some complexity increasing showed to be suitable for a formal verification approach. Formal Verification was now applied to verify recently added complex features. This approach is then compared with a simulation-only approach adopted earlier.
{"title":"A case study for Formal Verification of a timing co-processor","authors":"Cristiano Rodrigues","doi":"10.1109/LATW.2009.4813815","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813815","url":null,"abstract":"eTPU is a state-of-the-art timing co-processor unit that aims to relief I/O processing in new advanced microcontroller units. It has characteristics of both a peripheral and a processor, which are tightly integrated, requiring a verification strategy that covers equally well both of these roles. This paper discusses the formal verification effort of some specific eTPU features. For newer versions of eTPU, some complexity increasing showed to be suitable for a formal verification approach. Formal Verification was now applied to verify recently added complex features. This approach is then compared with a simulation-only approach adopted earlier.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121884570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813783
Luciano C. Ascari, L. Y. Araki, A. Pozo, S. Vergilio
Debugging is the most important task related to the testing activity. It has the goal of locating and removing a fault after a failure occurred during test. However, it is not a trivial task and generally consumes effort and time. Debugging techniques generally use testing information but usually they are very specific for certain domains, languages and development paradigms. Because of this, a Neural Network (NN) approach has been investigated with this goal. It is independent of the context and presented promising results for procedural code. However it was not validated in the context of Object-Oriented (OO) applications. In addition to this, the use of other Machine Learning techniques is also interesting, because they can be more efficient. With this in mind, the present work adapts the NN approach to the OO context and also explores the use of Support Vector Machines (SVMs). Results from the use of both techniques are presented and analysed. They show that their use contributes for easing the fault localization task.
{"title":"Exploring machine learning techniques for fault localization","authors":"Luciano C. Ascari, L. Y. Araki, A. Pozo, S. Vergilio","doi":"10.1109/LATW.2009.4813783","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813783","url":null,"abstract":"Debugging is the most important task related to the testing activity. It has the goal of locating and removing a fault after a failure occurred during test. However, it is not a trivial task and generally consumes effort and time. Debugging techniques generally use testing information but usually they are very specific for certain domains, languages and development paradigms. Because of this, a Neural Network (NN) approach has been investigated with this goal. It is independent of the context and presented promising results for procedural code. However it was not validated in the context of Object-Oriented (OO) applications. In addition to this, the use of other Machine Learning techniques is also interesting, because they can be more efficient. With this in mind, the present work adapts the NN approach to the OO context and also explores the use of Support Vector Machines (SVMs). Results from the use of both techniques are presented and analysed. They show that their use contributes for easing the fault localization task.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133881922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813818
Roberto Gómez, V. Champac, C. Hawkins, J. Segura
The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology [1–3]. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. This defect defies a guaranteed 100% detection. We will show that this mostly discarded failure mechanism is very relevant to modern ICs. Current leakage in nanoscale technologies influence significantly the behavior of this fault.
{"title":"A modern look at the CMOS stuck-open fault","authors":"Roberto Gómez, V. Champac, C. Hawkins, J. Segura","doi":"10.1109/LATW.2009.4813818","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813818","url":null,"abstract":"The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology [1–3]. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. This defect defies a guaranteed 100% detection. We will show that this mostly discarded failure mechanism is very relevant to modern ICs. Current leakage in nanoscale technologies influence significantly the behavior of this fault.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133237960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813791
M. Messing, Andreas Glowatz, F. Hapke, R. Drechsler
Automatic Test Pattern Generation (ATPG) is one of the core algorithms in testing of digital circuits and systems. Based on a given fault model a list of all faults to be tested, i.e. the fault list, is being created. For each fault in this list, one test pattern is generated (this pattern may cover other faults). Thereby, the order of the faults is crucial. In industrial ATPG, typically a simple list is used as fault list until today. In this work, we introduce a two-dimensional fault list and different strategies to order this list. The target is to reduce the number of generated patterns. The techniques are implemented in an industrial ATPG-framework. They are evaluated on industrial circuits. The results are discussed and a general purpose strategy is given.
{"title":"Using a two-dimensional fault list for compact Automatic Test Pattern Generation","authors":"M. Messing, Andreas Glowatz, F. Hapke, R. Drechsler","doi":"10.1109/LATW.2009.4813791","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813791","url":null,"abstract":"Automatic Test Pattern Generation (ATPG) is one of the core algorithms in testing of digital circuits and systems. Based on a given fault model a list of all faults to be tested, i.e. the fault list, is being created. For each fault in this list, one test pattern is generated (this pattern may cover other faults). Thereby, the order of the faults is crucial. In industrial ATPG, typically a simple list is used as fault list until today. In this work, we introduce a two-dimensional fault list and different strategies to order this list. The target is to reduce the number of generated patterns. The techniques are implemented in an industrial ATPG-framework. They are evaluated on industrial circuits. The results are discussed and a general purpose strategy is given.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129889443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813797
M. Portela-García, M. García-Valderas, C. López-Ongil, L. Entrena, B. Lestriez, L. Berrojo
Turbo Codes are used in satellites and deep-space exploration as an innovative solution for error control codes. Radiation effects could add noise levels above the correction capability of the wireless communication modules, even though turbo codes were assuring low Bit Error Rates. SEU effects in the BER of a Turbo Decoder intended for space applications has been analyzed in detail, injecting millions of faults by means of using an Autonomous Emulation System.
{"title":"Study of SEU effects in a Turbo Decoder Bit Error Rate","authors":"M. Portela-García, M. García-Valderas, C. López-Ongil, L. Entrena, B. Lestriez, L. Berrojo","doi":"10.1109/LATW.2009.4813797","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813797","url":null,"abstract":"Turbo Codes are used in satellites and deep-space exploration as an innovative solution for error control codes. Radiation effects could add noise levels above the correction capability of the wireless communication modules, even though turbo codes were assuring low Bit Error Rates. SEU effects in the BER of a Turbo Decoder intended for space applications has been analyzed in detail, injecting millions of faults by means of using an Autonomous Emulation System.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"37 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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