Pub Date : 2023-07-20DOI: 10.1142/s012915642350012x
R. Gudlavalleti, E. Heller, J. Chandy, F. Jain
This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.
{"title":"Compute-in-Memory SRAM Cell Using Multistate Spatial Wavefunction Switched (SWS)-Quantum Dot Channel (QDC) FET","authors":"R. Gudlavalleti, E. Heller, J. Chandy, F. Jain","doi":"10.1142/s012915642350012x","DOIUrl":"https://doi.org/10.1142/s012915642350012x","url":null,"abstract":"This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46813244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500064
Maruf Hossain, Md. Maruf Hossain Shuvo, Twisha Titirsha, S. K. Islam
This paper presents technology computer-aided design (TCAD) modeling of an enhancement-mode aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) with extensive π-gate optimization for high-power and radio frequency (RF) applications. Effects of the gate voltages on threshold (Vth), transconductance (gm), breakdown voltage (VBR), cutoff frequency (fT), maximum frequency of oscillation (fmax) and minimum noise figure (NFmin) are systematically investigated with different gate structures (π–Shaped p-GaN MISHEMT, π–Shaped p-GaN HEMT, π–Gate HEMT). A comparative study demonstrates that π–Gate with additional p-GaN and insulating layer makes the device effectively operate in the enhancement mode having a threshold voltage (Vth) = 1.72 V with a breakdown voltage (VBR) = 341 V, exhibiting better gate control with maximum transconductance (gm,max) of 0.321 S/mm. In addition, the proposed device architecture with an optimized gate structure maintains a balance between a positive device threshold and a high breakdown voltage and achieves a better noise immunity with the minimum noise figure of 0.64 dB while operating at 10 GHz with a cutoff frequency (fT) of 33.4 GHz, and a maximum stable operating frequency (fmax) of 82.3 GHz. Moreover, the device achieved an outstanding Vth, gm,max, VBR, fT, fmax and NFmin making it suitable for high-power, high-speed electronics, and low-noise amplifiers.
{"title":"Modeling of Enhancement Mode HEMT with Π-Gate Optimization for High Power Applications","authors":"Maruf Hossain, Md. Maruf Hossain Shuvo, Twisha Titirsha, S. K. Islam","doi":"10.1142/s0129156423500064","DOIUrl":"https://doi.org/10.1142/s0129156423500064","url":null,"abstract":"This paper presents technology computer-aided design (TCAD) modeling of an enhancement-mode aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) with extensive π-gate optimization for high-power and radio frequency (RF) applications. Effects of the gate voltages on threshold (Vth), transconductance (gm), breakdown voltage (VBR), cutoff frequency (fT), maximum frequency of oscillation (fmax) and minimum noise figure (NFmin) are systematically investigated with different gate structures (π–Shaped p-GaN MISHEMT, π–Shaped p-GaN HEMT, π–Gate HEMT). A comparative study demonstrates that π–Gate with additional p-GaN and insulating layer makes the device effectively operate in the enhancement mode having a threshold voltage (Vth) = 1.72 V with a breakdown voltage (VBR) = 341 V, exhibiting better gate control with maximum transconductance (gm,max) of 0.321 S/mm. In addition, the proposed device architecture with an optimized gate structure maintains a balance between a positive device threshold and a high breakdown voltage and achieves a better noise immunity with the minimum noise figure of 0.64 dB while operating at 10 GHz with a cutoff frequency (fT) of 33.4 GHz, and a maximum stable operating frequency (fmax) of 82.3 GHz. Moreover, the device achieved an outstanding Vth, gm,max, VBR, fT, fmax and NFmin making it suitable for high-power, high-speed electronics, and low-noise amplifiers.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49277005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500118
R. Dougenik, R. Lacomb, F. Jain
A novel gain and index tailored (GIT) external cavity laser (ECL) is presented. The single frequency laser demonstrates high power operation in excess of 250 mW and shot noise limited relative intensity noise (RIN) at 100 mW. This laser source is an ideal source for intensity-modulated direct detection (IMDD) photonic links. Link budget analysis is completed based on measured RIN and optical power. The analysis demonstrates that there are significant radio frequency performance advantages to operating at higher optical power while maintaining low RIN.
{"title":"Low Noise Gain and Index Tailored External Cavity Laser Operating at 1310 nm for Performance Enhancements of IMDD Photonic Links","authors":"R. Dougenik, R. Lacomb, F. Jain","doi":"10.1142/s0129156423500118","DOIUrl":"https://doi.org/10.1142/s0129156423500118","url":null,"abstract":"A novel gain and index tailored (GIT) external cavity laser (ECL) is presented. The single frequency laser demonstrates high power operation in excess of 250 mW and shot noise limited relative intensity noise (RIN) at 100 mW. This laser source is an ideal source for intensity-modulated direct detection (IMDD) photonic links. Link budget analysis is completed based on measured RIN and optical power. The analysis demonstrates that there are significant radio frequency performance advantages to operating at higher optical power while maintaining low RIN.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49382425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500076
Shunyao Fan, A. F. M. Moshiur Rahman, N. Dutta
In this paper, we propose a scheme for high-speed all-optical Pseudo-Random Binary Sequence (PRBS) generator and use it for generating keystream for encryption. This PRBS generator design is based on Linear Feedback Shift Registers (LFSR) and optical XOR and AND gates. The optical logical gates are based on quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI). With two photon absorption (TPA) in quantum dot-semiconductor optical amplifier (QD-SOA), this kind of optical logic gates performs well when processing data in an ultra-fast timescale and therefore able to function as high speed PRBS generator. Result shows that it’s possible for this scheme to realize all-optical encryption and decryption at high process rate up to 320 Gb/s. We simulated different ways of generating keystream with schemes such as cascaded generator, parallel generator and alternating step generator. These generators use more than one LFSR. Result shows that the schemes we use can function as stable and complex keystream generators.
{"title":"Encryption Using Optical Pseudo-Random Binary Sequence Based on Optical Logic Gate","authors":"Shunyao Fan, A. F. M. Moshiur Rahman, N. Dutta","doi":"10.1142/s0129156423500076","DOIUrl":"https://doi.org/10.1142/s0129156423500076","url":null,"abstract":"In this paper, we propose a scheme for high-speed all-optical Pseudo-Random Binary Sequence (PRBS) generator and use it for generating keystream for encryption. This PRBS generator design is based on Linear Feedback Shift Registers (LFSR) and optical XOR and AND gates. The optical logical gates are based on quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI). With two photon absorption (TPA) in quantum dot-semiconductor optical amplifier (QD-SOA), this kind of optical logic gates performs well when processing data in an ultra-fast timescale and therefore able to function as high speed PRBS generator. Result shows that it’s possible for this scheme to realize all-optical encryption and decryption at high process rate up to 320 Gb/s. We simulated different ways of generating keystream with schemes such as cascaded generator, parallel generator and alternating step generator. These generators use more than one LFSR. Result shows that the schemes we use can function as stable and complex keystream generators.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43613932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500222
R. Dougenik, R. Lacomb, F. Jain
A novel magnetostrictive thin film fiber sensor is presented which can be utilized in an interferometric architecture. The magnetostrictive fiber sensor utilizes novel fiber and thin film technology to achieve high sensitivity in the sub-nanotesla regime. The base sensor architecture utilizes optical fiber wound in a novel low stress flat coil resembling a record, coated with a thin magnetostrictive film. Two prototype variants were fabricated, incorporating FeCo sputtered films of different thicknesses on 4 μm polyimide jacket single mode fiber. The sensors were incorporated into a fiber optic interferometric measurement apparatus to characterize time-varying magnetic field sensitivity. Device results are presented which demonstrate sensitivity is a function of film thickness. The experimental data exhibited a two-order magnitude sensitivity improvement as the thin film thickness was doubled. Sensitivity projections are made based on film thickness.
{"title":"Magnetostrictive Fiber Sensors as Total Field Magnetometers","authors":"R. Dougenik, R. Lacomb, F. Jain","doi":"10.1142/s0129156423500222","DOIUrl":"https://doi.org/10.1142/s0129156423500222","url":null,"abstract":"A novel magnetostrictive thin film fiber sensor is presented which can be utilized in an interferometric architecture. The magnetostrictive fiber sensor utilizes novel fiber and thin film technology to achieve high sensitivity in the sub-nanotesla regime. The base sensor architecture utilizes optical fiber wound in a novel low stress flat coil resembling a record, coated with a thin magnetostrictive film. Two prototype variants were fabricated, incorporating FeCo sputtered films of different thicknesses on 4 μm polyimide jacket single mode fiber. The sensors were incorporated into a fiber optic interferometric measurement apparatus to characterize time-varying magnetic field sensitivity. Device results are presented which demonstrate sensitivity is a function of film thickness. The experimental data exhibited a two-order magnitude sensitivity improvement as the thin film thickness was doubled. Sensitivity projections are made based on film thickness.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48191469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500209
F. Nasri, Husien Salama
This paper investigates the non-Fourier transient heat transfer in an SOI FinFET transistor. The calibrated drift-diffusion (D-D) model in conjunction with the ballistic diffusive (BDE) model is used as an electrothermal model to predict phonon and electron transports in the quasi-ballistic regime. The finite element method has been employed to generate the numerical results. The proposed mathematical formulation was found to capture the transfer characteristics and the temporal temperature as given by TCAD simulation and experimental data. On the other hand, we have demonstrated that after 100 ns, the 14 nm Bulk FinFET supports better temperature distribution than the 14 nm SOI FinFET.
本文研究了SOI FinFET晶体管的非傅立叶瞬态传热。校准漂移扩散(D-D)模型结合弹道扩散(BDE)模型作为电热模型用于预测准弹道状态下声子和电子的输运。采用有限元法进行了数值模拟。通过TCAD仿真和实验数据，发现所提出的数学公式能很好地反映传热特性和时间温度。另一方面，我们已经证明，在100 ns后，14 nm Bulk FinFET比14 nm SOI FinFET支持更好的温度分布。
{"title":"Numerical Investigation of the Electrothermal Properties of SOI FinFET Transistor","authors":"F. Nasri, Husien Salama","doi":"10.1142/s0129156423500209","DOIUrl":"https://doi.org/10.1142/s0129156423500209","url":null,"abstract":"This paper investigates the non-Fourier transient heat transfer in an SOI FinFET transistor. The calibrated drift-diffusion (D-D) model in conjunction with the ballistic diffusive (BDE) model is used as an electrothermal model to predict phonon and electron transports in the quasi-ballistic regime. The finite element method has been employed to generate the numerical results. The proposed mathematical formulation was found to capture the transfer characteristics and the temporal temperature as given by TCAD simulation and experimental data. On the other hand, we have demonstrated that after 100 ns, the 14 nm Bulk FinFET supports better temperature distribution than the 14 nm SOI FinFET.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43832189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s012915642399001x
{"title":"Author Index: Volume 32 (2023)","authors":"","doi":"10.1142/s012915642399001x","DOIUrl":"https://doi.org/10.1142/s012915642399001x","url":null,"abstract":"","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48821253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-13DOI: 10.1142/s012915642350009x
A. Almalki, B. Saman, R. Gudlavalleti, J. Chandy, E. Heller, F. Jain
This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeOx-Ge/ SiOx-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.
{"title":"Design and Simulation of Multi-State D-Latch Circuit Using QDC-SWS FETs","authors":"A. Almalki, B. Saman, R. Gudlavalleti, J. Chandy, E. Heller, F. Jain","doi":"10.1142/s012915642350009x","DOIUrl":"https://doi.org/10.1142/s012915642350009x","url":null,"abstract":"This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeOx-Ge/ SiOx-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45836215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1142/s0129156423500015
Vijay Kumar, V. Jain
The lifecycle of the battery is mostly exaggerated by the overall energy throughput speed, accumulated heat, and rapid utilization. The adequate utilization and operation of the battery are improved in the flexibility range by the permutation of the battery and the ultracapacitor in the electric vehicle. The overall system performance is determined by the energy management system which plays a significant part in dual-energy storage systems. The major intent of this research is to enhance the performance of electric vehicles which is achieved by maintaining the charge of depleting and charge of sustaining level in the battery and the state of charge in the ultracapacitor. The proposed method controls the state of charge of the battery and the ultracapacitor to make sure the availability of charge throughout the complete settling rate of the battery in the electric vehicle. To attain this condition, the dual converter-based two-stage Artificial Neural Network is initialized. In the first stage of the Artificial Neural Network, the charge sustained in the ultracapacitor is controlled during acceleration which completely depends on the velocity of the vehicles. In contrast to that, in the second stage of the Artificial Neural Network, charge depleting in the UC is trained by connectionless with varying vehicle velocities at deceleration rates. The production and investigation of parameters are not effectively optimized using conventional methods hence the herding and howling characters are combined together and proposed energetic and problem-solving optimization-based metaheuristic algorithm that efficiently tunes the parameters. The SOC rate of the battery for three driving cycles using the proposed method follows FTP75 71.309% at 2474th s and J1015 attained 90.840% at 660th s and the UDDS attained 81.647%. The SOC rate of the Ultracapacitor for three driving cycles using the proposed method follows FTP75 63.518% at 2474 s, J1015 attained 69.332% at 660 s and UDDs attained 67.049%. The experimental arrangement is executed in MATLAB-Simulink. The state of charge of the battery and the ultracapacitors for the varying drive cycles as FTP75, J1015, and UDDS are experimentally validated and verified with the prevailing methods. The developed method reveals better performance for enhancing the lifespan of the power storeroom system in electric vehicles.
{"title":"An Advanced Ultracapacitor SOC Concept to Increase Battery Life Span of Electric Vehicles","authors":"Vijay Kumar, V. Jain","doi":"10.1142/s0129156423500015","DOIUrl":"https://doi.org/10.1142/s0129156423500015","url":null,"abstract":"The lifecycle of the battery is mostly exaggerated by the overall energy throughput speed, accumulated heat, and rapid utilization. The adequate utilization and operation of the battery are improved in the flexibility range by the permutation of the battery and the ultracapacitor in the electric vehicle. The overall system performance is determined by the energy management system which plays a significant part in dual-energy storage systems. The major intent of this research is to enhance the performance of electric vehicles which is achieved by maintaining the charge of depleting and charge of sustaining level in the battery and the state of charge in the ultracapacitor. The proposed method controls the state of charge of the battery and the ultracapacitor to make sure the availability of charge throughout the complete settling rate of the battery in the electric vehicle. To attain this condition, the dual converter-based two-stage Artificial Neural Network is initialized. In the first stage of the Artificial Neural Network, the charge sustained in the ultracapacitor is controlled during acceleration which completely depends on the velocity of the vehicles. In contrast to that, in the second stage of the Artificial Neural Network, charge depleting in the UC is trained by connectionless with varying vehicle velocities at deceleration rates. The production and investigation of parameters are not effectively optimized using conventional methods hence the herding and howling characters are combined together and proposed energetic and problem-solving optimization-based metaheuristic algorithm that efficiently tunes the parameters. The SOC rate of the battery for three driving cycles using the proposed method follows FTP75 71.309% at 2474th s and J1015 attained 90.840% at 660th s and the UDDS attained 81.647%. The SOC rate of the Ultracapacitor for three driving cycles using the proposed method follows FTP75 63.518% at 2474 s, J1015 attained 69.332% at 660 s and UDDs attained 67.049%. The experimental arrangement is executed in MATLAB-Simulink. The state of charge of the battery and the ultracapacitors for the varying drive cycles as FTP75, J1015, and UDDS are experimentally validated and verified with the prevailing methods. The developed method reveals better performance for enhancing the lifespan of the power storeroom system in electric vehicles.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46052239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1142/s0129156423500027
K. Sharma, Aveksha Sharma, R. Pandey, Jaya Madan
Achieving high-gain and low-noise operation of bulk-driven (BD) operational transconductance amplifier (OTA) with low-power consumption is a challenging task owing to inherent low transconductance and high noise in BD MOSFET. In this paper, we report a self-cascode partial positive feedback (SCPPF) approach-based BD OTA and have fairly compared the results with regular single MOS partial positive feedback (PPF) approach-based BD OTA. In comparison to regular BD PPF OTA, the proposed BD SCPPF OTA yields an improved gain of 68.71 dB, gain-bandwidth of 39.4 kHz, power consumption of 630 nW, output impedance of 0.4 MΩ and common mode rejection ratio of 134.4 dB for same input referred noise of 1.11 μV/√ Hz at frequency of 10 Hz and supply voltage of ±0.5 V. The area consumed by BD SCPPF OTA is 0.0523 mm2. The proposed BD SCPPF OTA can be possibly used to improve the performance of biomedical analog front-end sensing and signal processing systems.
{"title":"Design and Analysis of Low-Power Bulk-Driven Operational Transconductance Amplifier: A Self-Cascode Partial Positive Feedback Approach","authors":"K. Sharma, Aveksha Sharma, R. Pandey, Jaya Madan","doi":"10.1142/s0129156423500027","DOIUrl":"https://doi.org/10.1142/s0129156423500027","url":null,"abstract":"Achieving high-gain and low-noise operation of bulk-driven (BD) operational transconductance amplifier (OTA) with low-power consumption is a challenging task owing to inherent low transconductance and high noise in BD MOSFET. In this paper, we report a self-cascode partial positive feedback (SCPPF) approach-based BD OTA and have fairly compared the results with regular single MOS partial positive feedback (PPF) approach-based BD OTA. In comparison to regular BD PPF OTA, the proposed BD SCPPF OTA yields an improved gain of 68.71 dB, gain-bandwidth of 39.4 kHz, power consumption of 630 nW, output impedance of 0.4 MΩ and common mode rejection ratio of 134.4 dB for same input referred noise of 1.11 μV/√ Hz at frequency of 10 Hz and supply voltage of ±0.5 V. The area consumed by BD SCPPF OTA is 0.0523 mm2. The proposed BD SCPPF OTA can be possibly used to improve the performance of biomedical analog front-end sensing and signal processing systems.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46115990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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