Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522923
A. Moeini, Shuo Wang
This paper proposes a real time selective harmonic elimination technique for the current of the active rectifier. The partial derivation technique is applied to the Fourier series equations of voltage waveforms to implement real time SHE technique. In order to control the magnitude and phase of the low order current harmonics of the active rectifier, a new controller is proposed to fully mitigate the 5th and 7th current harmonic orders of the active rectifier even with the influence of grid voltage harmonics. Moreover, in this paper, an asymmetric voltage waveform will be employed to control both the magnitude and phase of the current harmonics of the active rectifier. The proposed technique needs very low memory storage for look-up tables, so it saves a lot of resources for DSP. Finally, the proposed technique is verified by MATLAB/Simulink simulations and experiments. The technique can be extended to eliminate more orders of harmonics.
{"title":"Asymmetric selective harmonic elimination technique using partial derivative for cascaded modular active rectifiers tied to a power grid with voltage harmonics","authors":"A. Moeini, Shuo Wang","doi":"10.1109/APEMC.2016.7522923","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522923","url":null,"abstract":"This paper proposes a real time selective harmonic elimination technique for the current of the active rectifier. The partial derivation technique is applied to the Fourier series equations of voltage waveforms to implement real time SHE technique. In order to control the magnitude and phase of the low order current harmonics of the active rectifier, a new controller is proposed to fully mitigate the 5th and 7th current harmonic orders of the active rectifier even with the influence of grid voltage harmonics. Moreover, in this paper, an asymmetric voltage waveform will be employed to control both the magnitude and phase of the current harmonics of the active rectifier. The proposed technique needs very low memory storage for look-up tables, so it saves a lot of resources for DSP. Finally, the proposed technique is verified by MATLAB/Simulink simulations and experiments. The technique can be extended to eliminate more orders of harmonics.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134549507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522821
M. Coenen, Ye Ming, Huichun Yu, Li Ension
System Efficient ESD Design (SEED) requires dynamic behavior models from the devices and circuitry used along the protection chain, typically from the discharge point of entry at the PCB boundary i.e. connector up to the circuits on-chip to be protected. In-between this path there may be external ESD protection i.e. voltage clamping together with parasitic layout effects, interconnect path delay with specific transmission line properties, package design up to on-chip protection design with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being unpowered or powered.
{"title":"Dynamic behavior model for SEED analysis; extraction using surface response modelling","authors":"M. Coenen, Ye Ming, Huichun Yu, Li Ension","doi":"10.1109/APEMC.2016.7522821","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522821","url":null,"abstract":"System Efficient ESD Design (SEED) requires dynamic behavior models from the devices and circuitry used along the protection chain, typically from the discharge point of entry at the PCB boundary i.e. connector up to the circuits on-chip to be protected. In-between this path there may be external ESD protection i.e. voltage clamping together with parasitic layout effects, interconnect path delay with specific transmission line properties, package design up to on-chip protection design with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being unpowered or powered.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133396731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522748
Jianquan Lou, Q. Sun, W. You, Yingchun Shu, A. Bhobe, Yuan Jinghan
Flyback converter is widely used for its high efficiency. However due to fast switching currents and voltages, it can cause high conducted emissions in a system. In this paper we present a method to characterize the EMI noise generation and the coupling mechanism in flyback converters. We also derive analytical formulae to calculate the frequency and amplitude of this EMI noise, which provides an easy way to predict EMI noise in early design stage. The results calculated by formulae are compared with simulation and agree well. A new standard filter design procedure for flyback converter is proposed based on these analytical formulae, which can help to mitigate electromagnetic compatibility (EMC) risk in the beginning of the project.
{"title":"Analytical calculation of conducted EMI in flyback converters","authors":"Jianquan Lou, Q. Sun, W. You, Yingchun Shu, A. Bhobe, Yuan Jinghan","doi":"10.1109/APEMC.2016.7522748","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522748","url":null,"abstract":"Flyback converter is widely used for its high efficiency. However due to fast switching currents and voltages, it can cause high conducted emissions in a system. In this paper we present a method to characterize the EMI noise generation and the coupling mechanism in flyback converters. We also derive analytical formulae to calculate the frequency and amplitude of this EMI noise, which provides an easy way to predict EMI noise in early design stage. The results calculated by formulae are compared with simulation and agree well. A new standard filter design procedure for flyback converter is proposed based on these analytical formulae, which can help to mitigate electromagnetic compatibility (EMC) risk in the beginning of the project.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115590862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522966
Yanfei Dong, Peiguo Liu
Electromagnetic band-gap (EBG) structure could effectively control electromagnetic wave propagation. In this paper, we proposed two kinds of electromagnetic band-gap structure. The proposed graphene EBG adopts square open-loop shape on ground planes, which displays good characteristics in dynamically adjusting the electromagnetic wave propagation in terahertz range. The same characteristics are retrieved in circular column electromagnetic band-gap based on graphene stack due to tunable dielectric property. The prototype structures are expected to use for potential terahertz devices.
{"title":"Applications of graphene in terahertz electromagnetic band-gap structure designs","authors":"Yanfei Dong, Peiguo Liu","doi":"10.1109/APEMC.2016.7522966","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522966","url":null,"abstract":"Electromagnetic band-gap (EBG) structure could effectively control electromagnetic wave propagation. In this paper, we proposed two kinds of electromagnetic band-gap structure. The proposed graphene EBG adopts square open-loop shape on ground planes, which displays good characteristics in dynamically adjusting the electromagnetic wave propagation in terahertz range. The same characteristics are retrieved in circular column electromagnetic band-gap based on graphene stack due to tunable dielectric property. The prototype structures are expected to use for potential terahertz devices.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115630152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522945
Miaomiao Ma, D. Jiao
We represent the dense system of volume integral equations (VIE) by an HSS (Hierarchically Semiseparable) matrix. We then develop a fast direct VIE solver of O(N) (linear) complexity, including both factorization and inversion, for the extraction of large-scale interconnects involving lossy conductors and inhomogeneous materials. The HSS-representation has a controlled accuracy; and the direct solution of the HSS matrix does not involve any further approximation. Numerical simulations of large-scale interconnects involving millions of unknowns on a single core CPU have demonstrated the superior performance of the proposed direct solver.
{"title":"Fast exact-arithmetic O(N) direct volume integral equation solver for large-scale interconnect extraction","authors":"Miaomiao Ma, D. Jiao","doi":"10.1109/APEMC.2016.7522945","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522945","url":null,"abstract":"We represent the dense system of volume integral equations (VIE) by an HSS (Hierarchically Semiseparable) matrix. We then develop a fast direct VIE solver of O(N) (linear) complexity, including both factorization and inversion, for the extraction of large-scale interconnects involving lossy conductors and inhomogeneous materials. The HSS-representation has a controlled accuracy; and the direct solution of the HSS matrix does not involve any further approximation. Numerical simulations of large-scale interconnects involving millions of unknowns on a single core CPU have demonstrated the superior performance of the proposed direct solver.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"117 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522816
Shijun Yang, Qingbin Chen, Wei Chen
Sandwich winding is usually used for low conduction loss and low leakage inductance in insolated converters. But it also tends to deteriorate the common mode (CM) EMI noise because of the bigger parasitic capacitances between primary and secondary windings. This paper analyzes the CM noise transferring path for typical isolated converters. Influence of different ground point location of the shielding on CM noise is investigated. A novel CM noise reduction method by optimizing the spacing between shielding and windings is proposed. The advantages of the proposed concepts and strategies are verified and demonstrated on a Fly-back converter. More than 20dB CM noise attenuation is achieved.
{"title":"Common mode EMI noise reduction technique by shielding optimization in isolated converters","authors":"Shijun Yang, Qingbin Chen, Wei Chen","doi":"10.1109/APEMC.2016.7522816","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522816","url":null,"abstract":"Sandwich winding is usually used for low conduction loss and low leakage inductance in insolated converters. But it also tends to deteriorate the common mode (CM) EMI noise because of the bigger parasitic capacitances between primary and secondary windings. This paper analyzes the CM noise transferring path for typical isolated converters. Influence of different ground point location of the shielding on CM noise is investigated. A novel CM noise reduction method by optimizing the spacing between shielding and windings is proposed. The advantages of the proposed concepts and strategies are verified and demonstrated on a Fly-back converter. More than 20dB CM noise attenuation is achieved.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116963182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522743
Xinjun Zhang, Weifeng Shu, Yinglei Ren, Ye Chunfei, Ye Xiaoning
Re-drivers are widely used in extending the solution space in high speed applications. However, recent lab data shows that the ambient temperature variation can lead to ~40mV degradation of the eye height at the receiver side on single re-driver system. In this paper, the authors will share key learnings of thermal impact on systems with both single re-driver and cascaded re-drivers. From these cases, the eye height is greatly reduced when temperature increases. This variation is due to resistance shifting of the output buffer, while most re-driver models do not account for it. An effective approach is applied to fine tune the equalization settings in the cascaded re-driver system. The learnings, together with the proposed approach, can help designers to design a robust, high performance, and cost-effective high speed link with re-drivers such as SAS-3, SATA-3, PCIe and USB, etc.
{"title":"Signal integrity performance degradation due to temperature variation in systems with re-drivers","authors":"Xinjun Zhang, Weifeng Shu, Yinglei Ren, Ye Chunfei, Ye Xiaoning","doi":"10.1109/APEMC.2016.7522743","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522743","url":null,"abstract":"Re-drivers are widely used in extending the solution space in high speed applications. However, recent lab data shows that the ambient temperature variation can lead to ~40mV degradation of the eye height at the receiver side on single re-driver system. In this paper, the authors will share key learnings of thermal impact on systems with both single re-driver and cascaded re-drivers. From these cases, the eye height is greatly reduced when temperature increases. This variation is due to resistance shifting of the output buffer, while most re-driver models do not account for it. An effective approach is applied to fine tune the equalization settings in the cascaded re-driver system. The learnings, together with the proposed approach, can help designers to design a robust, high performance, and cost-effective high speed link with re-drivers such as SAS-3, SATA-3, PCIe and USB, etc.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117170483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522910
Yaqi Yang, Zhibin Zhao, S. Gu, Di Li, Xiangxue Zeng
This paper analyzes the surge interference of the port of smart subassembly for potential difference of the grid while lightning strike on the metal framework of smart substation. The difference between the smart substation with conventional substations while direct lightning stroke is compared, and the influences are summarized.
{"title":"Analysis of the effect on smart subassembly in smart substation for lightning strike metal framework","authors":"Yaqi Yang, Zhibin Zhao, S. Gu, Di Li, Xiangxue Zeng","doi":"10.1109/APEMC.2016.7522910","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522910","url":null,"abstract":"This paper analyzes the surge interference of the port of smart subassembly for potential difference of the grid while lightning strike on the metal framework of smart substation. The difference between the smart substation with conventional substations while direct lightning stroke is compared, and the influences are summarized.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7523014
Bing Li, Junjun Wang, Xinwei Song, D. Su
A general circuit model for the field-wire coupling effect of electrically small irregular wire structures of various geometries is proposed in this paper. The formulas for the circuit elements are presented in analytical form and the limitations are discussed in detail. Finally, the model is validated on three typical cases by comparing the coupling currents on the terminal load with the counterpart by the method of moments.
{"title":"Circuit model for field-wire coupling of electrically small irregular wire structures","authors":"Bing Li, Junjun Wang, Xinwei Song, D. Su","doi":"10.1109/APEMC.2016.7523014","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7523014","url":null,"abstract":"A general circuit model for the field-wire coupling effect of electrically small irregular wire structures of various geometries is proposed in this paper. The formulas for the circuit elements are presented in analytical form and the limitations are discussed in detail. Finally, the model is validated on three typical cases by comparing the coupling currents on the terminal load with the counterpart by the method of moments.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123121810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-17DOI: 10.1109/APEMC.2016.7522852
Ming-Min Su, Peiguo Liu
In this paper, a parameter optimized locally one-dimensional finite-difference time-domain (LOD-FDTD) method using simulated annealing algorithms is presented. In the proposed method, the parameter optimized LOD-FDTD method can reduce the normalized numerical phase velocity error for arbitrary incident wave angles, for different spatial-step size and for time-step sizes. The results show that the proposed method is unconditionally stable. Compared with literature result, this method can minimize more dispersion error.
{"title":"A global optimized parameter to reduce the numerical dispersion of the LOD-FDTD method","authors":"Ming-Min Su, Peiguo Liu","doi":"10.1109/APEMC.2016.7522852","DOIUrl":"https://doi.org/10.1109/APEMC.2016.7522852","url":null,"abstract":"In this paper, a parameter optimized locally one-dimensional finite-difference time-domain (LOD-FDTD) method using simulated annealing algorithms is presented. In the proposed method, the parameter optimized LOD-FDTD method can reduce the normalized numerical phase velocity error for arbitrary incident wave angles, for different spatial-step size and for time-step sizes. The results show that the proposed method is unconditionally stable. Compared with literature result, this method can minimize more dispersion error.","PeriodicalId":358257,"journal":{"name":"2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123129036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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