A phase-locked loop (PLL) MMIC based on a ring-type injection-locked frequency divider (RILFD) and a cascode-type voltage-controlled oscillator (VCO) has been manufactured by using 0.5 mum enhanced/depletion mode (E/D) GaAs pHEMTs for Ka-band communications. In this circuit, the 15 GHz cascode oscillator including the 2nd harmonic cascode buffer amplifier was designed to generate a 30 GHz output signal. To synchronize the oscillation signal with the input reference signal, the wide locking-range divided-by-four RILFD using injection-locked technique and the cascode mixer to be a phase detector were used with a reference signal of 3.75 GHz. With a RC low-pass filter and a dc amplifier based on the E/D-mode inverter circuit, the loop gain and the output phase noise can be further improved. The measured result of the locking range is about 400 MHz near 30 GHz and the output phase noise is about -116 dBc/Hz at 1 MHz offset under a 2 V dc supply with 80 mW power consumption.
{"title":"A 30 GHz Single-Chip PLL MMIC Using 0.5 um Enhanced/Depletion-Mode GaAs pHEMT","authors":"F. Huang, Cheng-Kuo Lin, Yu-Chi Wang, Y. Chan","doi":"10.1109/CSICS07.2007.43","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.43","url":null,"abstract":"A phase-locked loop (PLL) MMIC based on a ring-type injection-locked frequency divider (RILFD) and a cascode-type voltage-controlled oscillator (VCO) has been manufactured by using 0.5 mum enhanced/depletion mode (E/D) GaAs pHEMTs for Ka-band communications. In this circuit, the 15 GHz cascode oscillator including the 2nd harmonic cascode buffer amplifier was designed to generate a 30 GHz output signal. To synchronize the oscillation signal with the input reference signal, the wide locking-range divided-by-four RILFD using injection-locked technique and the cascode mixer to be a phase detector were used with a reference signal of 3.75 GHz. With a RC low-pass filter and a dc amplifier based on the E/D-mode inverter circuit, the loop gain and the output phase noise can be further improved. The measured result of the locking range is about 400 MHz near 30 GHz and the output phase noise is about -116 dBc/Hz at 1 MHz offset under a 2 V dc supply with 80 mW power consumption.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124055986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Prikhodko, Y. Tkachenko, R. Srinivasan, Y. Zhu, J. Mason, S. Sprinkle, S. Nabokin, J. Chiesa
The theoretical background and hardware implementation of optimal matching filters designed to minimize harmonic generation by RF switches and provide harmonic filtering of the PA generated harmonics is presented. The switch with the optimally matched filters shows 5-7 dB improvements in harmonics generated under high VSWR, leading to better than -39dBm harmonics at 35/33 dBm for all phases of VSWR=5:1 for low/high band GSM applications. This technique leads to a fully integrated solution offering both improved harmonics performance and reduced size.
{"title":"Optimum Matching Technique for the Switch Design","authors":"D. Prikhodko, Y. Tkachenko, R. Srinivasan, Y. Zhu, J. Mason, S. Sprinkle, S. Nabokin, J. Chiesa","doi":"10.1109/CSICS07.2007.35","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.35","url":null,"abstract":"The theoretical background and hardware implementation of optimal matching filters designed to minimize harmonic generation by RF switches and provide harmonic filtering of the PA generated harmonics is presented. The switch with the optimally matched filters shows 5-7 dB improvements in harmonics generated under high VSWR, leading to better than -39dBm harmonics at 35/33 dBm for all phases of VSWR=5:1 for low/high band GSM applications. This technique leads to a fully integrated solution offering both improved harmonics performance and reduced size.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132918931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 40W GaN HEMT Doherty power amplifier (PA) for 2.5GHz band was developed. The Doherty PA was designed using large signal GaN HEMT models, and demonstrated a saturation output power of 54dBm (250W) and a drain efficiency of more than 60%. The measurement result shows good agreement with the large signal simulation result. We also investigated the Doherty PA linearity with digital pre-distortion (DPD) system, and obtained a drain efficiency of 48%, an ACLR of -53dBc and a power gain of 13.4dB at the average output power of 46dBm (40W) with 64QAM modulation signal. These superior performances show good suitability for 2.5GHz band WiMAX base stations.
研制了一种用于2.5GHz频段的40W GaN HEMT Doherty功率放大器。Doherty PA采用大信号GaN HEMT模型设计，饱和输出功率为54dBm (250W)，漏极效率超过60%。测量结果与大信号仿真结果吻合较好。我们还研究了数字预失真(DPD)系统的Doherty PA线性度，在64QAM调制信号的平均输出功率为46dBm (40W)时，漏极效率为48%，ACLR为-53dBc，功率增益为13.4dB。这些优越的性能显示出良好的适用于2.5GHz频段WiMAX基站。
{"title":"A 40W GaN HEMT Doherty Power Amplifier with 48% Efficiency for WiMAX Applications","authors":"H. Sano, N. Ui, S. Sano","doi":"10.1109/CSICS07.2007.15","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.15","url":null,"abstract":"A 40W GaN HEMT Doherty power amplifier (PA) for 2.5GHz band was developed. The Doherty PA was designed using large signal GaN HEMT models, and demonstrated a saturation output power of 54dBm (250W) and a drain efficiency of more than 60%. The measurement result shows good agreement with the large signal simulation result. We also investigated the Doherty PA linearity with digital pre-distortion (DPD) system, and obtained a drain efficiency of 48%, an ACLR of -53dBc and a power gain of 13.4dB at the average output power of 46dBm (40W) with 64QAM modulation signal. These superior performances show good suitability for 2.5GHz band WiMAX base stations.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114138528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Patil, Xiao-an Fu, C. Anupongongarch, M. Mehregany, S. Garverick
This paper reports the characterization and modeling of differential amplifiers constructed using integrated 6H-Silicon Carbide (SiC) depletion-mode n-channel JFETs operating at temperatures up to 450degC, along with off-chip passive components. The 3-stage amplifier has a differential voltage gain of -50 dB and a unity-gain frequency of -200 kHz at 450degC, limited by test parasiticus. With further improvements in the related interconnect technology, the JFET technology reported here would enable analog sensor interface circuits operating at temperatures as high as 600degC for use in data acquisition from high-impedance microsensors.
{"title":"Characterization of Silicon Carbide Differential Amplifiers at High Temperature","authors":"A. Patil, Xiao-an Fu, C. Anupongongarch, M. Mehregany, S. Garverick","doi":"10.1109/CSICS07.2007.33","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.33","url":null,"abstract":"This paper reports the characterization and modeling of differential amplifiers constructed using integrated 6H-Silicon Carbide (SiC) depletion-mode n-channel JFETs operating at temperatures up to 450degC, along with off-chip passive components. The 3-stage amplifier has a differential voltage gain of -50 dB and a unity-gain frequency of -200 kHz at 450degC, limited by test parasiticus. With further improvements in the related interconnect technology, the JFET technology reported here would enable analog sensor interface circuits operating at temperatures as high as 600degC for use in data acquisition from high-impedance microsensors.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125856740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 60-GHz power amplifier with 14 dB gain, 5 dB simulated noise figure, and a saturated output power of +6 dBm was fabricated in a 90 nm GP process with a 9-metal digital back end. The amplifier employs two cascode stages and a common-source output stage with inductive degeneration. It has a power-added-efficiency of 6% while consuming 45 mW from a 1.5-V supply. The robustness and repeatability of the small signal and large signal performance were characterized across dies, power supply voltage, and over temperature up to 125degC. The design was also scaled to 85 GHz in 65 nm CMOS with +5 dBm Psat.
{"title":"A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio","authors":"M. Khanpour, S. Voinigescu, M.T. Yang","doi":"10.1109/CSICS07.2007.29","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.29","url":null,"abstract":"A 60-GHz power amplifier with 14 dB gain, 5 dB simulated noise figure, and a saturated output power of +6 dBm was fabricated in a 90 nm GP process with a 9-metal digital back end. The amplifier employs two cascode stages and a common-source output stage with inductive degeneration. It has a power-added-efficiency of 6% while consuming 45 mW from a 1.5-V supply. The robustness and repeatability of the small signal and large signal performance were characterized across dies, power supply voltage, and over temperature up to 125degC. The design was also scaled to 85 GHz in 65 nm CMOS with +5 dBm Psat.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"76 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Houtsma, N. Weimann, A. Tate, J. Frackoviak, Y. Chen
A single-ended InP transimpedance amplifier (TIA) for next generation high-bandwidth optical fiber communication systems is presented. The TIA exhibits 48 dB-Omega transimpedance and has a 3-dB bandwidth of 92 GHz. The input-referred current noise is 20 pA/radicHz and the transimpedance group delay is below 10 ps over the entire measured frequency range.
{"title":"InP Single-Ended Transimpedance Amplifier with 92-GHz Transimpedance Bandwidth","authors":"V. Houtsma, N. Weimann, A. Tate, J. Frackoviak, Y. Chen","doi":"10.1109/CSICS07.2007.38","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.38","url":null,"abstract":"A single-ended InP transimpedance amplifier (TIA) for next generation high-bandwidth optical fiber communication systems is presented. The TIA exhibits 48 dB-Omega transimpedance and has a 3-dB bandwidth of 92 GHz. The input-referred current noise is 20 pA/radicHz and the transimpedance group delay is below 10 ps over the entire measured frequency range.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124279163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Noguchi, K. Hosoya, R. Ohhira, H. Uchida, A. Noda, N. Yoshida, S. Wada
We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear eye opening with an ultra-low jitter (< 9 mUI-rms) and an error-free operation (<1times10-12) throughout a wide range of 35 to 46 Gb/s at a 231-1 PRBS signal. The RMS and peak-to-peak jitter of the recovered clock were 226 fs and 1.56 ps, respectively. We suppressed output jitter to half of that found in previous work. In addition, a stable bit error rate (BER) that is insensitive to PRBS word length was demonstrated during an optical transmission test. These results show that our full-rate CDR is a very promising chip for 40-Gb/s-class optical transmission systems with the multi data rates.
{"title":"A 35-to-46-Gb/s Ultra-Low Jitter Clock and Data Recovery Circuit for Optical Fiber Transmission Systems","authors":"H. Noguchi, K. Hosoya, R. Ohhira, H. Uchida, A. Noda, N. Yoshida, S. Wada","doi":"10.1109/CSICS07.2007.40","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.40","url":null,"abstract":"We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear eye opening with an ultra-low jitter (< 9 mUI-rms) and an error-free operation (<1times10-12) throughout a wide range of 35 to 46 Gb/s at a 231-1 PRBS signal. The RMS and peak-to-peak jitter of the recovered clock were 226 fs and 1.56 ps, respectively. We suppressed output jitter to half of that found in previous work. In addition, a stable bit error rate (BER) that is insensitive to PRBS word length was demonstrated during an optical transmission test. These results show that our full-rate CDR is a very promising chip for 40-Gb/s-class optical transmission systems with the multi data rates.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124618027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reports on a novel InGaP HBT Darlington RF amplifier which employs dynamic feedback linearization in order to improve IP3 and P1dB compression. The dynamic feedback amplifier obtains 20 dB gain, a 0.05-4 GHz BW, a P1dB and IP3 of 21.2 dBm and 40 dBm, respectively at 2 GHz. Compared to a conventional Darlington feedback design using equivalent quiescent bias of 5V-30mA, the dynamic feedback Darlington achieved an improvement of 7.5 dB in P1dB and 11 dB in IP3. A record IP3/Pdc ratio linearity figure of merit (LFOM) of 55.4:1 and 26.9:1 were obtained at 850 MHz and 1.95 GHz. These results are believed to be the best IP3 LFOM results reported for a 5V wide band Darlington feedback amplifier.
{"title":"High Linearity Dynamic Feedback Darlington Amplifier","authors":"K. Kobayashi","doi":"10.1109/CSICS07.2007.53","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.53","url":null,"abstract":"This paper reports on a novel InGaP HBT Darlington RF amplifier which employs dynamic feedback linearization in order to improve IP3 and P1dB compression. The dynamic feedback amplifier obtains 20 dB gain, a 0.05-4 GHz BW, a P1dB and IP3 of 21.2 dBm and 40 dBm, respectively at 2 GHz. Compared to a conventional Darlington feedback design using equivalent quiescent bias of 5V-30mA, the dynamic feedback Darlington achieved an improvement of 7.5 dB in P1dB and 11 dB in IP3. A record IP3/Pdc ratio linearity figure of merit (LFOM) of 55.4:1 and 26.9:1 were obtained at 850 MHz and 1.95 GHz. These results are believed to be the best IP3 LFOM results reported for a 5V wide band Darlington feedback amplifier.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124202588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An S-band image reject downconversion mixer with high intercept point and fully integrated single-ended ports, including a UHF output, is demonstrated using GaAs pHEMT technology. The image rejection is better than 20 dB across a wide IF bandwidth ranging from 400 MHz to beyond 1 GHz with a high input IP3 of 20 dBm. On-chip passive baluns are used to provide the single-ended to differential conversion in the RF and IF paths necessary for the resistive FET mixer core. A polyphase filter is used to generate the quadrature local oscillator (LO) components, while an integrated UHF lumped element quadrature hybrid combines the intermediate frequency (IF) components to achieve image rejection fully on-chip without the need for external components.
{"title":"A Fully On-Chip, Single-Ended S-Band Image Reject Mixer for High Dynamic Range Applications","authors":"J. Lai, C. Christodoulou","doi":"10.1109/CSICS07.2007.56","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.56","url":null,"abstract":"An S-band image reject downconversion mixer with high intercept point and fully integrated single-ended ports, including a UHF output, is demonstrated using GaAs pHEMT technology. The image rejection is better than 20 dB across a wide IF bandwidth ranging from 400 MHz to beyond 1 GHz with a high input IP3 of 20 dBm. On-chip passive baluns are used to provide the single-ended to differential conversion in the RF and IF paths necessary for the resistive FET mixer core. A polyphase filter is used to generate the quadrature local oscillator (LO) components, while an integrated UHF lumped element quadrature hybrid combines the intermediate frequency (IF) components to achieve image rejection fully on-chip without the need for external components.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"52 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124237082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. K. Su, K. C. Chen, C. L. Lin, R. Chuang, J. Q. Huang, H. Hsu
Thermal management of devices package is now a critical problem for applications of high power light emitting diodes (LEDs). In this paper coppers were first electroplated on the novel package red, green, and blue LED chips directly. With the copper plating layer, the endurable injection current of these LED chips can be increased easily from conventional 350 mA to more than 1680 mA in room temperature; especially the input power of the GaN-based single chip blue LED can be increased to 12W. The relative luminous intensity at 350 mA of the novel red, green, and blue LEDs (RGB LEDs) have 53%, 69%, and 23% enhancement respectively compared with those of the conventional packaged LEDs. When the injection current of these LED chips were increased to 850mA , the relative luminous intensity of the novel RGB LEDs chips have 431% and 83%, and 18% enhancement respectively compared with those of the conventional packaged ones.
{"title":"Novel Package Technology of Ultra High Power Light-Emitting Diodes by Electroplating","authors":"Y. K. Su, K. C. Chen, C. L. Lin, R. Chuang, J. Q. Huang, H. Hsu","doi":"10.1109/CSICS07.2007.9","DOIUrl":"https://doi.org/10.1109/CSICS07.2007.9","url":null,"abstract":"Thermal management of devices package is now a critical problem for applications of high power light emitting diodes (LEDs). In this paper coppers were first electroplated on the novel package red, green, and blue LED chips directly. With the copper plating layer, the endurable injection current of these LED chips can be increased easily from conventional 350 mA to more than 1680 mA in room temperature; especially the input power of the GaN-based single chip blue LED can be increased to 12W. The relative luminous intensity at 350 mA of the novel red, green, and blue LEDs (RGB LEDs) have 53%, 69%, and 23% enhancement respectively compared with those of the conventional packaged LEDs. When the injection current of these LED chips were increased to 850mA , the relative luminous intensity of the novel RGB LEDs chips have 431% and 83%, and 18% enhancement respectively compared with those of the conventional packaged ones.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130756310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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