Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735011
M. Al-Mistarihi, A. Rjoub, Nedal R. Al-Taradeh
In this paper, an accurate new model for drain induced barrier lowering (DIBL) tunneling in silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The effect of drain (Vds) and substrate (Vbs) voltages variation on DIBL is discussed. The dependency of channel length variation (ΔL), junction depth (rj), and substrate impurity concentration (NB) on DIBL is analyzed, and new equations are obtained. The evaluation results for the proposed model using MATHEMATICA give good agreement when compared with analytical and simulation results for BSIM4 level 54 and recent well-known models using HSPICE simulator.
{"title":"Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor","authors":"M. Al-Mistarihi, A. Rjoub, Nedal R. Al-Taradeh","doi":"10.1109/ICM.2013.6735011","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735011","url":null,"abstract":"In this paper, an accurate new model for drain induced barrier lowering (DIBL) tunneling in silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The effect of drain (Vds) and substrate (Vbs) voltages variation on DIBL is discussed. The dependency of channel length variation (ΔL), junction depth (rj), and substrate impurity concentration (NB) on DIBL is analyzed, and new equations are obtained. The evaluation results for the proposed model using MATHEMATICA give good agreement when compared with analytical and simulation results for BSIM4 level 54 and recent well-known models using HSPICE simulator.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133335536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734991
A. Taibi, A. Slimane, M. Belaroussi, S. Tedjini, M. Trabelsi
This paper presents a low power and high linear reconfigurable CMOS low noise amplifier for wireless multi-standard applications including GSM (PCS1900), 3G (UMTS), Bluetooth and WLAN b/g. Based on inductive degenerated cascode topology, this LNA achieves a good trade-off between high gain, noise figure and power consumption. The input and output matching networks include controlled MOS-varactor devices to select the desired bands for multi-standard purpose. A post linearization technique is also used to improve the LNA linearity. Implemented in 0.18-μm CMOS technology, the simulated results perform a power gain higher than 21 dB, a noise figure below 2.7 dB, an input return loss less than -12.1dB and more than -3 dBm for the third-order input intercept point in frequency band 1.9-2.4 GHz. For all standards the proposed LNA consumes only a 10.9mW from 1.8V supply voltage.
{"title":"Low power and high linear reconfigurable CMOS LNA for multi-standard wireless applications","authors":"A. Taibi, A. Slimane, M. Belaroussi, S. Tedjini, M. Trabelsi","doi":"10.1109/ICM.2013.6734991","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734991","url":null,"abstract":"This paper presents a low power and high linear reconfigurable CMOS low noise amplifier for wireless multi-standard applications including GSM (PCS1900), 3G (UMTS), Bluetooth and WLAN b/g. Based on inductive degenerated cascode topology, this LNA achieves a good trade-off between high gain, noise figure and power consumption. The input and output matching networks include controlled MOS-varactor devices to select the desired bands for multi-standard purpose. A post linearization technique is also used to improve the LNA linearity. Implemented in 0.18-μm CMOS technology, the simulated results perform a power gain higher than 21 dB, a noise figure below 2.7 dB, an input return loss less than -12.1dB and more than -3 dBm for the third-order input intercept point in frequency band 1.9-2.4 GHz. For all standards the proposed LNA consumes only a 10.9mW from 1.8V supply voltage.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133214529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735012
Étienne Fuxa, J. Yon, J. Jomaah
This paper focuses on the study of thermal performances of MOS transistors for bolometer applications. Series of measurements have been conducted to obtain TCC (Temperature Coefficient of Current) versus gate voltage and temperature curves. The measurements were confronted to atlas simulations, and showed that in the subthreshold region the TCC ranges from 4%/K all the way to 9%/K. It was also determined that gate length does not have an influence on the TCC until short channel effects factor in.
{"title":"Temperature performances of bulk MOS transistors for use as temperature sensitive element for bolometer applications","authors":"Étienne Fuxa, J. Yon, J. Jomaah","doi":"10.1109/ICM.2013.6735012","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735012","url":null,"abstract":"This paper focuses on the study of thermal performances of MOS transistors for bolometer applications. Series of measurements have been conducted to obtain TCC (Temperature Coefficient of Current) versus gate voltage and temperature curves. The measurements were confronted to atlas simulations, and showed that in the subthreshold region the TCC ranges from 4%/K all the way to 9%/K. It was also determined that gate length does not have an influence on the TCC until short channel effects factor in.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125732406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734975
M. Khaled, M. Ramadan, Mostafa Gad El Rab, K. Chahine, A. Assi
This work discusses a waste heat recovery system applied to chimneys allowing to heat water in residential buildings. A prototype illustrating the idea is implemented and tested. Different waste heat scenarios by varying the quantity of burned firewood (heat input) are experimented. Temperature measurements are performed at different parts of the heat recovery system. Gas flow rates of the Exhaust pipes of the system are also measured. Using this system, measurements showed that a tank of 95 L of water can be heated up to 78 °C within one hour. Obtained results show that the convection and radiation exchanges at the bottom surface of the tank have a considerable impact on the total heat transfer rate of the water (up to 70%) used in the prototype under test.
{"title":"Heating water using the recovered chimney waste heat - Prototype and experimental analysis","authors":"M. Khaled, M. Ramadan, Mostafa Gad El Rab, K. Chahine, A. Assi","doi":"10.1109/ICM.2013.6734975","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734975","url":null,"abstract":"This work discusses a waste heat recovery system applied to chimneys allowing to heat water in residential buildings. A prototype illustrating the idea is implemented and tested. Different waste heat scenarios by varying the quantity of burned firewood (heat input) are experimented. Temperature measurements are performed at different parts of the heat recovery system. Gas flow rates of the Exhaust pipes of the system are also measured. Using this system, measurements showed that a tank of 95 L of water can be heated up to 78 °C within one hour. Obtained results show that the convection and radiation exchanges at the bottom surface of the tank have a considerable impact on the total heat transfer rate of the water (up to 70%) used in the prototype under test.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122326105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734984
K. Chahine
The need for estimating time delays arises in numerous applications where a multipath medium has to be identified from wavelets transmitted through the channel. This paper presents a method for estimating the time delays of ground penetrating radar backscattered signals. The proposed method consists of two steps: feature extraction through the generalized eigenvalue decomposition of a Hankel matrix pencil followed by training and prediction using support vector regression. The proposed feature extraction technique reduces the dimension of feature vectors and thus allows for more efficient testing and training. Simulation results show that the method succeeds in accurately estimating the time delays of the model.
{"title":"Time delay estimation of GPR backscattered signals using matrix pencil based support vector regression","authors":"K. Chahine","doi":"10.1109/ICM.2013.6734984","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734984","url":null,"abstract":"The need for estimating time delays arises in numerous applications where a multipath medium has to be identified from wavelets transmitted through the channel. This paper presents a method for estimating the time delays of ground penetrating radar backscattered signals. The proposed method consists of two steps: feature extraction through the generalized eigenvalue decomposition of a Hankel matrix pencil followed by training and prediction using support vector regression. The proposed feature extraction technique reduces the dimension of feature vectors and thus allows for more efficient testing and training. Simulation results show that the method succeeds in accurately estimating the time delays of the model.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115804481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734979
Odilon O. Dutra, Gustavo D. Colleta, L. H. C. Ferreira, T. Pimenta
This work describes a current mode implementation of Izhikevich neuron model designed with 130 nm halo implanted devices structured within matrices of order m × n capable of substantially increasing output impedance while also improving mismatch and requiring a power supply of only 250 mV.
{"title":"A sub-threshold halo implanted MOS implementation of an electronic neuron","authors":"Odilon O. Dutra, Gustavo D. Colleta, L. H. C. Ferreira, T. Pimenta","doi":"10.1109/ICM.2013.6734979","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734979","url":null,"abstract":"This work describes a current mode implementation of Izhikevich neuron model designed with 130 nm halo implanted devices structured within matrices of order m × n capable of substantially increasing output impedance while also improving mismatch and requiring a power supply of only 250 mV.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"942 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734995
A. Hatim, S. Belkouch, T. Sadiki, M. Hassani
In this paper, we propose a low complexity architecture for direct 2D-DCT computation. The architecture will transform the pixels from spatial to spectral domain with the required quality constraints of the compression standards. In our previous works we introduced a new fast 2D_DCT with low computations: only 40 additions are used and no multiplications are needed. Based on that algorithm we developed in this work a new architecture to achieve the computations of the 2D DCT directly without using any transposition memory. We defined Sk functions blocks to build the 2D DCT architecture. The Sk block perform 8 function depending on the control signals of the system. The number of additions/subtractions used is 63, but no multiplication or memory transposition is needed. The architecture is suitable for usage with statistical rules to predict the zero quantized coefficients, which can considerably reduce the number of computation. We implemented the design using an FPGA Cyclone 3. The design can reach up to 244 MHz and uses 1188 logic elements, and it respect the real time video requirements.
{"title":"Efficient hardware architecture for direct 2D DCT computation and its FPGA implementation","authors":"A. Hatim, S. Belkouch, T. Sadiki, M. Hassani","doi":"10.1109/ICM.2013.6734995","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734995","url":null,"abstract":"In this paper, we propose a low complexity architecture for direct 2D-DCT computation. The architecture will transform the pixels from spatial to spectral domain with the required quality constraints of the compression standards. In our previous works we introduced a new fast 2D_DCT with low computations: only 40 additions are used and no multiplications are needed. Based on that algorithm we developed in this work a new architecture to achieve the computations of the 2D DCT directly without using any transposition memory. We defined Sk functions blocks to build the 2D DCT architecture. The Sk block perform 8 function depending on the control signals of the system. The number of additions/subtractions used is 63, but no multiplication or memory transposition is needed. The architecture is suitable for usage with statistical rules to predict the zero quantized coefficients, which can considerably reduce the number of computation. We implemented the design using an FPGA Cyclone 3. The design can reach up to 244 MHz and uses 1188 logic elements, and it respect the real time video requirements.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125684672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735017
H. Arbess, K. Isoird
New field plate architecture is applied to pseudo vertical diamond Schottky diode. New topology structure has been proposed and simulated using Sentaurus TCAD simulation in order to minimize the maximum electric field in the dielectric at high voltage operation. Firstly and after simple variations in the field plate architecture, the breakdown voltage was improved from 1632 V to 2141 V at 700 K. Concerning Emax in the dielectric, we obtained high decreasing of the maximum electric field following the policy of pressure distribution.
{"title":"Field plate termination for high voltage diamond Schottky diode","authors":"H. Arbess, K. Isoird","doi":"10.1109/ICM.2013.6735017","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735017","url":null,"abstract":"New field plate architecture is applied to pseudo vertical diamond Schottky diode. New topology structure has been proposed and simulated using Sentaurus TCAD simulation in order to minimize the maximum electric field in the dielectric at high voltage operation. Firstly and after simple variations in the field plate architecture, the breakdown voltage was improved from 1632 V to 2141 V at 700 K. Concerning Emax in the dielectric, we obtained high decreasing of the maximum electric field following the policy of pressure distribution.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126240588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734967
A. Hayek, Moneer Al-Bokhaiti, J. Borcsok
FPGAs introduce a very attractive platform for the designing process of complex embedded systems. The complexity of these systems should be controlled to fulfill high demands and requirements, especially in safety-related applications, where aspects like reliability, availability and safety are of the utmost significance. In this context, the present paper intends the design and implementation of a novel on-chip quadruple redundant safety-related system architecture (1oo4-architecture - one out of four) as a fault tolerant technique to increase the level of safety integrity, reliability and availability of electronic embedded systems. For this aim the 1oo4-architecture and their related safety characteristics are briefly demonstrated. The FPGA-based embedded system model of this novel architecture is developed and explained. The main part of this paper focuses on the safety-related implementation on FPGA. Finally, an evaluation of the implemented architecture concludes this paper.
{"title":"Design and implementation of an FPGA-based 1oo4-architecture for safety-related system-on-chips","authors":"A. Hayek, Moneer Al-Bokhaiti, J. Borcsok","doi":"10.1109/ICM.2013.6734967","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734967","url":null,"abstract":"FPGAs introduce a very attractive platform for the designing process of complex embedded systems. The complexity of these systems should be controlled to fulfill high demands and requirements, especially in safety-related applications, where aspects like reliability, availability and safety are of the utmost significance. In this context, the present paper intends the design and implementation of a novel on-chip quadruple redundant safety-related system architecture (1oo4-architecture - one out of four) as a fault tolerant technique to increase the level of safety integrity, reliability and availability of electronic embedded systems. For this aim the 1oo4-architecture and their related safety characteristics are briefly demonstrated. The FPGA-based embedded system model of this novel architecture is developed and explained. The main part of this paper focuses on the safety-related implementation on FPGA. Finally, an evaluation of the implemented architecture concludes this paper.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134549892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734971
Rshdee Alhakim, E. Simeu
Maintaining the synchronization between receiver and transmitter in the presence of Doppler effect is considered as a major challenge for ultra-wideband (UWB) communication systems. Delay-Locked Loop (DLL) method is widely proposed to keep the satisfactory synchronization. In this paper, we modify the structure of DLL, using Internal Model Control (IMC). Unfortunately, primary simulation results confirm that the IMC-DLL has a high opportunity to lose tracking in the presence of Doppler effect. In order to solve this problem, we develop the IMC tracking structure by adding an adaptive filter block, which has a simple structure: one addition and one division operators. The simulation results confirm that the proposed IMC-DLL has better transient response, compared with the classical DLL.
{"title":"Fast-tracking delay-locked loop for UWB communication systems","authors":"Rshdee Alhakim, E. Simeu","doi":"10.1109/ICM.2013.6734971","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734971","url":null,"abstract":"Maintaining the synchronization between receiver and transmitter in the presence of Doppler effect is considered as a major challenge for ultra-wideband (UWB) communication systems. Delay-Locked Loop (DLL) method is widely proposed to keep the satisfactory synchronization. In this paper, we modify the structure of DLL, using Internal Model Control (IMC). Unfortunately, primary simulation results confirm that the IMC-DLL has a high opportunity to lose tracking in the presence of Doppler effect. In order to solve this problem, we develop the IMC tracking structure by adding an adaptive filter block, which has a simple structure: one addition and one division operators. The simulation results confirm that the proposed IMC-DLL has better transient response, compared with the classical DLL.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134441055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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