Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734945
H. Escid, Sonia Salhi, A. Slimane
In this paper, a low noise and high bandwidth transimpedance amplifier (TIA) is designed for optical receiver using a 0.18 μm standard in CMOS technology. The proposed circuit operates at a data rate of 13.25 Gb/s. Employing a series inductive peaking technique, an improvement of bandwidth by only one inductor within the structure is achieved to reach a wide bandwidth of 9.28 GHz. The gain of this amplifier is 53 dB at 9.28 GHz and its input current noise is about 36.12 pA/√Hz.
{"title":"Bandwidth enhancement for 0.18 µm CMOS transimpedance amplifier circuit","authors":"H. Escid, Sonia Salhi, A. Slimane","doi":"10.1109/ICM.2013.6734945","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734945","url":null,"abstract":"In this paper, a low noise and high bandwidth transimpedance amplifier (TIA) is designed for optical receiver using a 0.18 μm standard in CMOS technology. The proposed circuit operates at a data rate of 13.25 Gb/s. Employing a series inductive peaking technique, an improvement of bandwidth by only one inductor within the structure is achieved to reach a wide bandwidth of 9.28 GHz. The gain of this amplifier is 53 dB at 9.28 GHz and its input current noise is about 36.12 pA/√Hz.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126861010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734970
D. Homouz, Z. Abid, B. Mohammad, Y. Halawani, Michael Jacobson
The Memristor, as the newly discovered fourth circuit element, is being used in many applications such as memory and digital circuits, as well as neuromorphic systems. The unique characteristics of the memristor: retaining its resistance state, ability to behave as a switch and consequently the possibility to be used in both memory and digital circuits. Its resistance can also change gradually allowing the potential of mimicking neural chemical synapses. These applications of the memristor will be reviewed and discussed using a nonlinear mathematical model of physical bipolar memristor devices.
{"title":"Memristors for digital, memory and neuromorphic circuits","authors":"D. Homouz, Z. Abid, B. Mohammad, Y. Halawani, Michael Jacobson","doi":"10.1109/ICM.2013.6734970","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734970","url":null,"abstract":"The Memristor, as the newly discovered fourth circuit element, is being used in many applications such as memory and digital circuits, as well as neuromorphic systems. The unique characteristics of the memristor: retaining its resistance state, ability to behave as a switch and consequently the possibility to be used in both memory and digital circuits. Its resistance can also change gradually allowing the potential of mimicking neural chemical synapses. These applications of the memristor will be reviewed and discussed using a nonlinear mathematical model of physical bipolar memristor devices.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133288634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734988
V. Sklyarov, I. Skliarova, A. Sudnitson
The paper discusses effectiveness of N-ary trees for solving different application problems with case studies on search and sort. A new method for representation of trees in memory, which takes advantages of widely available in commercial Field-Programmable Gate Array (FPGA) built-in block RAM, is proposed. It is shown that N-ary trees can be coded in such a way that enables the required size of memory to be significantly reduced with practically the same performance as in the previously developed methods. Thus, larger trees can be stored and further handled in FPGAs with equal hardware resources. It is also shown that the trees can be processed using both iterative and recursive techniques. The latter is discussed in detail due to opportunities for more compact and clear specifications, and comparison is done with the previous results permitting very good performance to be achieved.
{"title":"Processing N-ary trees in reconfigurable hardware","authors":"V. Sklyarov, I. Skliarova, A. Sudnitson","doi":"10.1109/ICM.2013.6734988","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734988","url":null,"abstract":"The paper discusses effectiveness of N-ary trees for solving different application problems with case studies on search and sort. A new method for representation of trees in memory, which takes advantages of widely available in commercial Field-Programmable Gate Array (FPGA) built-in block RAM, is proposed. It is shown that N-ary trees can be coded in such a way that enables the required size of memory to be significantly reduced with practically the same performance as in the previously developed methods. Thus, larger trees can be stored and further handled in FPGAs with equal hardware resources. It is also shown that the trees can be processed using both iterative and recursive techniques. The latter is discussed in detail due to opportunities for more compact and clear specifications, and comparison is done with the previous results permitting very good performance to be achieved.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131698683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734960
Z. Merhi, M. Nahas, Samih Abdul-Nabi, A. Haj-Ali, M. Bayoumi
Range estimation using RSSI (received signal strength indicator) for localization application for wireless sensor networks is a challenging task. Interference from the shared 2.4GHz channel and fading due to multipath propagation and shadowing deteriorate the process of range estimation. In this work an estimation of these noise levels that are present in the environment is being carried out by anchor nodes which are placed throughout the sensing field. These anchor nodes will compare the actual distance between them with distance computed from the measured RSSI. Four different techniques have been devised that applies a smoothing coefficient on the measured RSSI taking into consideration information about the environment from the anchor nodes. Simulation shows that even when the error introduced is equivalent to 100% of the transmission range, the error in range estimation was around 25%.
{"title":"RSSI range estimation for indoor anchor based localization for wireless sensor networks","authors":"Z. Merhi, M. Nahas, Samih Abdul-Nabi, A. Haj-Ali, M. Bayoumi","doi":"10.1109/ICM.2013.6734960","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734960","url":null,"abstract":"Range estimation using RSSI (received signal strength indicator) for localization application for wireless sensor networks is a challenging task. Interference from the shared 2.4GHz channel and fading due to multipath propagation and shadowing deteriorate the process of range estimation. In this work an estimation of these noise levels that are present in the environment is being carried out by anchor nodes which are placed throughout the sensing field. These anchor nodes will compare the actual distance between them with distance computed from the measured RSSI. Four different techniques have been devised that applies a smoothing coefficient on the measured RSSI taking into consideration information about the environment from the anchor nodes. Simulation shows that even when the error introduced is equivalent to 100% of the transmission range, the error in range estimation was around 25%.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117253733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735006
M. Hajj-Hassan, A. Harb, Hussein Hajj-Hassan
The paper presents the design of MEMS-based sensory system for real-time bacteria detection. The principle of functioning is based on monitoring the variation in capacitance signals owing to the adherence of target bacteria to the sensing interface. The system is designed using custom-based technology and it consists of comb finger capacitor structures made out of doped polysilicon. Aiming at improving the detection efficiency, the space between the comb fingers, forming the two electrodes of the capacitive sensor, will be made porous through a post-processing with Xenon Difluoride (XeF2) dry etching technique. This allows entrapping bacteria in between the electrodes thus increasing the variation of capacitance. This latter, is acquired using a Charge Based Capacitance Measurement (CBCM) sensory circuit built with to the 0.13 μm CMOS technology. The circuit is able to detect a difference in capacitance as low as 0.75 fF.
{"title":"Bacterial immobilization and detection using porous silicon platform and CMOS sensory circuit","authors":"M. Hajj-Hassan, A. Harb, Hussein Hajj-Hassan","doi":"10.1109/ICM.2013.6735006","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735006","url":null,"abstract":"The paper presents the design of MEMS-based sensory system for real-time bacteria detection. The principle of functioning is based on monitoring the variation in capacitance signals owing to the adherence of target bacteria to the sensing interface. The system is designed using custom-based technology and it consists of comb finger capacitor structures made out of doped polysilicon. Aiming at improving the detection efficiency, the space between the comb fingers, forming the two electrodes of the capacitive sensor, will be made porous through a post-processing with Xenon Difluoride (XeF2) dry etching technique. This allows entrapping bacteria in between the electrodes thus increasing the variation of capacitance. This latter, is acquired using a Charge Based Capacitance Measurement (CBCM) sensory circuit built with to the 0.13 μm CMOS technology. The circuit is able to detect a difference in capacitance as low as 0.75 fF.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122318144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734989
R. Chebli, M. Sawan
This paper concerns the design and implementation of a new fully integrated Chopped Logarithmic Programmable Gain Amplifier (CLPGA) intended for a front-end EEG acquisition interface. The proposed front-end has low-input referred noise and high-common mode rejection ratio (CMRR) compared to Instrumentation Amplifier features, and its rail-to-rail topology allows electrode offset rejection. The logarithmic amplification block is composed of three cascaded true logarithmic amplification stages. Also, a chopper stabilization technique is used to improve the noise figure. This front-end interface is followed by an analog to digital convertor, and in order to prevent EEG signal distortion, the magnitude of the later signal is controlled by implementing new programming gain approach. Post-layout simulation in 0.18 μm CMOS technology demonstrates a High CMRR of 284 dB @50/60 Hz, an input referred noise of ~0.5 mVrs on 100 Hz BW and an input common mode ranges from 0.6 to 1.12 V for 1.8 V supply. The measured power consumption is 1.2 mW and the effective CLPGA area is 0.5 mm2 including the digital part needed for programming the gain.
{"title":"Chopped Logarithmic Programmable Gain Amplifier intended to EEG acquisition interface","authors":"R. Chebli, M. Sawan","doi":"10.1109/ICM.2013.6734989","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734989","url":null,"abstract":"This paper concerns the design and implementation of a new fully integrated Chopped Logarithmic Programmable Gain Amplifier (CLPGA) intended for a front-end EEG acquisition interface. The proposed front-end has low-input referred noise and high-common mode rejection ratio (CMRR) compared to Instrumentation Amplifier features, and its rail-to-rail topology allows electrode offset rejection. The logarithmic amplification block is composed of three cascaded true logarithmic amplification stages. Also, a chopper stabilization technique is used to improve the noise figure. This front-end interface is followed by an analog to digital convertor, and in order to prevent EEG signal distortion, the magnitude of the later signal is controlled by implementing new programming gain approach. Post-layout simulation in 0.18 μm CMOS technology demonstrates a High CMRR of 284 dB @50/60 Hz, an input referred noise of ~0.5 mVrs on 100 Hz BW and an input common mode ranges from 0.6 to 1.12 V for 1.8 V supply. The measured power consumption is 1.2 mW and the effective CLPGA area is 0.5 mm2 including the digital part needed for programming the gain.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"122 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121092141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734955
A. Assi, M. Al-Amin
Parasitic loss in monocrystalline silicon (mc-Si) solar cell significantly degrades the cell's electrical performance. However, surface contamination due to the presence of organic residues and non-optimized silicon nitride properties (SiNx), and deposits by plasma- enhanced chemical vapor deposition (PECVD), lead to higher parasitic loss. In this research work, a cleaning process by using sodium hypo chlorate (NaOCl) and potassium hydroxide (KOH) is introduced before the anisotropic texturization by sodium/potassium hydroxide (NaOH/KOH) and Isopropyl alcohol (IPA) solutions. The surface morphology, reflectance factor (RF) are investigated and compared. Furthermore, SiNx layer properties have been optimized and the effect of process parameters on shunt resistance (RSH) has been analyzed. A batch of 156 mm pseudo square (PSQ) mc-Si solar cells are fabricated with the optimized process where electrical properties are analyzed and compared with the standard one. RSH, fill factor (FF) and efficiency are found to be higher by 40%, 1.6% (absolute) and 0.37% (absolute) respectively for the optimized process.
{"title":"Reducing the parasitic loss of c-Si solar cells","authors":"A. Assi, M. Al-Amin","doi":"10.1109/ICM.2013.6734955","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734955","url":null,"abstract":"Parasitic loss in monocrystalline silicon (mc-Si) solar cell significantly degrades the cell's electrical performance. However, surface contamination due to the presence of organic residues and non-optimized silicon nitride properties (SiNx), and deposits by plasma- enhanced chemical vapor deposition (PECVD), lead to higher parasitic loss. In this research work, a cleaning process by using sodium hypo chlorate (NaOCl) and potassium hydroxide (KOH) is introduced before the anisotropic texturization by sodium/potassium hydroxide (NaOH/KOH) and Isopropyl alcohol (IPA) solutions. The surface morphology, reflectance factor (RF) are investigated and compared. Furthermore, SiNx layer properties have been optimized and the effect of process parameters on shunt resistance (RSH) has been analyzed. A batch of 156 mm pseudo square (PSQ) mc-Si solar cells are fabricated with the optimized process where electrical properties are analyzed and compared with the standard one. RSH, fill factor (FF) and efficiency are found to be higher by 40%, 1.6% (absolute) and 0.37% (absolute) respectively for the optimized process.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124989450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735001
Abdelhamid Hariche, M. Belarbi, Hayat Daoud
Event-B is the promising approach applied on several domains, it can be used to specify, prove and develop SoCs and MPSoCs models incrementally using the refinement. The suggested new refinement approach consists of suggesting new concepts and constraints related to the reliability of QNoCs and the over-cost related to the solutions of FPGA-Based technology fault-tolerance in the reason of practically managing the complexity caused by the extremely large number of variables used in the VHDL code (last step of the refinement) which are describing the state of QNoC systems. To remediate to this problem, we introduce concepts of decomposition and Re-composition that use three new operators (Rename, Enrich, Ensure) that they are linking together and used to enhance the Event-B refinement to finally make it more and more structural.
{"title":"A new operators-based approach for the Event-B refinement: QNoC case study","authors":"Abdelhamid Hariche, M. Belarbi, Hayat Daoud","doi":"10.1109/ICM.2013.6735001","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735001","url":null,"abstract":"Event-B is the promising approach applied on several domains, it can be used to specify, prove and develop SoCs and MPSoCs models incrementally using the refinement. The suggested new refinement approach consists of suggesting new concepts and constraints related to the reliability of QNoCs and the over-cost related to the solutions of FPGA-Based technology fault-tolerance in the reason of practically managing the complexity caused by the extremely large number of variables used in the VHDL code (last step of the refinement) which are describing the state of QNoC systems. To remediate to this problem, we introduce concepts of decomposition and Re-composition that use three new operators (Rename, Enrich, Ensure) that they are linking together and used to enhance the Event-B refinement to finally make it more and more structural.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127426451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734978
Salma Shabayek, Alaa Medra, R. Guindi
An ultra low power wake-up receiver for Wireless Sensor Network (WSN) applications is presented. The proposed wake-up receiver is composed of two stages. The first stage is a low-power low-sensitivity stage that acts as a `sentinel' and continuously monitors the channel, while the second stage is a conventional low-power wake-up receiver. The 2.44GHz two-stage receiver has a sensitivity of -72dBm when the transmitted signal power is 0dBm. The power consumed during sleep mode is 2.5μWatts and 41μWatts in the wake-up receiver active mode with a 0.5V supply voltage. The power consumption is nearly one order-of-magnitude below previously published wake-up receiver designs for WSNs.
{"title":"A 2.5 µWatts two stage wake-up receiver for Wireless Sensor Networks","authors":"Salma Shabayek, Alaa Medra, R. Guindi","doi":"10.1109/ICM.2013.6734978","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734978","url":null,"abstract":"An ultra low power wake-up receiver for Wireless Sensor Network (WSN) applications is presented. The proposed wake-up receiver is composed of two stages. The first stage is a low-power low-sensitivity stage that acts as a `sentinel' and continuously monitors the channel, while the second stage is a conventional low-power wake-up receiver. The 2.44GHz two-stage receiver has a sensitivity of -72dBm when the transmitted signal power is 0dBm. The power consumed during sleep mode is 2.5μWatts and 41μWatts in the wake-up receiver active mode with a 0.5V supply voltage. The power consumption is nearly one order-of-magnitude below previously published wake-up receiver designs for WSNs.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129632667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-15DOI: 10.1109/ICM.2013.6735014
Bertrand F. Tchanche, P. Loonis, M. Pétrissans, H. Ramenah
An organic Rankine cycle (ORC) is simply a steam cycle in which the traditional steam is replaced by refrigerants or hydrocarbons. ORCs utilize clean energy resources: geothermal fluids, solar irradiation, ocean thermal gradient, heat from biomass combustion and waste heat from industrial thermal processes. The interest is growing over this technology. Large systems (> 400 kW) are commercially available while small scale systems are still under development. This technology is a new opportunity for industries and alternative solution for clean power generation. This paper recalls ORC principles, outlines challenges to be overcome (working fluids, small expanders design, performance map, heat exchangers integration, and project guidelines) and gives few data on the ORC market.
{"title":"Organic Rankine cycle systems Principles, opportunities and challenges","authors":"Bertrand F. Tchanche, P. Loonis, M. Pétrissans, H. Ramenah","doi":"10.1109/ICM.2013.6735014","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735014","url":null,"abstract":"An organic Rankine cycle (ORC) is simply a steam cycle in which the traditional steam is replaced by refrigerants or hydrocarbons. ORCs utilize clean energy resources: geothermal fluids, solar irradiation, ocean thermal gradient, heat from biomass combustion and waste heat from industrial thermal processes. The interest is growing over this technology. Large systems (> 400 kW) are commercially available while small scale systems are still under development. This technology is a new opportunity for industries and alternative solution for clean power generation. This paper recalls ORC principles, outlines challenges to be overcome (working fluids, small expanders design, performance map, heat exchangers integration, and project guidelines) and gives few data on the ORC market.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129595189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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