Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734987
K. Cheng, S. Le Beux, I. O’Connor
Ambipolar and/or Independent Double Gate-FET (Am/IDG-FET) technology offers the possibility to optimize the architecture of reconfigurable cells at transistor level. Many of such reconfigurable cells have been proposed offering different partial functionality set, and previous work shows the benefit of such designs in terms of electric performance. This paper analyzes the benefits and drawbacks of Reconfigurable Cells based on Am/IDG-FETs versus commonly used 2, 4, and 6-inputs LUTs considering the number of transistor and the number of input. Results show the drastic optimization (Reduction of 30% to 50% of the transistor count) but at the cost of a reduce set of function at the cell level. As main FPGA manufacturer proved that a 6-inputs LUTs is the best solutions in terms of input granularity, 6-inputs Am/IDG-FET based Reconfigurable cells represent a considerable optimized solution.
{"title":"Am/IDG-FET based reconfigurable cells versus LUTs: Characteristics description and analysis","authors":"K. Cheng, S. Le Beux, I. O’Connor","doi":"10.1109/ICM.2013.6734987","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734987","url":null,"abstract":"Ambipolar and/or Independent Double Gate-FET (Am/IDG-FET) technology offers the possibility to optimize the architecture of reconfigurable cells at transistor level. Many of such reconfigurable cells have been proposed offering different partial functionality set, and previous work shows the benefit of such designs in terms of electric performance. This paper analyzes the benefits and drawbacks of Reconfigurable Cells based on Am/IDG-FETs versus commonly used 2, 4, and 6-inputs LUTs considering the number of transistor and the number of input. Results show the drastic optimization (Reduction of 30% to 50% of the transistor count) but at the cost of a reduce set of function at the cell level. As main FPGA manufacturer proved that a 6-inputs LUTs is the best solutions in terms of input granularity, 6-inputs Am/IDG-FET based Reconfigurable cells represent a considerable optimized solution.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134515580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734962
M. Nahas, Mohamad Mjalled, Zaher Zohbi, Z. Merhi, M. Ghantous
To improve the interworking between LTE and WiFi wireless technologies, an efficient handover mechanism is proposed. Dynamic and critical measures like mobile-assisted parameters are inserted to the Access Network Discovery and Selection Function (ANDSF) entity defined by 3GPP standard. Moreover, Context Aware (CA) decision algorithm is integrated within the ANDSF server so that the inserted measurements are expeditiously invested to improve the handover decision policy. The performance enhancement of the proposed model compared to the traditional one is shown by numerical simulations.
{"title":"Enhancing LTE - WiFi interoperability using context aware criteria for handover decision","authors":"M. Nahas, Mohamad Mjalled, Zaher Zohbi, Z. Merhi, M. Ghantous","doi":"10.1109/ICM.2013.6734962","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734962","url":null,"abstract":"To improve the interworking between LTE and WiFi wireless technologies, an efficient handover mechanism is proposed. Dynamic and critical measures like mobile-assisted parameters are inserted to the Access Network Discovery and Selection Function (ANDSF) entity defined by 3GPP standard. Moreover, Context Aware (CA) decision algorithm is integrated within the ANDSF server so that the inserted measurements are expeditiously invested to improve the handover decision policy. The performance enhancement of the proposed model compared to the traditional one is shown by numerical simulations.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123590377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734951
S. Kala, S. Nalesh, S. Nandy, R. Narayan
This paper presents a Radix-43 based FFT architecture suitable for OFDM based WLAN applications. The radix-43 parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm2. The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.
{"title":"Design of a low power 64 point FFT architecture for WLAN applications","authors":"S. Kala, S. Nalesh, S. Nandy, R. Narayan","doi":"10.1109/ICM.2013.6734951","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734951","url":null,"abstract":"This paper presents a Radix-43 based FFT architecture suitable for OFDM based WLAN applications. The radix-43 parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm2. The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116932081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734986
W. Mansour, R. Velazco, R. Ayoubi, H. Ziade, W. El Falou
A fully automated fault-injection method is presented. It deals with transient faults resulting from the impact of energetic particles and it can be applied early at design phase, on any circuit for which the register transfer level model is available. Results issued from its application to an Artificial Neural Network benchmark application put in evidence the accuracy of the studied method to predict error rates due to transient faults generated by the radiation environment.
{"title":"A method and an automated tool to perform SET fault-injection on HDL-based designs","authors":"W. Mansour, R. Velazco, R. Ayoubi, H. Ziade, W. El Falou","doi":"10.1109/ICM.2013.6734986","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734986","url":null,"abstract":"A fully automated fault-injection method is presented. It deals with transient faults resulting from the impact of energetic particles and it can be applied early at design phase, on any circuit for which the register transfer level model is available. Results issued from its application to an Artificial Neural Network benchmark application put in evidence the accuracy of the studied method to predict error rates due to transient faults generated by the radiation environment.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116125502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735018
M. Owayjan, Adel I. Chit, Elie Abdo, Chadi Fakhry
Load balancing is crucial in integrating renewable power from large wind turbines into the existing grid. This is due to the fact that the output power of the wind turbines is affected by the wind's speed. One solution to connect a large wind turbine with the electrical grid is to create a dump load that is responsible for dissipating extra power generated by the wind energy. This paper presents a new system that regulates the output frequency of a wind turbine power generator to 50 Hz using a microcontroller. This new design includes an intelligent dump load controller for wind turbines. Depending on the user's consumption, the load can go from zero to full load, in a way that the power generated is balanced with the power consumed. The design is implemented and tested on a real large power wind turbine, and the results obtained are very satisfactory.
{"title":"Intelligent dump load controller for high power wind turbine","authors":"M. Owayjan, Adel I. Chit, Elie Abdo, Chadi Fakhry","doi":"10.1109/ICM.2013.6735018","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735018","url":null,"abstract":"Load balancing is crucial in integrating renewable power from large wind turbines into the existing grid. This is due to the fact that the output power of the wind turbines is affected by the wind's speed. One solution to connect a large wind turbine with the electrical grid is to create a dump load that is responsible for dissipating extra power generated by the wind energy. This paper presents a new system that regulates the output frequency of a wind turbine power generator to 50 Hz using a microcontroller. This new design includes an intelligent dump load controller for wind turbines. Depending on the user's consumption, the load can go from zero to full load, in a way that the power generated is balanced with the power consumed. The design is implemented and tested on a real large power wind turbine, and the results obtained are very satisfactory.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734954
A. Assi, M. Al-Amin
Soldering techniques used to interconnect large thin c-Si solar cells in PV modules have a significant impact on the generated electrical power and reliability of the manufactured modules. Poor soldering process results on an abnormal mechanical or thermal stress which leads to micro cracks, cell breakage, and lower adhesion force. Moreover, poor soldering increases the contact resistance (Rc) between the busbar and ribbon and lowers the fill factor (FF) of the PV module. In this paper, the impact of process parameters in an automated induction soldering process has been examined. Different adhesion force (AF) profiles and relationship with current transport mechanism have been investigated. AF is increased with temperature till 240-260°C whereas it is lowered at low and very high soldering temperature. Electroluminescence (EL) image showed that solar cell is prone to micro-cracks at higher temperature but observed as a random event. Modules were processed with different soldering conditions and characterized. Results show that, using the suggested soldering process, FF can be improved by 0.53, and the power output can be as high as 251.26 W, which is higher by 2.50% compared to the non-optimized process.
{"title":"Enhancement of electrical performance of c-Si PV modules through optimized soldering process","authors":"A. Assi, M. Al-Amin","doi":"10.1109/ICM.2013.6734954","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734954","url":null,"abstract":"Soldering techniques used to interconnect large thin c-Si solar cells in PV modules have a significant impact on the generated electrical power and reliability of the manufactured modules. Poor soldering process results on an abnormal mechanical or thermal stress which leads to micro cracks, cell breakage, and lower adhesion force. Moreover, poor soldering increases the contact resistance (Rc) between the busbar and ribbon and lowers the fill factor (FF) of the PV module. In this paper, the impact of process parameters in an automated induction soldering process has been examined. Different adhesion force (AF) profiles and relationship with current transport mechanism have been investigated. AF is increased with temperature till 240-260°C whereas it is lowered at low and very high soldering temperature. Electroluminescence (EL) image showed that solar cell is prone to micro-cracks at higher temperature but observed as a random event. Modules were processed with different soldering conditions and characterized. Results show that, using the suggested soldering process, FF can be improved by 0.53, and the power output can be as high as 251.26 W, which is higher by 2.50% compared to the non-optimized process.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734996
V. Mishra, A. Sengupta
The process of Design Space Exploration (DSE) during architectural synthesis is very intricate and tedious. It involves trade-off between conflicting design objectives of power-performance as well as between orthogonal issues of exploration time and quality of result. This paper proposes a novel integrated framework on swarm intelligence (particle swarm optimization) based DSE for power-performance trade-off during architectural synthesis of control and data intensive applications. The proposed integrated approach comprises of a comprehensive mapping process and reliable solution evaluation strategy. Therefore, the novel contributions of the paper are as follows: i) Introduction of a novel particle swarm optimization driven DSE methodology for power-performance trade-off ii) Novel solution evaluation methodology incorporating power and execution time parameters iii) Novel stochastic based diversity introduction technique (particle mutation algorithm) iv) Novel perturbation technique to control unwarranted exploration drift of particles v) improved results in QoR (> 21%) and reduction in exploration time (> 81%) when compared to recent DSE approaches for the tested benchmarks.
建筑综合中的设计空间探索(Design Space Exploration, DSE)过程十分复杂和繁琐。它涉及到在相互冲突的动力性能设计目标之间以及在探索时间和结果质量的正交问题之间的权衡。本文提出了一种新的基于群体智能(粒子群优化)的DSE集成框架，用于控制和数据密集型应用的体系结构综合中的功率性能权衡。所提出的综合方法包括一个全面的映射过程和可靠的解决方案评估策略。因此，本文的新颖贡献如下:i)引入了一种新的粒子群优化驱动的DSE方法，用于功率性能权衡ii)结合功率和执行时间参数的新颖解决方案评估方法iii)新的基于随机的多样性引入技术(粒子突变算法)iv)新的微扰技术来控制粒子的不必要的勘探漂移v)与最近的DSE方法相比，QoR(> 21%)的结果得到改善，勘探时间减少(> 81%)经过测试的基准。
{"title":"Swarm intelligence driven Design Space Exploration: An integrated framework for power-performance trade-off in architectural synthesis","authors":"V. Mishra, A. Sengupta","doi":"10.1109/ICM.2013.6734996","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734996","url":null,"abstract":"The process of Design Space Exploration (DSE) during architectural synthesis is very intricate and tedious. It involves trade-off between conflicting design objectives of power-performance as well as between orthogonal issues of exploration time and quality of result. This paper proposes a novel integrated framework on swarm intelligence (particle swarm optimization) based DSE for power-performance trade-off during architectural synthesis of control and data intensive applications. The proposed integrated approach comprises of a comprehensive mapping process and reliable solution evaluation strategy. Therefore, the novel contributions of the paper are as follows: i) Introduction of a novel particle swarm optimization driven DSE methodology for power-performance trade-off ii) Novel solution evaluation methodology incorporating power and execution time parameters iii) Novel stochastic based diversity introduction technique (particle mutation algorithm) iv) Novel perturbation technique to control unwarranted exploration drift of particles v) improved results in QoR (> 21%) and reduction in exploration time (> 81%) when compared to recent DSE approaches for the tested benchmarks.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131114756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734948
W. Mansour, Greicy Marques-Costa, R. Velazco
Self-convergence is a property that allows distributed systems, when perturbed or badly initialized, to recover a correct operation within finite number of calculation steps. In this paper, an FPGA implementation of this algorithm is presented. The intrinsic robustness of the studied implementation with respect to soft errors resulting from radiation effects is explored by means of a fault-injected method. Obtained results put in evidence the fault-tolerance capabilities and robustness of the tested hardware-implemented algorithm.
{"title":"Robustness with respect to SEU of a hardware-implemented self-converging algorithm","authors":"W. Mansour, Greicy Marques-Costa, R. Velazco","doi":"10.1109/ICM.2013.6734948","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734948","url":null,"abstract":"Self-convergence is a property that allows distributed systems, when perturbed or badly initialized, to recover a correct operation within finite number of calculation steps. In this paper, an FPGA implementation of this algorithm is presented. The intrinsic robustness of the studied implementation with respect to soft errors resulting from radiation effects is explored by means of a fault-injected method. Obtained results put in evidence the fault-tolerance capabilities and robustness of the tested hardware-implemented algorithm.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129867625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734973
A. El-rachini, H. Chible, G. Nicola, M. Barbaro, L. Raffo
Non-idealities such as static device mismatch and dynamic timing mismatch, in different architectures of multi-steps analog to digital converter affect the redundancy and performance at the output of an instrument. Redundant sign digit (RSD) is an approach of calibration have been proposed to detect and automation no anymore only for cyclic converter but also for multistage A/D with M-bits per cycle for correction of errors in order to improve the resolution and the redundancy of A/D converters and to adapt the high performance of digital signal processing system. In this paper, we will presented a behavioral model in order to investigate the impact of different sources of error at different levels of simulation based at the comparison of RSD to conventional converter with Z extra decision level (CRZ).
{"title":"Behavioural models for analog to digital conversion architectures for deep submicron technology nodes","authors":"A. El-rachini, H. Chible, G. Nicola, M. Barbaro, L. Raffo","doi":"10.1109/ICM.2013.6734973","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734973","url":null,"abstract":"Non-idealities such as static device mismatch and dynamic timing mismatch, in different architectures of multi-steps analog to digital converter affect the redundancy and performance at the output of an instrument. Redundant sign digit (RSD) is an approach of calibration have been proposed to detect and automation no anymore only for cyclic converter but also for multistage A/D with M-bits per cycle for correction of errors in order to improve the resolution and the redundancy of A/D converters and to adapt the high performance of digital signal processing system. In this paper, we will presented a behavioral model in order to investigate the impact of different sources of error at different levels of simulation based at the comparison of RSD to conventional converter with Z extra decision level (CRZ).","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133660589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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