Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735016
Hassan Abbass, Hawraa Amhaz, G. Sicard, D. Alleysson
In this paper we present a new mixed design of the tone mapping technique used to adjust high dynamic range (HDR) image sensor luminosities. The dynamic range extension along with the tone mapping technique implementation allows covering correctly more than six orders of luminosity magnitude. The architecture is inspired from the human vision system operation. The proposed function and its architecture design as well as MATLAB emulation applied to images extracted from a linear CMOS image sensor designed in 0.35um AMS technology are illustrated along the paragraphs of the paper.
{"title":"Novel mixed design of tone mapping technique for HDR CMOS image sensor","authors":"Hassan Abbass, Hawraa Amhaz, G. Sicard, D. Alleysson","doi":"10.1109/ICM.2013.6735016","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735016","url":null,"abstract":"In this paper we present a new mixed design of the tone mapping technique used to adjust high dynamic range (HDR) image sensor luminosities. The dynamic range extension along with the tone mapping technique implementation allows covering correctly more than six orders of luminosity magnitude. The architecture is inspired from the human vision system operation. The proposed function and its architecture design as well as MATLAB emulation applied to images extracted from a linear CMOS image sensor designed in 0.35um AMS technology are illustrated along the paragraphs of the paper.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133422504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734962
M. Nahas, Mohamad Mjalled, Zaher Zohbi, Z. Merhi, M. Ghantous
To improve the interworking between LTE and WiFi wireless technologies, an efficient handover mechanism is proposed. Dynamic and critical measures like mobile-assisted parameters are inserted to the Access Network Discovery and Selection Function (ANDSF) entity defined by 3GPP standard. Moreover, Context Aware (CA) decision algorithm is integrated within the ANDSF server so that the inserted measurements are expeditiously invested to improve the handover decision policy. The performance enhancement of the proposed model compared to the traditional one is shown by numerical simulations.
{"title":"Enhancing LTE - WiFi interoperability using context aware criteria for handover decision","authors":"M. Nahas, Mohamad Mjalled, Zaher Zohbi, Z. Merhi, M. Ghantous","doi":"10.1109/ICM.2013.6734962","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734962","url":null,"abstract":"To improve the interworking between LTE and WiFi wireless technologies, an efficient handover mechanism is proposed. Dynamic and critical measures like mobile-assisted parameters are inserted to the Access Network Discovery and Selection Function (ANDSF) entity defined by 3GPP standard. Moreover, Context Aware (CA) decision algorithm is integrated within the ANDSF server so that the inserted measurements are expeditiously invested to improve the handover decision policy. The performance enhancement of the proposed model compared to the traditional one is shown by numerical simulations.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123590377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735018
M. Owayjan, Adel I. Chit, Elie Abdo, Chadi Fakhry
Load balancing is crucial in integrating renewable power from large wind turbines into the existing grid. This is due to the fact that the output power of the wind turbines is affected by the wind's speed. One solution to connect a large wind turbine with the electrical grid is to create a dump load that is responsible for dissipating extra power generated by the wind energy. This paper presents a new system that regulates the output frequency of a wind turbine power generator to 50 Hz using a microcontroller. This new design includes an intelligent dump load controller for wind turbines. Depending on the user's consumption, the load can go from zero to full load, in a way that the power generated is balanced with the power consumed. The design is implemented and tested on a real large power wind turbine, and the results obtained are very satisfactory.
{"title":"Intelligent dump load controller for high power wind turbine","authors":"M. Owayjan, Adel I. Chit, Elie Abdo, Chadi Fakhry","doi":"10.1109/ICM.2013.6735018","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735018","url":null,"abstract":"Load balancing is crucial in integrating renewable power from large wind turbines into the existing grid. This is due to the fact that the output power of the wind turbines is affected by the wind's speed. One solution to connect a large wind turbine with the electrical grid is to create a dump load that is responsible for dissipating extra power generated by the wind energy. This paper presents a new system that regulates the output frequency of a wind turbine power generator to 50 Hz using a microcontroller. This new design includes an intelligent dump load controller for wind turbines. Depending on the user's consumption, the load can go from zero to full load, in a way that the power generated is balanced with the power consumed. The design is implemented and tested on a real large power wind turbine, and the results obtained are very satisfactory.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734954
A. Assi, M. Al-Amin
Soldering techniques used to interconnect large thin c-Si solar cells in PV modules have a significant impact on the generated electrical power and reliability of the manufactured modules. Poor soldering process results on an abnormal mechanical or thermal stress which leads to micro cracks, cell breakage, and lower adhesion force. Moreover, poor soldering increases the contact resistance (Rc) between the busbar and ribbon and lowers the fill factor (FF) of the PV module. In this paper, the impact of process parameters in an automated induction soldering process has been examined. Different adhesion force (AF) profiles and relationship with current transport mechanism have been investigated. AF is increased with temperature till 240-260°C whereas it is lowered at low and very high soldering temperature. Electroluminescence (EL) image showed that solar cell is prone to micro-cracks at higher temperature but observed as a random event. Modules were processed with different soldering conditions and characterized. Results show that, using the suggested soldering process, FF can be improved by 0.53, and the power output can be as high as 251.26 W, which is higher by 2.50% compared to the non-optimized process.
{"title":"Enhancement of electrical performance of c-Si PV modules through optimized soldering process","authors":"A. Assi, M. Al-Amin","doi":"10.1109/ICM.2013.6734954","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734954","url":null,"abstract":"Soldering techniques used to interconnect large thin c-Si solar cells in PV modules have a significant impact on the generated electrical power and reliability of the manufactured modules. Poor soldering process results on an abnormal mechanical or thermal stress which leads to micro cracks, cell breakage, and lower adhesion force. Moreover, poor soldering increases the contact resistance (Rc) between the busbar and ribbon and lowers the fill factor (FF) of the PV module. In this paper, the impact of process parameters in an automated induction soldering process has been examined. Different adhesion force (AF) profiles and relationship with current transport mechanism have been investigated. AF is increased with temperature till 240-260°C whereas it is lowered at low and very high soldering temperature. Electroluminescence (EL) image showed that solar cell is prone to micro-cracks at higher temperature but observed as a random event. Modules were processed with different soldering conditions and characterized. Results show that, using the suggested soldering process, FF can be improved by 0.53, and the power output can be as high as 251.26 W, which is higher by 2.50% compared to the non-optimized process.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734949
M. Fouda, M. Khatib, Ahmed G. Radwan
Recently, Memristive elements such as memristor, memcapacitor and meminductors have become very attractive components in many applications, due to its unique behavior which can not be obtained using the other conventional elements. This paper discusses the analytical analysis of two memcapacitors connected in series and in parallel taking the effect of mismatch in mobility factor and polarity of each one. The obtained formulas of instantaneous memcapacitance for each memcapacitor are derived and four special cases are analyzed in more details. The proposed special cases are validated using PSPICE simulations showing a great matching.
{"title":"On the mathematical modeling of series and parallel memcapacitors","authors":"M. Fouda, M. Khatib, Ahmed G. Radwan","doi":"10.1109/ICM.2013.6734949","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734949","url":null,"abstract":"Recently, Memristive elements such as memristor, memcapacitor and meminductors have become very attractive components in many applications, due to its unique behavior which can not be obtained using the other conventional elements. This paper discusses the analytical analysis of two memcapacitors connected in series and in parallel taking the effect of mismatch in mobility factor and polarity of each one. The obtained formulas of instantaneous memcapacitance for each memcapacitor are derived and four special cases are analyzed in more details. The proposed special cases are validated using PSPICE simulations showing a great matching.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116609446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734948
W. Mansour, Greicy Marques-Costa, R. Velazco
Self-convergence is a property that allows distributed systems, when perturbed or badly initialized, to recover a correct operation within finite number of calculation steps. In this paper, an FPGA implementation of this algorithm is presented. The intrinsic robustness of the studied implementation with respect to soft errors resulting from radiation effects is explored by means of a fault-injected method. Obtained results put in evidence the fault-tolerance capabilities and robustness of the tested hardware-implemented algorithm.
{"title":"Robustness with respect to SEU of a hardware-implemented self-converging algorithm","authors":"W. Mansour, Greicy Marques-Costa, R. Velazco","doi":"10.1109/ICM.2013.6734948","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734948","url":null,"abstract":"Self-convergence is a property that allows distributed systems, when perturbed or badly initialized, to recover a correct operation within finite number of calculation steps. In this paper, an FPGA implementation of this algorithm is presented. The intrinsic robustness of the studied implementation with respect to soft errors resulting from radiation effects is explored by means of a fault-injected method. Obtained results put in evidence the fault-tolerance capabilities and robustness of the tested hardware-implemented algorithm.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129867625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734986
W. Mansour, R. Velazco, R. Ayoubi, H. Ziade, W. El Falou
A fully automated fault-injection method is presented. It deals with transient faults resulting from the impact of energetic particles and it can be applied early at design phase, on any circuit for which the register transfer level model is available. Results issued from its application to an Artificial Neural Network benchmark application put in evidence the accuracy of the studied method to predict error rates due to transient faults generated by the radiation environment.
{"title":"A method and an automated tool to perform SET fault-injection on HDL-based designs","authors":"W. Mansour, R. Velazco, R. Ayoubi, H. Ziade, W. El Falou","doi":"10.1109/ICM.2013.6734986","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734986","url":null,"abstract":"A fully automated fault-injection method is presented. It deals with transient faults resulting from the impact of energetic particles and it can be applied early at design phase, on any circuit for which the register transfer level model is available. Results issued from its application to an Artificial Neural Network benchmark application put in evidence the accuracy of the studied method to predict error rates due to transient faults generated by the radiation environment.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116125502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734951
S. Kala, S. Nalesh, S. Nandy, R. Narayan
This paper presents a Radix-43 based FFT architecture suitable for OFDM based WLAN applications. The radix-43 parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm2. The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.
{"title":"Design of a low power 64 point FFT architecture for WLAN applications","authors":"S. Kala, S. Nalesh, S. Nandy, R. Narayan","doi":"10.1109/ICM.2013.6734951","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734951","url":null,"abstract":"This paper presents a Radix-43 based FFT architecture suitable for OFDM based WLAN applications. The radix-43 parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm2. The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116932081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734973
A. El-rachini, H. Chible, G. Nicola, M. Barbaro, L. Raffo
Non-idealities such as static device mismatch and dynamic timing mismatch, in different architectures of multi-steps analog to digital converter affect the redundancy and performance at the output of an instrument. Redundant sign digit (RSD) is an approach of calibration have been proposed to detect and automation no anymore only for cyclic converter but also for multistage A/D with M-bits per cycle for correction of errors in order to improve the resolution and the redundancy of A/D converters and to adapt the high performance of digital signal processing system. In this paper, we will presented a behavioral model in order to investigate the impact of different sources of error at different levels of simulation based at the comparison of RSD to conventional converter with Z extra decision level (CRZ).
{"title":"Behavioural models for analog to digital conversion architectures for deep submicron technology nodes","authors":"A. El-rachini, H. Chible, G. Nicola, M. Barbaro, L. Raffo","doi":"10.1109/ICM.2013.6734973","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734973","url":null,"abstract":"Non-idealities such as static device mismatch and dynamic timing mismatch, in different architectures of multi-steps analog to digital converter affect the redundancy and performance at the output of an instrument. Redundant sign digit (RSD) is an approach of calibration have been proposed to detect and automation no anymore only for cyclic converter but also for multistage A/D with M-bits per cycle for correction of errors in order to improve the resolution and the redundancy of A/D converters and to adapt the high performance of digital signal processing system. In this paper, we will presented a behavioral model in order to investigate the impact of different sources of error at different levels of simulation based at the comparison of RSD to conventional converter with Z extra decision level (CRZ).","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133660589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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