Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497571
{"title":"Section S2: Fusion Diagnostics I&C","authors":"","doi":"10.23919/mixdes52406.2021.9497571","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497571","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123325355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497645
M. Zaborowski, D. Tomaszewski, J. Marczewski, P. Zagrajek
A new approach to an analysis of the operation of a “black box” device generating a DC output signal is presented. The signal is measured using a lock-in in voltage and current modes. A measured small frequency output admittance is used to develop an equivalent circuit of the device. The method allows for conclusions on a sensor internal structure and operation principles. It is illustrated by analysis of the operation of a SOI JLFET THz radiation sensor.
{"title":"A Simple Method for Analysis of Operation of JLFET THz Radiation Sensors","authors":"M. Zaborowski, D. Tomaszewski, J. Marczewski, P. Zagrajek","doi":"10.23919/MIXDES52406.2021.9497645","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497645","url":null,"abstract":"A new approach to an analysis of the operation of a “black box” device generating a DC output signal is presented. The signal is measured using a lock-in in voltage and current modes. A measured small frequency output admittance is used to develop an equivalent circuit of the device. The method allows for conclusions on a sensor internal structure and operation principles. It is illustrated by analysis of the operation of a SOI JLFET THz radiation sensor.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114680063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497582
Babak Agheli, A. Kalami, A. Amini
Protection relays are essential components in distribution networks that are used to protect the interphase faults and single-phase-to-ground faults. However, these relays do not assurance the protection due to the sharp growing short circuits. They may be the result of demanding more and more power usage by the commercial and residential users. Overcurrent relay (OCR) is the cost-effective and broadly used element in power system protection. In this paper, the design of an overcurrent relay in 0.18μm CMOS standard technology is performed for the protection of the 10-kilo-volts distribution system against the undesired currents. In this case, we have considered a time-reversed type relay where the operation time of the relay has a reverse proportion with its current. Firstly, crucial features of the relay are converted into digital data using electronic circuits including; encoder, analog to digital converter (ADC), multiplier, etc. In the next step, using an analog comparator leads to having the results of the comparison between the relay nominal-current and the actual line current. Finally, the value and the duration of the overcurrent are compared with the relay characteristics and the output results will ensure the circuit to continue the operation or not. Therefore, the proposed relay guarantees the protection of the system by overcurrent detection and cutting-off the system in the critical situations in a safe and fast way. Simulation results through Hspice can strongly prove the proper operation of the proposed overcurrent relay.
{"title":"Design of an Overcurrent Protection Relay Based on Electronics Technology","authors":"Babak Agheli, A. Kalami, A. Amini","doi":"10.23919/MIXDES52406.2021.9497582","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497582","url":null,"abstract":"Protection relays are essential components in distribution networks that are used to protect the interphase faults and single-phase-to-ground faults. However, these relays do not assurance the protection due to the sharp growing short circuits. They may be the result of demanding more and more power usage by the commercial and residential users. Overcurrent relay (OCR) is the cost-effective and broadly used element in power system protection. In this paper, the design of an overcurrent relay in 0.18μm CMOS standard technology is performed for the protection of the 10-kilo-volts distribution system against the undesired currents. In this case, we have considered a time-reversed type relay where the operation time of the relay has a reverse proportion with its current. Firstly, crucial features of the relay are converted into digital data using electronic circuits including; encoder, analog to digital converter (ADC), multiplier, etc. In the next step, using an analog comparator leads to having the results of the comparison between the relay nominal-current and the actual line current. Finally, the value and the duration of the overcurrent are compared with the relay characteristics and the output results will ensure the circuit to continue the operation or not. Therefore, the proposed relay guarantees the protection of the system by overcurrent detection and cutting-off the system in the critical situations in a safe and fast way. Simulation results through Hspice can strongly prove the proper operation of the proposed overcurrent relay.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128230819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497597
Braeden Morrison, M. Lukowiak
Recursion is a very efficient abstraction that can be found in definitions of many algorithms. However, recursion can be difficult to implement in hardware and as a result is not supported by the majority of high-level synthesis tools (HLS). This work introduces a new framework for implementing recursive functions in hardware, which we call TreeRecur. TreeRecur uses trees to represent the branching recursive function calls of divide-and-conquer algorithms, which makes it possible to take advantage of their procedure-level parallelism. To allow for design flexibility, TreeRecur executes algorithms using a configurable number of independent function processors. These processors are generated using HLS design flow, making it easy to implement a variety of different algorithms. Functionality of our framework was tested on a field programmable gate array (FPGA) using two simple algorithms and compared against software implementations of the same algorithms. Performance results were collected in terms of execution speed and energy consumption. The execution speeds of TreeRecur are shown to be comparable to software programs when differences in clock speed are accounted for and its energy consumption is up to 11 times better than the software solution’s.
{"title":"Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms","authors":"Braeden Morrison, M. Lukowiak","doi":"10.23919/MIXDES52406.2021.9497597","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497597","url":null,"abstract":"Recursion is a very efficient abstraction that can be found in definitions of many algorithms. However, recursion can be difficult to implement in hardware and as a result is not supported by the majority of high-level synthesis tools (HLS). This work introduces a new framework for implementing recursive functions in hardware, which we call TreeRecur. TreeRecur uses trees to represent the branching recursive function calls of divide-and-conquer algorithms, which makes it possible to take advantage of their procedure-level parallelism. To allow for design flexibility, TreeRecur executes algorithms using a configurable number of independent function processors. These processors are generated using HLS design flow, making it easy to implement a variety of different algorithms. Functionality of our framework was tested on a field programmable gate array (FPGA) using two simple algorithms and compared against software implementations of the same algorithms. Performance results were collected in terms of execution speed and energy consumption. The execution speeds of TreeRecur are shown to be comparable to software programs when differences in clock speed are accounted for and its energy consumption is up to 11 times better than the software solution’s.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134150690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497636
Amirouche Oumaziz, A. Bourennane, F. Richardeau
The paper deals with the monolithic integration of a power converter phase leg. It focuses on the integration of a power phase leg consisting of a VDMOS and an IGBT. This association is suitable for monolithic power integration in silicon. Different monolithic chips integrating phase legs were proposed and discussed in this paper. Interesting advantages can be brought by the monolithic integration of the converter phase leg. These advantages include power chips realization simplification, control of gate transistors with respect to constant voltages (DC-link or ground-0V).
{"title":"New Monolithic Multi-terminal Si-chips Integrating a Power Converter Phase-leg for Specific Applications","authors":"Amirouche Oumaziz, A. Bourennane, F. Richardeau","doi":"10.23919/MIXDES52406.2021.9497636","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497636","url":null,"abstract":"The paper deals with the monolithic integration of a power converter phase leg. It focuses on the integration of a power phase leg consisting of a VDMOS and an IGBT. This association is suitable for monolithic power integration in silicon. Different monolithic chips integrating phase legs were proposed and discussed in this paper. Interesting advantages can be brought by the monolithic integration of the converter phase leg. These advantages include power chips realization simplification, control of gate transistors with respect to constant voltages (DC-link or ground-0V).","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114898665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497616
{"title":"Section 6: Embedded Systems","authors":"","doi":"10.23919/mixdes52406.2021.9497616","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497616","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115171441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497551
{"title":"Section 1: Design of Integrated Circuits and Microsystems","authors":"","doi":"10.23919/mixdes52406.2021.9497551","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497551","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497537
Jason Blocklove, Steven Farris, M. Kurdziel, M. Lukowiak, S. Radziszowski
At different stages of the Integrated Circuit (IC) lifecycle there are attacks which threaten to compromise the integrity of the design through piracy, reverse engineering, hardware Trojan insertion, side channel analysis, and other physical attacks. Some of the most notable challenges in this field deal specifically with Intellectual Property (IP) theft and reverse engineering attacks. One method by which some of these concerns can be addressed is by introducing hardware obfuscation to the design in various forms. In this work we evaluate the effectiveness of a few different forms of netlist-level hardware obfuscation of a 16-bit substitution box component of a customizable cipher MK-3. These obfuscation methods were attacked using a satisfiability (SAT) attack, which is able to iteratively rule out classes of keys at once. This has been shown to be very effective against many forms of hardware obfuscation. A method to successfully defend against this attack is described in this paper. This method introduces a modified SIMON block cipher as a One-way Random Function (ORF) that is used to generate an obfuscation key. The S-box obfuscated using this 32-bit key and a round-reduced implementation of the SIMON cipher is shown to be secure against a SAT attack for at least 5 days.
{"title":"Hardware Obfuscation of the 16-bit S-box in the MK-3 Cipher","authors":"Jason Blocklove, Steven Farris, M. Kurdziel, M. Lukowiak, S. Radziszowski","doi":"10.23919/MIXDES52406.2021.9497537","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497537","url":null,"abstract":"At different stages of the Integrated Circuit (IC) lifecycle there are attacks which threaten to compromise the integrity of the design through piracy, reverse engineering, hardware Trojan insertion, side channel analysis, and other physical attacks. Some of the most notable challenges in this field deal specifically with Intellectual Property (IP) theft and reverse engineering attacks. One method by which some of these concerns can be addressed is by introducing hardware obfuscation to the design in various forms. In this work we evaluate the effectiveness of a few different forms of netlist-level hardware obfuscation of a 16-bit substitution box component of a customizable cipher MK-3. These obfuscation methods were attacked using a satisfiability (SAT) attack, which is able to iteratively rule out classes of keys at once. This has been shown to be very effective against many forms of hardware obfuscation. A method to successfully defend against this attack is described in this paper. This method introduces a modified SIMON block cipher as a One-way Random Function (ORF) that is used to generate an obfuscation key. The S-box obfuscated using this 32-bit key and a round-reduced implementation of the SIMON cipher is shown to be secure against a SAT attack for at least 5 days.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131586773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497565
I. Pandiev
A simple PSpice macromodel was developed, and verified for monolithic power amplifiers operated with a single-supply voltage. The proposed macromodel is developed using simplification and build-up techniques for macromodeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macromodel also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model was implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit was built using standard PSpice components and analog behavioral (ABM) blocks. The accuracy of the model was verified by comparing the simulation results of the electrical parameters with the respectively measured values by experimental testing of sample circuits. The comparative analysis showed that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.
{"title":"Development of PSpice Macromodel for Monolithic Single-Supply Power Amplifiers","authors":"I. Pandiev","doi":"10.23919/MIXDES52406.2021.9497565","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497565","url":null,"abstract":"A simple PSpice macromodel was developed, and verified for monolithic power amplifiers operated with a single-supply voltage. The proposed macromodel is developed using simplification and build-up techniques for macromodeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macromodel also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model was implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit was built using standard PSpice components and analog behavioral (ABM) blocks. The accuracy of the model was verified by comparing the simulation results of the electrical parameters with the respectively measured values by experimental testing of sample circuits. The comparative analysis showed that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126789764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497553
{"title":"Section 2: Thermal Issues in Microelectronics","authors":"","doi":"10.23919/mixdes52406.2021.9497553","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497553","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127028999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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