Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497565
I. Pandiev
A simple PSpice macromodel was developed, and verified for monolithic power amplifiers operated with a single-supply voltage. The proposed macromodel is developed using simplification and build-up techniques for macromodeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macromodel also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model was implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit was built using standard PSpice components and analog behavioral (ABM) blocks. The accuracy of the model was verified by comparing the simulation results of the electrical parameters with the respectively measured values by experimental testing of sample circuits. The comparative analysis showed that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.
{"title":"Development of PSpice Macromodel for Monolithic Single-Supply Power Amplifiers","authors":"I. Pandiev","doi":"10.23919/MIXDES52406.2021.9497565","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497565","url":null,"abstract":"A simple PSpice macromodel was developed, and verified for monolithic power amplifiers operated with a single-supply voltage. The proposed macromodel is developed using simplification and build-up techniques for macromodeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macromodel also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model was implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit was built using standard PSpice components and analog behavioral (ABM) blocks. The accuracy of the model was verified by comparing the simulation results of the electrical parameters with the respectively measured values by experimental testing of sample circuits. The comparative analysis showed that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126789764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497563
K. Górecki, K. Posobkiewicz
The paper analyses the usefulness of selected thermo-sensitive parameters (TSP) in measuring thermal resistance of power MOS transistors. Three TSPs were considered: threshold voltage, voltage at the forward biased drain-substrate junction and voltage between the drain and the source of the transistor operating in the linear range. For each of the mentioned TSPs, thermometric characteristics were measured at selected current values. The linear range of each of the measured characteristics was discussed. An analysis of the measurement error of thermal resistance of a selected power MOS transistor was carried out using each of the considered TSPs. The results of thermal resistance measurements performed using the considered TSPs and a thermoresistor were compared and discussed.
{"title":"Comparison of the Usefulness of Selected Thermo-sensitive Parameters of Power MOSFETs","authors":"K. Górecki, K. Posobkiewicz","doi":"10.23919/MIXDES52406.2021.9497563","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497563","url":null,"abstract":"The paper analyses the usefulness of selected thermo-sensitive parameters (TSP) in measuring thermal resistance of power MOS transistors. Three TSPs were considered: threshold voltage, voltage at the forward biased drain-substrate junction and voltage between the drain and the source of the transistor operating in the linear range. For each of the mentioned TSPs, thermometric characteristics were measured at selected current values. The linear range of each of the measured characteristics was discussed. An analysis of the measurement error of thermal resistance of a selected power MOS transistor was carried out using each of the considered TSPs. The results of thermal resistance measurements performed using the considered TSPs and a thermoresistor were compared and discussed.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126689823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497643
G. Wirth
Modeling and simulation of charge trapping is discussed in the context of random telegraph noise (RTN), bias temperature instability (BTI) and low-frequency noise (1/f noise), aiming unified compact modeling. Analytical formulations for 1/f noise (frequency domain), RTN (time domain) and BTI have been derived, using a single modeling framework, where model parameters are the same in frequency and time domain. The area scaling of 1/f noise, RTN and BTI is discussed in detail, as well as its variability among devices that by design should be identical. The modeling addresses the time dependent variability in the electrical behavior of devices and circuits.
{"title":"Modeling and Simulation of Charge Trapping in 1/f Noise, RTN and BTI: from Devices to Circuits","authors":"G. Wirth","doi":"10.23919/MIXDES52406.2021.9497643","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497643","url":null,"abstract":"Modeling and simulation of charge trapping is discussed in the context of random telegraph noise (RTN), bias temperature instability (BTI) and low-frequency noise (1/f noise), aiming unified compact modeling. Analytical formulations for 1/f noise (frequency domain), RTN (time domain) and BTI have been derived, using a single modeling framework, where model parameters are the same in frequency and time domain. The area scaling of 1/f noise, RTN and BTI is discussed in detail, as well as its variability among devices that by design should be identical. The modeling addresses the time dependent variability in the electrical behavior of devices and circuits.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131725267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497577
{"title":"Section S1: Compact Modeling for Semiconductor Device, Sensor and IC Design","authors":"","doi":"10.23919/mixdes52406.2021.9497577","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497577","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497579
{"title":"Section 4: Power Electronics","authors":"","doi":"10.23919/mixdes52406.2021.9497579","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497579","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133960601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497641
A. Yesayan, J. Sallese
In this work, we present a simple compact model for junctionless ion-sensitive FETs (JL ISFET) operating in depletion. The sensitivity dependence on nanowire physical and geometrical parameters are discussed as guidelines for the device optimization. The model validation with COMSOL Multiphysics simulations is presented.
{"title":"Compact Analytical Model of Nanowire Junctionless ISFET","authors":"A. Yesayan, J. Sallese","doi":"10.23919/MIXDES52406.2021.9497641","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497641","url":null,"abstract":"In this work, we present a simple compact model for junctionless ion-sensitive FETs (JL ISFET) operating in depletion. The sensitivity dependence on nanowire physical and geometrical parameters are discussed as guidelines for the device optimization. The model validation with COMSOL Multiphysics simulations is presented.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497601
Piotr Amrozik, K. Hałagan, K. Rudnicki
ARUZ (Analizator Rzeczywistych Układów Złożonych, Analyser of Real Complex Systems) is a massively parallel FPGA-based simulator located at BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Lattice Liquid (DLL) algorithm in hardware. In this paper, FPGA implementation details are presented for DLL functionality extension. This extension allows to simulate simple chemical reactions of first and second order realized in a parallel approach.
ARUZ (analyzer Rzeczywistych Układów Złożonych，分析仪of Real Complex Systems)是位于bionanpark Lodz的大规模并行fpga模拟器。这台机器在硬件上体现了动态点阵液体(DLL)算法。本文给出了DLL功能扩展的FPGA实现细节。这个扩展允许模拟一阶和二阶的简单化学反应，以并行的方式实现。
{"title":"Modelling of First- and Second-order Chemical Reactions on ARUZ – Massively-parallel FPGA-based Machine","authors":"Piotr Amrozik, K. Hałagan, K. Rudnicki","doi":"10.23919/MIXDES52406.2021.9497601","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497601","url":null,"abstract":"ARUZ (Analizator Rzeczywistych Układów Złożonych, Analyser of Real Complex Systems) is a massively parallel FPGA-based simulator located at BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Lattice Liquid (DLL) algorithm in hardware. In this paper, FPGA implementation details are presented for DLL functionality extension. This extension allows to simulate simple chemical reactions of first and second order realized in a parallel approach.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"37 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132850614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497554
T. Stefański, K. Rudnicki, Wojciech Zebrowski
Recently, we have opened the source code of coprocessor for multiple-precision arithmetic (MPA). In this contribution, the implementation and benchmarking results for this MPA coprocessor are presented on modern Zynq Ultrascale+ multiprocessor system on chip, which combines field-programmable gate array with quad-core ARM Cortex-A53 64-bit central processing unit (CPU). In our benchmark, a single coprocessor can be up to 4.5 times faster than a single CPU core within the same chip emulating MPA using a software library.
{"title":"Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale+ MPSoC","authors":"T. Stefański, K. Rudnicki, Wojciech Zebrowski","doi":"10.23919/MIXDES52406.2021.9497554","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497554","url":null,"abstract":"Recently, we have opened the source code of coprocessor for multiple-precision arithmetic (MPA). In this contribution, the implementation and benchmarking results for this MPA coprocessor are presented on modern Zynq Ultrascale+ multiprocessor system on chip, which combines field-programmable gate array with quad-core ARM Cortex-A53 64-bit central processing unit (CPU). In our benchmark, a single coprocessor can be up to 4.5 times faster than a single CPU core within the same chip emulating MPA using a software library.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114276989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497506
{"title":"[Title page]","authors":"","doi":"10.23919/mixdes52406.2021.9497506","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497506","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"485 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497528
M. Kucharski, M. Widlok, P. Bajurko, R. Piesiewicz
This paper presents an 89–102 GHz I/Q receiver (RX) containing an LO frequency multiplying chain (×4) manufactured in SiGe BiCMOS technology. The RX entails a two-stage low-noise amplifier (LNA) followed by a lumped version of Wilkinson power splitter to feed two mixers driven by LO signals shifted by 90 degrees. Quadrature LO signals are generated using a reduced-size branchline coupler. The mixing stage enables conversion gain (CG) tuning in 13.2–26.8 dB range at 94 GHz by means of pMOS transistors biased in triode region. The RX provides 13GHz 3-dB bandwidth with peak CG of 26.8 dB and NF of 11.7 dB consuming 80mA from 3.3V supply. The chip occupies 1.07mm2 silicon area.
{"title":"A W-band SiGe BiCMOS I/Q Receiver with Tunable Conversion Gain for Radar Applications","authors":"M. Kucharski, M. Widlok, P. Bajurko, R. Piesiewicz","doi":"10.23919/MIXDES52406.2021.9497528","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497528","url":null,"abstract":"This paper presents an 89–102 GHz I/Q receiver (RX) containing an LO frequency multiplying chain (×4) manufactured in SiGe BiCMOS technology. The RX entails a two-stage low-noise amplifier (LNA) followed by a lumped version of Wilkinson power splitter to feed two mixers driven by LO signals shifted by 90 degrees. Quadrature LO signals are generated using a reduced-size branchline coupler. The mixing stage enables conversion gain (CG) tuning in 13.2–26.8 dB range at 94 GHz by means of pMOS transistors biased in triode region. The RX provides 13GHz 3-dB bandwidth with peak CG of 26.8 dB and NF of 11.7 dB consuming 80mA from 3.3V supply. The chip occupies 1.07mm2 silicon area.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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