Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227076
Nan Jiang Nan Jiang, J. Pisharath, A. Choudhary
Communication systems with multiple computing resources are gaining popularity. These devices consume a considerable amount of energy, and require that the system resources be fully utilized at all times. In this paper, we aim to reduce the energy consumption and also improve the system utilization by incorporating performance-enhancement and power-optimization techniques into a multi-resource heterogeneous communication system. We study the performance and energy improvements contributed by our techniques, using a traditional evaluation framework. However, this framework fails to clearly model the performance-energy tradeoffs in the system. Hence, we propose a more relevant framework with a new metric named Energy-resource efficiency (ERE) to study these systems. ERE defines a link between the performance and energy variations in a system to clearly highlight the various performance-energy tradeoffs. Our experimental results shown that, when ERE is used to calibrate the performance-energy tradeoffs, one can achieve up to 80% performance and energy gains in a power-aware heterogeneous communication system.
{"title":"Characterizing and improving energy-delay tradeoffs in heterogeneous communication systems","authors":"Nan Jiang Nan Jiang, J. Pisharath, A. Choudhary","doi":"10.1109/SCS.2003.1227076","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227076","url":null,"abstract":"Communication systems with multiple computing resources are gaining popularity. These devices consume a considerable amount of energy, and require that the system resources be fully utilized at all times. In this paper, we aim to reduce the energy consumption and also improve the system utilization by incorporating performance-enhancement and power-optimization techniques into a multi-resource heterogeneous communication system. We study the performance and energy improvements contributed by our techniques, using a traditional evaluation framework. However, this framework fails to clearly model the performance-energy tradeoffs in the system. Hence, we propose a more relevant framework with a new metric named Energy-resource efficiency (ERE) to study these systems. ERE defines a link between the performance and energy variations in a system to clearly highlight the various performance-energy tradeoffs. Our experimental results shown that, when ERE is used to calibrate the performance-energy tradeoffs, one can achieve up to 80% performance and energy gains in a power-aware heterogeneous communication system.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124535389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227067
H. Ahmadi, O. Shoaei, M. Azizi
An 8-bit, 150 MS/s folding interpolating ADC in a digital CMOS technology is described. The developed converter uses resistor interpolation method along with the fully-differential, continuous-time, and open-loop circuitry in order to achieve a high speed operation with low area and power consumption. Also the number of latches in the digital encoder block is reduced using previously described analog encoding. The simulation results of the converter in 0.25 μm CMOS are presented. The ADC power dissipation from a 3V power supply is 310 mW at 150 MHz sampling rate.
{"title":"An 8-bit, 150 MS/s folding and interpolating ADC in 0.25 μm CMOS with resistive averaging","authors":"H. Ahmadi, O. Shoaei, M. Azizi","doi":"10.1109/SCS.2003.1227067","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227067","url":null,"abstract":"An 8-bit, 150 MS/s folding interpolating ADC in a digital CMOS technology is described. The developed converter uses resistor interpolation method along with the fully-differential, continuous-time, and open-loop circuitry in order to achieve a high speed operation with low area and power consumption. Also the number of latches in the digital encoder block is reduced using previously described analog encoding. The simulation results of the converter in 0.25 μm CMOS are presented. The ADC power dissipation from a 3V power supply is 310 mW at 150 MHz sampling rate.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226998
L. Fanucci, A. Giambastiani, C. Rosadini
This paper presents the verification process performed during the development of an automotive platform suited to interface a generic sensor. The platform aims to reduce the cost of the analog circuitry needed to interface the sensor, by massive usage of digital electronic, and by addressing a wide class of automotive applications based on sensor signal elaboration. Particularly, all the verification steps from identification of the right level of abstraction and hierarchy, platform hardware-software co-simulation and prototype hardware emulation are described.
{"title":"VLSI design and verification methodologies for automotive embedded systems","authors":"L. Fanucci, A. Giambastiani, C. Rosadini","doi":"10.1109/SCS.2003.1226998","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226998","url":null,"abstract":"This paper presents the verification process performed during the development of an automotive platform suited to interface a generic sensor. The platform aims to reduce the cost of the analog circuitry needed to interface the sensor, by massive usage of digital electronic, and by addressing a wide class of automotive applications based on sensor signal elaboration. Particularly, all the verification steps from identification of the right level of abstraction and hierarchy, platform hardware-software co-simulation and prototype hardware emulation are described.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126780673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226946
S. Ciochină, C. Anghel, A. Enescu
Transmit diversity is a very attractive solution for efficient communications through fading wireless channels. The paper presents some aspects concerning the synthesis of the coding matrix in a multiantenna configuration. Because no optimal (maximum coding advantage, maximum transmission rate, minimum delay) codes can be found for systems with more than two antennas, some sub-optimal solutions are analyzed.
{"title":"Sub-optimal solutions to code synthesis for space-time diversity","authors":"S. Ciochină, C. Anghel, A. Enescu","doi":"10.1109/SCS.2003.1226946","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226946","url":null,"abstract":"Transmit diversity is a very attractive solution for efficient communications through fading wireless channels. The paper presents some aspects concerning the synthesis of the coding matrix in a multiantenna configuration. Because no optimal (maximum coding advantage, maximum transmission rate, minimum delay) codes can be found for systems with more than two antennas, some sub-optimal solutions are analyzed.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132566440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227112
M. Hnatiuc, G. Lamarque
The purpose of this work is to stimulate a neural network with non-linear activation functions. The non-linear functions are simulated in Microsoft Visual Studio C++ 6.0 to observe the precision and to implement on the programmable logic devices. This network is realized to accept very small input values. The multiplication between input values and weight values is realized with the add-logarithm and exponential functions. One approximates all the non-linear functions with linear functions using shift-add blocks.
这项工作的目的是用非线性激活函数来刺激神经网络。在Microsoft Visual Studio c++ 6.0中对非线性函数进行仿真，观察其精度并在可编程逻辑器件上实现。该网络可以接受非常小的输入值。输入值与权值之间的乘法是通过加对数和指数函数实现的。一个近似所有的非线性函数与线性函数使用移位加块。
{"title":"Implementation of neural network with approximations functions","authors":"M. Hnatiuc, G. Lamarque","doi":"10.1109/SCS.2003.1227112","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227112","url":null,"abstract":"The purpose of this work is to stimulate a neural network with non-linear activation functions. The non-linear functions are simulated in Microsoft Visual Studio C++ 6.0 to observe the precision and to implement on the programmable logic devices. This network is realized to accept very small input values. The multiplication between input values and weight values is realized with the add-logarithm and exponential functions. One approximates all the non-linear functions with linear functions using shift-add blocks.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131864110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227139
M. V. Nemescu, D. Lucache, D. Ioachim
The paper purpose is to present the existence and appearance of the slow oscillations, based on resonant jumps, in circuits or systems described by Duffing-type equation having a nonlinearity coefficient with inertial variation. The conditions necessary for jump producing and for slow oscillations appearance are emphasized. The theoretical approach is confirmed by numerical simulation.
{"title":"Slow oscillations in circuits and nonlinear systems described by Duffing equation","authors":"M. V. Nemescu, D. Lucache, D. Ioachim","doi":"10.1109/SCS.2003.1227139","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227139","url":null,"abstract":"The paper purpose is to present the existence and appearance of the slow oscillations, based on resonant jumps, in circuits or systems described by Duffing-type equation having a nonlinearity coefficient with inertial variation. The conditions necessary for jump producing and for slow oscillations appearance are emphasized. The theoretical approach is confirmed by numerical simulation.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"59 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130306391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226993
D. Cepareanu, N. Lucanu, I. Pletea
This paper presents the analyzing of a lower sideband up converter, made in the microstrip technology, for which the input signals have the frequency range 2.3 GHz and the output signals have the frequency range 22 GHz.
{"title":"Lower sideband up converter with varactor diode","authors":"D. Cepareanu, N. Lucanu, I. Pletea","doi":"10.1109/SCS.2003.1226993","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226993","url":null,"abstract":"This paper presents the analyzing of a lower sideband up converter, made in the microstrip technology, for which the input signals have the frequency range 2.3 GHz and the output signals have the frequency range 22 GHz.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116358465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227105
I. Bogdan, C. Comsa
Smart antennas are considered vital components of the future 3G mobile communication networks based on www.symena.com, G.V. Tsoulos et al. (2000), and P. Gendren (2002). The topic is very broad in nature and includes adaptation algorithms according to Y.S. Song et al. (2001) and C. Paleologu et al. (2002), receiver architecture, channel modeling and estimation, adaptive coding, antenna theory by H.S. Cho et al. (2001), A. Sabharwal et al. (2000) and M.L. Leou et al. (2000) etc. This paper is a study of circular array applications as smart antennas intended to evaluate the advantages and the drawbacks and to establish guidelines to design its parameters. A classification of smart antennas is also included.
{"title":"Analysis of circular arrays as smart antennas for cellular networks","authors":"I. Bogdan, C. Comsa","doi":"10.1109/SCS.2003.1227105","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227105","url":null,"abstract":"Smart antennas are considered vital components of the future 3G mobile communication networks based on www.symena.com, G.V. Tsoulos et al. (2000), and P. Gendren (2002). The topic is very broad in nature and includes adaptation algorithms according to Y.S. Song et al. (2001) and C. Paleologu et al. (2002), receiver architecture, channel modeling and estimation, adaptive coding, antenna theory by H.S. Cho et al. (2001), A. Sabharwal et al. (2000) and M.L. Leou et al. (2000) etc. This paper is a study of circular array applications as smart antennas intended to evaluate the advantages and the drawbacks and to establish guidelines to design its parameters. A classification of smart antennas is also included.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114590073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227012
H. Ebrahimirad, S. Vaez‐Zadeh, M. Jalili-Kharaajoo
In this paper, a sliding mode controller is applied to a permanent magnet synchronous motor. A semi-linearized model is introduced for quick speed controller design and evaluation. Finally, the proposed control action is compared with that of a PI controller. Simulation results reveal the effectiveness of the proposed sliding mode controller.
{"title":"Robust sliding mode control applied to speed control of PM synchronous motors","authors":"H. Ebrahimirad, S. Vaez‐Zadeh, M. Jalili-Kharaajoo","doi":"10.1109/SCS.2003.1227012","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227012","url":null,"abstract":"In this paper, a sliding mode controller is applied to a permanent magnet synchronous motor. A semi-linearized model is introduced for quick speed controller design and evaluation. Finally, the proposed control action is compared with that of a PI controller. Simulation results reveal the effectiveness of the proposed sliding mode controller.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114909163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227095
M. Siripruchyanun, P. Wardkein, Sunee Kurutuch
This article presents a novel approach to implement PWM signal generator using CMOS transconductors, its scheme comprises CMOS Schmitt trigger and voltage to current converter. It can originate PWM signal over a wide frequency range arising from differentiation of modulating input signal in the provided time. The outstanding feature of the proposed scheme is that the PWM output has frequency-constant, which does not depend on amplitude of the modulating signal. This makes it suitable to use in application of adjacent frequency between carrier and modulating signal, which differs from the conventional PWM signal generators. The proposed circuit has relatively simpler scheme. It consists of exclusively 12 MOS transistors, 3 current sources, 1 capacitor and 2 resistors, thus it is suitable for further fabrication through CMOS technology. Furthermore, its frequency and amplitude of PWM output signal can be independently adjusted by electronic method. The SPICE simulation results are shown, which are in correspondence to theoretical anticipation.
{"title":"An integrable CMOS transconductors-based differentiated input/frequency-constant PWM signal generator","authors":"M. Siripruchyanun, P. Wardkein, Sunee Kurutuch","doi":"10.1109/SCS.2003.1227095","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227095","url":null,"abstract":"This article presents a novel approach to implement PWM signal generator using CMOS transconductors, its scheme comprises CMOS Schmitt trigger and voltage to current converter. It can originate PWM signal over a wide frequency range arising from differentiation of modulating input signal in the provided time. The outstanding feature of the proposed scheme is that the PWM output has frequency-constant, which does not depend on amplitude of the modulating signal. This makes it suitable to use in application of adjacent frequency between carrier and modulating signal, which differs from the conventional PWM signal generators. The proposed circuit has relatively simpler scheme. It consists of exclusively 12 MOS transistors, 3 current sources, 1 capacitor and 2 resistors, thus it is suitable for further fabrication through CMOS technology. Furthermore, its frequency and amplitude of PWM output signal can be independently adjusted by electronic method. The SPICE simulation results are shown, which are in correspondence to theoretical anticipation.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122023648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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