Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226938
Y. Andreyev, B. A. Khadgi, V. A. Morozov, S. Starkov
This paper estimates BER for Ultrawideband Direct Chaotic Communications (UWDCC) through multipath indoor channel is obtained.
本文对室内多径超宽带直接混沌通信(UWDCC)的误码率进行了估计。
{"title":"Ultrawideband multipath indoor channel for direct chaotic communications","authors":"Y. Andreyev, B. A. Khadgi, V. A. Morozov, S. Starkov","doi":"10.1109/SCS.2003.1226938","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226938","url":null,"abstract":"This paper estimates BER for Ultrawideband Direct Chaotic Communications (UWDCC) through multipath indoor channel is obtained.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128360432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226939
J. L. Tecpanecatl-Xihuitl, M. Bayoumi
This paper presents an efficient multistage decimation filter using a specific decomposition multistage and pipeline/interleaving technique to reduce the amount of multiplications. The multistage decimator filter is an important block on digital IF receivers for advanced dedicated mobile data technology called Mobitex and Ardis networks. The results are presented and compared with current results in the literature. The frequency response shows that the requirements are reached and the amount of multiplications is highly reduced. In each case, we get results with an improvement of 55% and 45% just in the multistage decimation filter. Additionally, using PI techniques we just need a single filter to process the components I, and Q in the IF digital receiver.
{"title":"Efficient multistage decimation filter using pipeline/interleaving architectures for digital IF receiver","authors":"J. L. Tecpanecatl-Xihuitl, M. Bayoumi","doi":"10.1109/SCS.2003.1226939","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226939","url":null,"abstract":"This paper presents an efficient multistage decimation filter using a specific decomposition multistage and pipeline/interleaving technique to reduce the amount of multiplications. The multistage decimator filter is an important block on digital IF receivers for advanced dedicated mobile data technology called Mobitex and Ardis networks. The results are presented and compared with current results in the literature. The frequency response shows that the requirements are reached and the amount of multiplications is highly reduced. In each case, we get results with an improvement of 55% and 45% just in the multistage decimation filter. Additionally, using PI techniques we just need a single filter to process the components I, and Q in the IF digital receiver.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128765794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227138
D. Cafagna, G. Grassi
This paper deals with hyperchaos synchronization via a scalar signal. By exploiting observer design and time-division multiplexing of the transmitted signal, a novel framework for synchronizing hyperchaotic circuits with one or several non-linearities is proposed. The approach is successfully applied to 8th order circuits with one non-linearity as well as to 6th order circuits with two non-linearities.
{"title":"Synchronizing hyperchaotic systems with several non-linearities: observer design and time-division multiplexing of the scalar signal","authors":"D. Cafagna, G. Grassi","doi":"10.1109/SCS.2003.1227138","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227138","url":null,"abstract":"This paper deals with hyperchaos synchronization via a scalar signal. By exploiting observer design and time-division multiplexing of the transmitted signal, a novel framework for synchronizing hyperchaotic circuits with one or several non-linearities is proposed. The approach is successfully applied to 8th order circuits with one non-linearity as well as to 6th order circuits with two non-linearities.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226997
J. Plosila, P. Liljeberg, J. Isoaho
This paper describes an on-chip bus architecture targeted for the globally asynchronous locally synchronous system-on-chip design strategy. The proposed pipelined bus structure is composed of asynchronously interacting segments which can operate in parallel. The bus is segmented using transfer stages which partition bus into a set of point-to-point interconnects. Self-timed arbitration and control is distributed among the pipelined stages to enable parallel operation of distinct segments, to prevent problems present in a globally clocked system, and to increase design modularity. In a 0.18 μm technology, each bus segment is capable of transferring data at a maximum throughput of 1.2 giga data items per second concurrently in both directions.
{"title":"Pipelined on-chip bus architecture with distributed self-timed control","authors":"J. Plosila, P. Liljeberg, J. Isoaho","doi":"10.1109/SCS.2003.1226997","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226997","url":null,"abstract":"This paper describes an on-chip bus architecture targeted for the globally asynchronous locally synchronous system-on-chip design strategy. The proposed pipelined bus structure is composed of asynchronously interacting segments which can operate in parallel. The bus is segmented using transfer stages which partition bus into a set of point-to-point interconnects. Self-timed arbitration and control is distributed among the pipelined stages to enable parallel operation of distinct segments, to prevent problems present in a globally clocked system, and to increase design modularity. In a 0.18 μm technology, each bus segment is capable of transferring data at a maximum throughput of 1.2 giga data items per second concurrently in both directions.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117080145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227114
B. Metin, E. Arslan, O. Cicekoglu
Current conveyor was developed by Sedra at almost the same time with the commercial IC opamp in 1968. Although it is one of the oldest active components and has a better frequency response than opamp, there are not as many applications presented in the literature as with the opamp that is used in a wide variety of applications in electronic circuits. This paper aims to use this old however beneficial element in the analogue filter area by giving several new all-pass filter applications. All circuits given employ a single capacitor and are therefore canonic in the number of capacitors.
{"title":"All-pass sections realized with single first generation current conveyor","authors":"B. Metin, E. Arslan, O. Cicekoglu","doi":"10.1109/SCS.2003.1227114","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227114","url":null,"abstract":"Current conveyor was developed by Sedra at almost the same time with the commercial IC opamp in 1968. Although it is one of the oldest active components and has a better frequency response than opamp, there are not as many applications presented in the literature as with the opamp that is used in a wide variety of applications in electronic circuits. This paper aims to use this old however beneficial element in the analogue filter area by giving several new all-pass filter applications. All circuits given employ a single capacitor and are therefore canonic in the number of capacitors.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122320173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226989
C. Neacsu
The paper investigates a new multi-tone harmonic balance approach based on multivariate representation of multirate signals. The proposed algorithm generates the new Newton-Raphson iterate using an iterative method based on Krylov subspaces - namely the GMRES method. An example of using the simulator developed around the proposed method is finally shown.
{"title":"Multirate harmonic balance simulation","authors":"C. Neacsu","doi":"10.1109/SCS.2003.1226989","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226989","url":null,"abstract":"The paper investigates a new multi-tone harmonic balance approach based on multivariate representation of multirate signals. The proposed algorithm generates the new Newton-Raphson iterate using an iterative method based on Krylov subspaces - namely the GMRES method. An example of using the simulator developed around the proposed method is finally shown.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129749194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227082
A. I. Galarniotis, A. Tsakoumis, P. Fessas, S. Vladov, V. Mladenov
Finite impulse response (FIR) neural network and Elman neural network have been compared in electric load prediction. An FIR neural network has been trained with a temporal back-propagation learning algorithm and the results obtained showed that the effectiveness of the algorithm is more important than the applied network model. The comparison between both networks and the standard approach with Multilayer perceptron (MLP) network, demonstrates that the FIR network acts adequately. It performs better than the Elman network. Both networks perform better than the MLP network.
{"title":"Using Elman and FIR neural networks for short term electric load forecasting","authors":"A. I. Galarniotis, A. Tsakoumis, P. Fessas, S. Vladov, V. Mladenov","doi":"10.1109/SCS.2003.1227082","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227082","url":null,"abstract":"Finite impulse response (FIR) neural network and Elman neural network have been compared in electric load prediction. An FIR neural network has been trained with a temporal back-propagation learning algorithm and the results obtained showed that the effectiveness of the algorithm is more important than the applied network model. The comparison between both networks and the standard approach with Multilayer perceptron (MLP) network, demonstrates that the FIR network acts adequately. It performs better than the Elman network. Both networks perform better than the MLP network.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126833564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226980
G. Grassi, D. Cafagna
In this paper modeling, analysis and design of a class of Cellular Neural Networks (CNNs) are discussed. In particular, a discrete-time CNN model is introduced and the global asymptotic stability of its equilibrium point is analyzed. By taking into account such stability results, a novel technique for designing associative memories is developed. The objective is achieved by satisfying frequency domain stability criteria via feedback parameters related to circulant matrices. The approach, by generating CNN's conditions, enables both hetero-associative and auto-associative memories to be designed. Finally, two examples highlight the capabilities of the designed networks in storing and retrieving information.
{"title":"Modeling, analysis and design of a class of cellular neural networks","authors":"G. Grassi, D. Cafagna","doi":"10.1109/SCS.2003.1226980","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226980","url":null,"abstract":"In this paper modeling, analysis and design of a class of Cellular Neural Networks (CNNs) are discussed. In particular, a discrete-time CNN model is introduced and the global asymptotic stability of its equilibrium point is analyzed. By taking into account such stability results, a novel technique for designing associative memories is developed. The objective is achieved by satisfying frequency domain stability criteria via feedback parameters related to circulant matrices. The approach, by generating CNN's conditions, enables both hetero-associative and auto-associative memories to be designed. Finally, two examples highlight the capabilities of the designed networks in storing and retrieving information.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126668933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226990
A. Maxim
A 10 Gb/s EAM driver was realized in a 0.2μ SiGe technology having a 60 GHz transition frequency. Fast switching was achieved with a cascoded output switch, while low voltage operation was assured using a tail resistor that generates the modulation current in conjunction with a common-mode feedback. Inductive peaking and PTAT biasing was used throughout the signal path, enhancing switching speed and minimizing temperature and process variation of the AC performances. The power dissipation was reduced with 30% by using push-pull emitter follower architecture. ICs main specifications are: supply voltage4.75-5.5V, modulation current 40-120mA, rise/fall time <25ps, deterministic jitter <15ps and die area 1.3×1.7mm2.
{"title":"A 10 Gb/s electro-absorption-modulator (EAM) driver using push-pull emitter followers and a cascoded output switch","authors":"A. Maxim","doi":"10.1109/SCS.2003.1226990","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226990","url":null,"abstract":"A 10 Gb/s EAM driver was realized in a 0.2μ SiGe technology having a 60 GHz transition frequency. Fast switching was achieved with a cascoded output switch, while low voltage operation was assured using a tail resistor that generates the modulation current in conjunction with a common-mode feedback. Inductive peaking and PTAT biasing was used throughout the signal path, enhancing switching speed and minimizing temperature and process variation of the AC performances. The power dissipation was reduced with 30% by using push-pull emitter follower architecture. ICs main specifications are: supply voltage4.75-5.5V, modulation current 40-120mA, rise/fall time <25ps, deterministic jitter <15ps and die area 1.3×1.7mm2.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129266849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227000
L. Vornicu, L. Dimitriu
A method to enhance the data transmission performances in a real-time complex system is presented. It uses serial multiplexed buses that assure high performances in data transmission concerning a minimum rate of errors and a reduced latency according to L. Vornicu (2000) and R. Jurgen (1995). The reliability can be increased based on redundancy feature of bus system used. The method could be interesting from designer's point of view, but also could be useful for the users, giving a new approach in multiplex wiring real-time complex system analysis and design.
{"title":"A method to enhance data transfer performances in a real-time complex system using serial multiplexed bus","authors":"L. Vornicu, L. Dimitriu","doi":"10.1109/SCS.2003.1227000","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227000","url":null,"abstract":"A method to enhance the data transmission performances in a real-time complex system is presented. It uses serial multiplexed buses that assure high performances in data transmission concerning a minimum rate of errors and a reduced latency according to L. Vornicu (2000) and R. Jurgen (1995). The reliability can be increased based on redundancy feature of bus system used. The method could be interesting from designer's point of view, but also could be useful for the users, giving a new approach in multiplex wiring real-time complex system analysis and design.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125461557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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