Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946974
G. Mazzini, R. Rovatti, G. Setti
Classical tools for statistical analysis of chaotic maps can be generalized to express any-order joint probability of the state and thus any-order correlation functions of the trajectories. When trajectories are quantized correlations can be naturally expressed as combinations of tensors. These expressions feature noteworthy properties when,. piecewise-affine Markov maps are considered. The class of (n,t)-tailed shifts spans the range of maps producing exponentially vanishing correlation and allows the derivation of an analytical expression for any-order quantized correlation functions.
{"title":"Statistical approach to discrete-time chaotic systems: advanced tools for quantized chaotic trajectories","authors":"G. Mazzini, R. Rovatti, G. Setti","doi":"10.1109/TUTCAS.2001.946974","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946974","url":null,"abstract":"Classical tools for statistical analysis of chaotic maps can be generalized to express any-order joint probability of the state and thus any-order correlation functions of the trajectories. When trajectories are quantized correlations can be naturally expressed as combinations of tensors. These expressions feature noteworthy properties when,. piecewise-affine Markov maps are considered. The class of (n,t)-tailed shifts spans the range of maps producing exponentially vanishing correlation and allows the derivation of an analytical expression for any-order quantized correlation functions.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946901
T. S. Lande
This article discusses neuromorphic medical electronics including biological computation, neuromorphic coding, neuromorphic hardware and neuromorphic instrumentation. Two examples are given from the auditory system: a silicon cochlea and a neuromorphic cochlea implant.
{"title":"Neuromorphic medical electronics","authors":"T. S. Lande","doi":"10.1109/TUTCAS.2001.946901","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946901","url":null,"abstract":"This article discusses neuromorphic medical electronics including biological computation, neuromorphic coding, neuromorphic hardware and neuromorphic instrumentation. Two examples are given from the auditory system: a silicon cochlea and a neuromorphic cochlea implant.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132032973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946967
G. Gielen
The author discusses the systematic design of data converters. The topics covered include: performance limits in analog designs; data converter design flow; architectural design; circuit design; and layout generation.
{"title":"Systematic design of data converters","authors":"G. Gielen","doi":"10.1109/TUTCAS.2001.946967","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946967","url":null,"abstract":"The author discusses the systematic design of data converters. The topics covered include: performance limits in analog designs; data converter design flow; architectural design; circuit design; and layout generation.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125064641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946983
H. Veendrick
Scaling results in: increasing design productivity gap; increasing mask costs; increasing leakage currents; increasing noise while noise margins reduce; increasing test costs; increasing technology costs due to approaching the limits. Design measures to limit leakage and noise and to support testing and debug, require an increasing number of transistors (up to 20-40%) and more complex processes to support embedded options. The move to the next technology will become less and less commercially attractive.
{"title":"The future of semiconductors; Moore or less","authors":"H. Veendrick","doi":"10.1109/TUTCAS.2001.946983","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946983","url":null,"abstract":"Scaling results in: increasing design productivity gap; increasing mask costs; increasing leakage currents; increasing noise while noise margins reduce; increasing test costs; increasing technology costs due to approaching the limits. Design measures to limit leakage and noise and to support testing and debug, require an increasing number of transistors (up to 20-40%) and more complex processes to support embedded options. The move to the next technology will become less and less commercially attractive.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134528244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946962
M. Olivarez
The author discusses the various factors which should be taken into account for the successful design of a system-on-chip (SoC). These factors result from the merging of software and hardware disciplines and include: the use of the SpecC to implement quickly and easily executable specification and behavioral description creation; the productivity gain from working at higher levels of abstraction; IP reuse; architectural exploration performed quickly and products produced to specification; customers should quickly receive functional models and verify end systems, before costly changes are required.
{"title":"Factors for success in SoC design","authors":"M. Olivarez","doi":"10.1109/TUTCAS.2001.946962","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946962","url":null,"abstract":"The author discusses the various factors which should be taken into account for the successful design of a system-on-chip (SoC). These factors result from the merging of software and hardware disciplines and include: the use of the SpecC to implement quickly and easily executable specification and behavioral description creation; the productivity gain from working at higher levels of abstraction; IP reuse; architectural exploration performed quickly and products produced to specification; customers should quickly receive functional models and verify end systems, before costly changes are required.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116860029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1007/978-1-4615-1481-7_2
A. Gerstlauer
{"title":"Modeling and design with SpecC","authors":"A. Gerstlauer","doi":"10.1007/978-1-4615-1481-7_2","DOIUrl":"https://doi.org/10.1007/978-1-4615-1481-7_2","url":null,"abstract":"","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"369 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123406106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946981
H. Veendrick
This article discusses the design of 100 nm CMOS integrated circuits, emphasising the implications for transistors, logic circuits, matching techniques and embedded systems. Included is a discussion of the requirements of high-speed low-power circuits, and the emerging system-on-chip technologies.
{"title":"100 nm CMOS technology. A design perspective","authors":"H. Veendrick","doi":"10.1109/TUTCAS.2001.946981","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946981","url":null,"abstract":"This article discusses the design of 100 nm CMOS integrated circuits, emphasising the implications for transistors, logic circuits, matching techniques and embedded systems. Included is a discussion of the requirements of high-speed low-power circuits, and the emerging system-on-chip technologies.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129787744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946963
D. Gajski
The author discusses the SpecC design environment, considering the following topics: validation levels; abstraction levels; SpecC scope, methodology and refinements; refinement user interface; user feedback; user guided refinement; automatic refinement; validation user interface; modelling, refinement, exploration and synthesis engines.
{"title":"SpecC design environment","authors":"D. Gajski","doi":"10.1109/TUTCAS.2001.946963","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946963","url":null,"abstract":"The author discusses the SpecC design environment, considering the following topics: validation levels; abstraction levels; SpecC scope, methodology and refinements; refinement user interface; user feedback; user guided refinement; automatic refinement; validation user interface; modelling, refinement, exploration and synthesis engines.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946968
J. Khan
The author presents a general discussion on 3G and 4G wireless network architectures. The topics covered include: the basic features of 3G and 4G systems; the migration path from 2G to 3G and 4G; service characteristics; the wireless networking environment; radio transmission issues; the air interface issue; transmission techniques; software radio; and Bluetooth.
{"title":"Introduction to 3G/4G wireless network architectures","authors":"J. Khan","doi":"10.1109/TUTCAS.2001.946968","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946968","url":null,"abstract":"The author presents a general discussion on 3G and 4G wireless network architectures. The topics covered include: the basic features of 3G and 4G systems; the migration path from 2G to 3G and 4G; service characteristics; the wireless networking environment; radio transmission issues; the air interface issue; transmission techniques; software radio; and Bluetooth.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/TUTCAS.2001.946950
K. Roy, R. Krishnammthy
This article discusses high performance and low-power circuits. It covers leakage control (CAD and circuit techniques) including stacked CMOS with gated-Vdd (application: DRI-cache), multiple VT and dynamic VT, circuit techniques (MTCMOS, VTCMOS. DTMOS, SCMOS, etc.) and SOI implementation. Ultra low voltage digital sub-threshold logic in bursty and non-bursty modes for medical applications, and testing of deep sub-micron low voltage CMOS (modified IDDQ testing and cross-talk faults in high speed circuits) are also discussed.
{"title":"Design of low voltage CMOS circuits","authors":"K. Roy, R. Krishnammthy","doi":"10.1109/TUTCAS.2001.946950","DOIUrl":"https://doi.org/10.1109/TUTCAS.2001.946950","url":null,"abstract":"This article discusses high performance and low-power circuits. It covers leakage control (CAD and circuit techniques) including stacked CMOS with gated-Vdd (application: DRI-cache), multiple VT and dynamic VT, circuit techniques (MTCMOS, VTCMOS. DTMOS, SCMOS, etc.) and SOI implementation. Ultra low voltage digital sub-threshold logic in bursty and non-bursty modes for medical applications, and testing of deep sub-micron low voltage CMOS (modified IDDQ testing and cross-talk faults in high speed circuits) are also discussed.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132448988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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