Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682971
Sungjin Lee, Jihong Kim
NAND flash memory is commonly known as a power-efficient storage medium. Because of the increasing complexity of flash-based storage devices, however, it is more difficult to achieve good power-efficiency without considering an energy-efficient storage device design. In this paper, we investigate the potential benefit of dynamic voltage/frequency scaling (DVFS) on the energy-efficiency of flash-based storage devices. We first develop a performance/power model for a flash device by using an FPGA-based flash device platform. We then propose a simple DVFS heuristic algorithm that exploits workload fluctuations of a flash device to achieve a significant reduction in energy consumption without performance degradation. Experimental results show that a flash device with DVFS can reduce energy consumption by up to 20%-30%.
{"title":"Using dynamic voltage scaling for energy-efficient flash-based storage devices","authors":"Sungjin Lee, Jihong Kim","doi":"10.1109/SOCDC.2010.5682971","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682971","url":null,"abstract":"NAND flash memory is commonly known as a power-efficient storage medium. Because of the increasing complexity of flash-based storage devices, however, it is more difficult to achieve good power-efficiency without considering an energy-efficient storage device design. In this paper, we investigate the potential benefit of dynamic voltage/frequency scaling (DVFS) on the energy-efficiency of flash-based storage devices. We first develop a performance/power model for a flash device by using an FPGA-based flash device platform. We then propose a simple DVFS heuristic algorithm that exploits workload fluctuations of a flash device to achieve a significant reduction in energy consumption without performance degradation. Experimental results show that a flash device with DVFS can reduce energy consumption by up to 20%-30%.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124118377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682886
Hyun-Bae Jin, Jong-Seok Han, Jin-Ku Kang
This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel is synthesized using a FPGA board and it operates at 72MHz to support 720Mbps.
{"title":"A 720Mbps fast auxiliary channel design for DisplayPort 1.2","authors":"Hyun-Bae Jin, Jong-Seok Han, Jin-Ku Kang","doi":"10.1109/SOCDC.2010.5682886","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682886","url":null,"abstract":"This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel is synthesized using a FPGA board and it operates at 72MHz to support 720Mbps.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125990090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682962
Y. Lai, Yeong-Kang Lai
In this paper, we propose a reconfigurable IDCT architecture for multi-standard video decoders. It can support different video standards such as MPEG-1/2/4, VC-1 and H.264 AVC. Moreover, the particular part of this architecture does not use any multiplier and ROM circuit; it only needs adders and shifters. In digital circuit, the area of adders and shifters are superior to multipliers and ROM, The reconfigurable IDCT architecture only needs 13 adders in the adder kernel. Finally, we realize this architecture by using 0.18um technology to accomplish the chip design. The experimental result shows the total gate counts only 12.4 K. Moreover, the power consumption is 4.85mW@100MHz. Therefore, the architecture is regular and suitable for multi-standard video decoders.
{"title":"Design and implementation of reconfigurable IDCT architecture for multi-standard video decoders","authors":"Y. Lai, Yeong-Kang Lai","doi":"10.1109/SOCDC.2010.5682962","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682962","url":null,"abstract":"In this paper, we propose a reconfigurable IDCT architecture for multi-standard video decoders. It can support different video standards such as MPEG-1/2/4, VC-1 and H.264 AVC. Moreover, the particular part of this architecture does not use any multiplier and ROM circuit; it only needs adders and shifters. In digital circuit, the area of adders and shifters are superior to multipliers and ROM, The reconfigurable IDCT architecture only needs 13 adders in the adder kernel. Finally, we realize this architecture by using 0.18um technology to accomplish the chip design. The experimental result shows the total gate counts only 12.4 K. Moreover, the power consumption is 4.85mW@100MHz. Therefore, the architecture is regular and suitable for multi-standard video decoders.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133684099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, 3D related applications, including 3D movie and 3DTV, are getting more and more attentions. In order to make the real-time 3D applications feasible, efficient multview video coding (MVC) scheme is desired. However, the system throughput requirement on a high definition (HD) MVC encoder is at least two times higher than the current highest throughput H.264/AVC encoder design. In order to meet the target HD MVC specifications, the system scheduling analysis for the HD MVC encoder is performed in this paper. By the 8-stage MB pipeline system architecture with view-parallel MB-interleaved system scheduling and other in-core computation optimizations, the proposed HD MVC encoder design provides about 339% to 1536% higher system throughput than the previous HD H.264/AVC encoder chips[4][5][6] and therefore the real-time HD MVC encoding can be achieved.
{"title":"System scheduling analysis for high definition multiview video encoder","authors":"Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Tzu-Der Chuang, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/SOCDC.2010.5682965","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682965","url":null,"abstract":"In recent years, 3D related applications, including 3D movie and 3DTV, are getting more and more attentions. In order to make the real-time 3D applications feasible, efficient multview video coding (MVC) scheme is desired. However, the system throughput requirement on a high definition (HD) MVC encoder is at least two times higher than the current highest throughput H.264/AVC encoder design. In order to meet the target HD MVC specifications, the system scheduling analysis for the HD MVC encoder is performed in this paper. By the 8-stage MB pipeline system architecture with view-parallel MB-interleaved system scheduling and other in-core computation optimizations, the proposed HD MVC encoder design provides about 339% to 1536% higher system throughput than the previous HD H.264/AVC encoder chips[4][5][6] and therefore the real-time HD MVC encoding can be achieved.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132710631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682922
M. Shrivastava, H. Gossner, M. Baghini, V. Rao
This paper presents ESD evaluation of various nanoscale drain extended MOS devices. Current and time evolution of current filaments formed under the ESD stress conditions are investigated. A complete picture of device's behavior at the onset of space charge modulation and the evolution of current filamentation is discussed based on Transient Interferometric mapping studies.
{"title":"On the Transient behavior of various drain extended MOS devices under the ESD stress condition","authors":"M. Shrivastava, H. Gossner, M. Baghini, V. Rao","doi":"10.1109/SOCDC.2010.5682922","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682922","url":null,"abstract":"This paper presents ESD evaluation of various nanoscale drain extended MOS devices. Current and time evolution of current filaments formed under the ESD stress conditions are investigated. A complete picture of device's behavior at the onset of space charge modulation and the evolution of current filamentation is discussed based on Transient Interferometric mapping studies.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132408011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682904
Yong-Hee Lee, Chun-Kyun Seok, Bong-Joo Kim, Seung-Bin You, Wang-Seup Yeum, Hojin Park, Byeong-ha Park
A stereo audio DAC with ground-centered class-D headphone drivers is fully integrated in a 45nm CMOS technology. A built-in self-calibration is proposed to minimize DC offset voltage causing static power dissipation. The asymmetric averaging PWM is also applied to improve linearity and suppress switching noise and loss. The measured SNR and DR are 103dB and 98dB, respectively.
{"title":"A self-calibration 103-dB SNR stereo audio DAC with true-GND class-D headphone drivers in 45nm CMOS","authors":"Yong-Hee Lee, Chun-Kyun Seok, Bong-Joo Kim, Seung-Bin You, Wang-Seup Yeum, Hojin Park, Byeong-ha Park","doi":"10.1109/SOCDC.2010.5682904","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682904","url":null,"abstract":"A stereo audio DAC with ground-centered class-D headphone drivers is fully integrated in a 45nm CMOS technology. A built-in self-calibration is proposed to minimize DC offset voltage causing static power dissipation. The asymmetric averaging PWM is also applied to improve linearity and suppress switching noise and loss. The measured SNR and DR are 103dB and 98dB, respectively.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"33 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116594853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682954
Hee Kwan Eun, S. Hwang, M. Sunwoo
This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs such as H.264/AVC and MPEG4. With the proposed specific instructions and hardware accelerators, it can handle the processing requirement of High Definition (HD) video. With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also other fast search algorithms. The gate count is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with sixteen PEGs runs at 160MHz and can handle 1080p@30 frame in realtime.
{"title":"Novel IME instructions and their hardware architecture for ME ASIP","authors":"Hee Kwan Eun, S. Hwang, M. Sunwoo","doi":"10.1109/SOCDC.2010.5682954","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682954","url":null,"abstract":"This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs such as H.264/AVC and MPEG4. With the proposed specific instructions and hardware accelerators, it can handle the processing requirement of High Definition (HD) video. With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also other fast search algorithms. The gate count is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with sixteen PEGs runs at 160MHz and can handle 1080p@30 frame in realtime.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116606035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682908
Jianing Su, Zhenghao Lu, Xiaopeng Yu, Yang Liu
Low-density parity-check (LDPC) codes have recently been considered as a viable candidate for forward error correction in system level hardware-redundant, fault-tolerant logics. An important factor that influences the choosing of a specific FEC technique in a nano-scale system implementation is its real-time performance, namely its computational complexity. In this paper, we propose a set of rules to decide whether a variable node in a LDPC decoder should update its value in subsequent iterations of the decoding process, or be considered as converged. We show that by carefully choosing the convergence rules for variable nodes, significant reduction of decoding complexity can be achieved with endurable performance loss.
{"title":"Reduced-complexity decoding of low-density parity check codes based on adaptive convergence","authors":"Jianing Su, Zhenghao Lu, Xiaopeng Yu, Yang Liu","doi":"10.1109/SOCDC.2010.5682908","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682908","url":null,"abstract":"Low-density parity-check (LDPC) codes have recently been considered as a viable candidate for forward error correction in system level hardware-redundant, fault-tolerant logics. An important factor that influences the choosing of a specific FEC technique in a nano-scale system implementation is its real-time performance, namely its computational complexity. In this paper, we propose a set of rules to decide whether a variable node in a LDPC decoder should update its value in subsequent iterations of the decoding process, or be considered as converged. We show that by carefully choosing the convergence rules for variable nodes, significant reduction of decoding complexity can be achieved with endurable performance loss.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133353717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682977
Jongsu Kim, Yong-Ho Kim, Sang-Kee Lee
This work presents an efficient image fusion of the visible range (VR) and infrared range (IR) images for image enhancement in digital still camera. Fusion is achieved by estimating the weighting parameters which contain the properties of IR image and by combining the VR and IR images using the parameters. Specifically, the weighting parameters are calculated from the estimated illumination and detail components by a weighted low pass filter (WLPF). In addition, for a user preference, we compress dynamic range of the fused image using a retinex technique and adjust contrast/color based on global color distribution. Experiment results show that the proposed scheme produces good outcomes in terms of visual observation and numerical score.
{"title":"Image enhancement through weighting function estimation with infrared image","authors":"Jongsu Kim, Yong-Ho Kim, Sang-Kee Lee","doi":"10.1109/SOCDC.2010.5682977","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682977","url":null,"abstract":"This work presents an efficient image fusion of the visible range (VR) and infrared range (IR) images for image enhancement in digital still camera. Fusion is achieved by estimating the weighting parameters which contain the properties of IR image and by combining the VR and IR images using the parameters. Specifically, the weighting parameters are calculated from the estimated illumination and detail components by a weighted low pass filter (WLPF). In addition, for a user preference, we compress dynamic range of the fused image using a retinex technique and adjust contrast/color based on global color distribution. Experiment results show that the proposed scheme produces good outcomes in terms of visual observation and numerical score.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"4 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133377002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682894
Sudheendra K. Srivathsa, Vikram B. Suresh, Pavan Panchapakeshan, S. Kundu
Increasing on-chip temperature in SoC designs has reinforced the need for Dynamic Thermal Management (DTM). The conventional DTM techniques adopted in microprocessors based on DVFS are not suitable in the context of SoCs as they tend to have multiple voltage and frequency domains. In this paper we propose a reactive and a predictive DTM technique using bus arbitration. Based on the thermal profile the bus grants and hence the bus transactions are controlled. This regulates the data flow which reduces the activity in the functional units. The results show that the on-chip temperature can be maintained 3–5°C below the chip temperature threshold with a worst case performance penalty of 5% and a fast response time of at most 5 clock cycles. The hardware cost of implementing the proposed scheme is 3619.7μm2 in 45nm technology, which is less than 0.06% of the chip area. Apart from its simplicity, lower cost and effectiveness, the solution is non-intrusive on the design and scalable to many cores.
{"title":"Dynamic Thermal Management for system-on-chip using bus arbitration","authors":"Sudheendra K. Srivathsa, Vikram B. Suresh, Pavan Panchapakeshan, S. Kundu","doi":"10.1109/SOCDC.2010.5682894","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682894","url":null,"abstract":"Increasing on-chip temperature in SoC designs has reinforced the need for Dynamic Thermal Management (DTM). The conventional DTM techniques adopted in microprocessors based on DVFS are not suitable in the context of SoCs as they tend to have multiple voltage and frequency domains. In this paper we propose a reactive and a predictive DTM technique using bus arbitration. Based on the thermal profile the bus grants and hence the bus transactions are controlled. This regulates the data flow which reduces the activity in the functional units. The results show that the on-chip temperature can be maintained 3–5°C below the chip temperature threshold with a worst case performance penalty of 5% and a fast response time of at most 5 clock cycles. The hardware cost of implementing the proposed scheme is 3619.7μm2 in 45nm technology, which is less than 0.06% of the chip area. Apart from its simplicity, lower cost and effectiveness, the solution is non-intrusive on the design and scalable to many cores.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117320079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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