Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682926
Yun-Ze Long, C. Johnny, Z. Fan
One-dimensional (1-D) nanomaterials have been extensively explored as the potential building blocks for a variety of electronic and optoelectronic applications due to the continuous increasing demand for miniaturized devices and circuits. In addition, this category of materials possesses a number of unique properties different from bulk materials, such as excellent flexibility, high surface-to-volume ratio, etc., which make them attractive for applications in flexible electronics, sensors, and so on. Nevertheless, controlled and uniform assembly of synthetic 1-D materials with high scalability is still one of the major bottleneck challenges towards the materials and device integration for circuit applications. Here we illustrate the large-scale heterogeneous assembly of highly ordered arrays of organic and inorganic 1-D materials via electrospinning and contact printing methods. These innovative approaches enable the control of the ordering and packing density of 1-D nanomaterials in a significant degree, thus are versatile for the design and implementation of novel electronic circuitry. In particular, we have configured assembled inorganic 1-D materials as a variety of functional electronic and optoelectronic devices, including field-effect transistors, Schottky diodes and photodiodes on both rigid and flexible substrates. Furthermore, we have fabricated and characterized an all-nanowire integrated image sensor. This demonstrates that these functional components can be heterogeneously integrated together to implement nanomaterial-based circuitry.
{"title":"Heterogeneous integration of 1-D nanomaterials for electronic circuitry","authors":"Yun-Ze Long, C. Johnny, Z. Fan","doi":"10.1109/SOCDC.2010.5682926","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682926","url":null,"abstract":"One-dimensional (1-D) nanomaterials have been extensively explored as the potential building blocks for a variety of electronic and optoelectronic applications due to the continuous increasing demand for miniaturized devices and circuits. In addition, this category of materials possesses a number of unique properties different from bulk materials, such as excellent flexibility, high surface-to-volume ratio, etc., which make them attractive for applications in flexible electronics, sensors, and so on. Nevertheless, controlled and uniform assembly of synthetic 1-D materials with high scalability is still one of the major bottleneck challenges towards the materials and device integration for circuit applications. Here we illustrate the large-scale heterogeneous assembly of highly ordered arrays of organic and inorganic 1-D materials via electrospinning and contact printing methods. These innovative approaches enable the control of the ordering and packing density of 1-D nanomaterials in a significant degree, thus are versatile for the design and implementation of novel electronic circuitry. In particular, we have configured assembled inorganic 1-D materials as a variety of functional electronic and optoelectronic devices, including field-effect transistors, Schottky diodes and photodiodes on both rigid and flexible substrates. Furthermore, we have fabricated and characterized an all-nanowire integrated image sensor. This demonstrates that these functional components can be heterogeneously integrated together to implement nanomaterial-based circuitry.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682898
D. Yoo, Suk-ju Kang, Sung Kyu Lee, Young Hwan Kim
In this paper, we propose a motion vector smoothing scheme for motion-compensated frame rate up-conversion. The proposed motion vector smoothing consists of three steps which are outlier detection, outlier correction, and motion vector refinement steps. The proposed method enhances the image quality of the interpolated frame by up to 0.88 dB, and the visual result of the proposed method is better than those of the benchmark methods
{"title":"Motion vector smoothing for motion-compensated frame rate up-conversion","authors":"D. Yoo, Suk-ju Kang, Sung Kyu Lee, Young Hwan Kim","doi":"10.1109/SOCDC.2010.5682898","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682898","url":null,"abstract":"In this paper, we propose a motion vector smoothing scheme for motion-compensated frame rate up-conversion. The proposed motion vector smoothing consists of three steps which are outlier detection, outlier correction, and motion vector refinement steps. The proposed method enhances the image quality of the interpolated frame by up to 0.88 dB, and the visual result of the proposed method is better than those of the benchmark methods","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121951691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682912
Taewan Kim, Sang-Hoon Hong, Yunmo Chung, Inhag Park
In this paper, we propose a framework that allows an efficient way of designing and verifying an SoC. In particular, the proposed SoC design framework, which is based on the OpenRISC platform, utilizes the web environment to reduce the tooling costs while providing similar design times for a small work group. Expensive processing tasks, such as RTL level simulations and cross-compilations, are performed on the remote central server. The server also allows a user to share his or her IP libraries with different clients with user controllable library access permissions. The client is a 15MB program that performs and interfaces to all other tasks required for the SoC design. We demonstrate that the proposed server-client interface performs almost seamlessly.
{"title":"Web-based CAD framework for low cost SoC design prototyping","authors":"Taewan Kim, Sang-Hoon Hong, Yunmo Chung, Inhag Park","doi":"10.1109/SOCDC.2010.5682912","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682912","url":null,"abstract":"In this paper, we propose a framework that allows an efficient way of designing and verifying an SoC. In particular, the proposed SoC design framework, which is based on the OpenRISC platform, utilizes the web environment to reduce the tooling costs while providing similar design times for a small work group. Expensive processing tasks, such as RTL level simulations and cross-compilations, are performed on the remote central server. The server also allows a user to share his or her IP libraries with different clients with user controllable library access permissions. The client is a 15MB program that performs and interfaces to all other tasks required for the SoC design. We demonstrate that the proposed server-client interface performs almost seamlessly.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682953
Sangmin Lee, Taewook Chung, Kilhwan Kim, Chulho Chung, Young-Ho Jung, Jaeseok Kim
We propose a low-complexity design and implementation for baseband modem processors in WiMedia UWB systems. The proposed processor is a MAC-PHY integrated baseband processor that complies with Standard 1.1 (ECMA368/369) and supports full mode up to 480 Mbps. It realizes low power and low area by adopting 4-parallel structures to decrease operating frequency. It was implemented with a CMOS 0.13 μm process, has an operating frequency of 152 MHz, and was synthesized with approx. 1.6M gates.
{"title":"Low-complexity design of PHY/MAC modem processor for WiMedia UWB systems","authors":"Sangmin Lee, Taewook Chung, Kilhwan Kim, Chulho Chung, Young-Ho Jung, Jaeseok Kim","doi":"10.1109/SOCDC.2010.5682953","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682953","url":null,"abstract":"We propose a low-complexity design and implementation for baseband modem processors in WiMedia UWB systems. The proposed processor is a MAC-PHY integrated baseband processor that complies with Standard 1.1 (ECMA368/369) and supports full mode up to 480 Mbps. It realizes low power and low area by adopting 4-parallel structures to decrease operating frequency. It was implemented with a CMOS 0.13 μm process, has an operating frequency of 152 MHz, and was synthesized with approx. 1.6M gates.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125804654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682920
Jaehyun Jeong, T. Iizuka, T. Nakura, M. Ikeda, K. Asada
In this paper, we propose a pulse delay circuit using a differential buffer ring. The proposed circuit keeps an input pulse propagating on the buffer ring without a degradation of pulse width information. The cross-coupled buffer ring with compensating inverters improves the tolerance to the process variation. The proposed circuit has been implemented using 65nm CMOS process, and the simulation results demonstrate that the proposed circuit keeps an input pulse width independent of the process corner conditions, and the measurement results show that the proposed pulse delay circuit using differential buffer ring is more robust to the process variability than conventional buffer ring.
{"title":"A robust pulse delay circuit utilizing a differential buffer ring","authors":"Jaehyun Jeong, T. Iizuka, T. Nakura, M. Ikeda, K. Asada","doi":"10.1109/SOCDC.2010.5682920","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682920","url":null,"abstract":"In this paper, we propose a pulse delay circuit using a differential buffer ring. The proposed circuit keeps an input pulse propagating on the buffer ring without a degradation of pulse width information. The cross-coupled buffer ring with compensating inverters improves the tolerance to the process variation. The proposed circuit has been implemented using 65nm CMOS process, and the simulation results demonstrate that the proposed circuit keeps an input pulse width independent of the process corner conditions, and the measurement results show that the proposed pulse delay circuit using differential buffer ring is more robust to the process variability than conventional buffer ring.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"455 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125847741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682910
Zhenghao Lu, X. Yu, K. Yeo
As the VLSI technology node is getting into the sub-100nm regime, the reliability issues caused by random interferences such as noise, process variations and manufacturing defects are changing the nature of digital computation from deterministic to probabilistic. This paper studies the principle of probabilistic-based Markov Random Field (MRF) design methodology for CMOS static logic gates. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. A Differential Cascode Voltage Switch (DCVS) based MRF logic design method is proposed, which presents substantial noise immunity improvement over the normal MRF logic circuits. The proposed method is validated by simulation in 65nm CMOS technology.
{"title":"Design of probabilistic-based Markov Random Field logic gates in 65nm CMOS technology","authors":"Zhenghao Lu, X. Yu, K. Yeo","doi":"10.1109/SOCDC.2010.5682910","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682910","url":null,"abstract":"As the VLSI technology node is getting into the sub-100nm regime, the reliability issues caused by random interferences such as noise, process variations and manufacturing defects are changing the nature of digital computation from deterministic to probabilistic. This paper studies the principle of probabilistic-based Markov Random Field (MRF) design methodology for CMOS static logic gates. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. A Differential Cascode Voltage Switch (DCVS) based MRF logic design method is proposed, which presents substantial noise immunity improvement over the normal MRF logic circuits. The proposed method is validated by simulation in 65nm CMOS technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128067227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682906
Jingjing Lan, W. Goh, Z. Kong, K. Yeo
Random number generator (RNG) is widely used in cryptographic system as the cryptographic keys generator. These keys are the most important component in the system since the security of the cryptographic system relies entirely on its quality. As digital circuit becomes faster and smaller, some of the desired properties a RNG should have are low-power and good statistical quality. This paper presents a low energy consumption RNG including a serial-to-parallel shift register, a 32-bit register and a pseudo random number generator (PRNG) module. The design can be implemented completely in digital circuit and requires no external components. A prototype was implemented using Chartered Semiconductor 0.18 μm CMOS technology and the power consumption was less than 5 mW. The random sequence produced by the proposed architecture has good statistical properties based on National Institute of Standards and Technology (NIST) statistical test. This RNG can be used to improve the performances such as flexibility and power consumption in communication device and cryptographic application.
{"title":"A random number generator for low power cryptographic application","authors":"Jingjing Lan, W. Goh, Z. Kong, K. Yeo","doi":"10.1109/SOCDC.2010.5682906","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682906","url":null,"abstract":"Random number generator (RNG) is widely used in cryptographic system as the cryptographic keys generator. These keys are the most important component in the system since the security of the cryptographic system relies entirely on its quality. As digital circuit becomes faster and smaller, some of the desired properties a RNG should have are low-power and good statistical quality. This paper presents a low energy consumption RNG including a serial-to-parallel shift register, a 32-bit register and a pseudo random number generator (PRNG) module. The design can be implemented completely in digital circuit and requires no external components. A prototype was implemented using Chartered Semiconductor 0.18 μm CMOS technology and the power consumption was less than 5 mW. The random sequence produced by the proposed architecture has good statistical properties based on National Institute of Standards and Technology (NIST) statistical test. This RNG can be used to improve the performances such as flexibility and power consumption in communication device and cryptographic application.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116848640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682929
Xin Jin, Kun Ba, S. Goto
In this paper, an encoding system is proposed to further reduce the power consumption in parallel video encoding based on difference detection and Hilbert transform based workload estimation (HTWE). The proposed parallel encoding system provides an average of 40% computational complexity reduction for parallel encoding without objective performance loss. For the multi-core platform with frequency and voltage scalability, up to 78% of power reduction can be achieved.
{"title":"Low power parallel encoding system for video surveillance applications","authors":"Xin Jin, Kun Ba, S. Goto","doi":"10.1109/SOCDC.2010.5682929","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682929","url":null,"abstract":"In this paper, an encoding system is proposed to further reduce the power consumption in parallel video encoding based on difference detection and Hilbert transform based workload estimation (HTWE). The proposed parallel encoding system provides an average of 40% computational complexity reduction for parallel encoding without objective performance loss. For the multi-core platform with frequency and voltage scalability, up to 78% of power reduction can be achieved.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125324473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682903
Byoungjoong Kang, Jounghyun Yim, Taewan Kim, Heeseon Shin, Sangsoo Ko, Won Ko, Inhyo Ryu, Sung-Gi Yang, Wooseung Choo, Byeong-ha Park
An Ultra-wideband (UWB) transmitter is proposed that can correct phase errors in quadrature local (LO) signals automatically without help of baseband processor (BBP), operating from 3 to 9 GHz in 65 nm CMOS. The measured tuning range for sideband rejection is 32.7 dB at 7.7 GHz and 13.6 dB at 8.7 GHz. The measured EVM is lower than −20 dB for all supporting bands and TFCs (Time frequency codes) that are prescribed by WiMedia alliance. The power consumption of the transmitter including LO path and PLLs is 210 mW from a 1.2 V supply.
{"title":"An Ultra-wideband transmitter with automatic self-calibration of sideband rejection up to 9 GHz in 65nm CMOS","authors":"Byoungjoong Kang, Jounghyun Yim, Taewan Kim, Heeseon Shin, Sangsoo Ko, Won Ko, Inhyo Ryu, Sung-Gi Yang, Wooseung Choo, Byeong-ha Park","doi":"10.1109/SOCDC.2010.5682903","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682903","url":null,"abstract":"An Ultra-wideband (UWB) transmitter is proposed that can correct phase errors in quadrature local (LO) signals automatically without help of baseband processor (BBP), operating from 3 to 9 GHz in 65 nm CMOS. The measured tuning range for sideband rejection is 32.7 dB at 7.7 GHz and 13.6 dB at 8.7 GHz. The measured EVM is lower than −20 dB for all supporting bands and TFCs (Time frequency codes) that are prescribed by WiMedia alliance. The power consumption of the transmitter including LO path and PLLs is 210 mW from a 1.2 V supply.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133311071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682945
He Tang, H Zhao, Xin Wang, Lin Lin, Q. Fang, Jian Liu, Albert Z. H. Wang, S. Fan, B. Zhao, Zitao Shi, Yuhua Cheng
Analog-to-digital converter (ADC) is a key component electronic system. Flash ADC is widely used in high-speed systems. However, practical flash ADC design is very challenging where experience plays a significant role. ADC design involves in many factors at different levels including architecture, circuit, device and technology. This paper reports a quantitative design methodology for capacitive interpolated flash ADCs, which establishes a design matrix that links ADC chip performance with architecture, block circuit, devices and process parameters. Complex relationship among critical ADC specs, such as, sampling speed, interpolation factors, number of stages, preamplifier bandwidth and transistor parasitic effects, etc, are described. An accurate dynamic power analysis technique is depicted. This flash ADC design method was validated using several designs in 90nm and 130nm CMOS technologies.
{"title":"Capacitive interpolated Flash ADC design technique","authors":"He Tang, H Zhao, Xin Wang, Lin Lin, Q. Fang, Jian Liu, Albert Z. H. Wang, S. Fan, B. Zhao, Zitao Shi, Yuhua Cheng","doi":"10.1109/SOCDC.2010.5682945","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682945","url":null,"abstract":"Analog-to-digital converter (ADC) is a key component electronic system. Flash ADC is widely used in high-speed systems. However, practical flash ADC design is very challenging where experience plays a significant role. ADC design involves in many factors at different levels including architecture, circuit, device and technology. This paper reports a quantitative design methodology for capacitive interpolated flash ADCs, which establishes a design matrix that links ADC chip performance with architecture, block circuit, devices and process parameters. Complex relationship among critical ADC specs, such as, sampling speed, interpolation factors, number of stages, preamplifier bandwidth and transistor parasitic effects, etc, are described. An accurate dynamic power analysis technique is depicted. This flash ADC design method was validated using several designs in 90nm and 130nm CMOS technologies.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"649 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132022527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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