Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682943
Yu-Chi Tsao, K. Choi
Based on the conventional common subexpression elimination (CSE) algorithm, in this paper we propose a new flow, which reduces redundant recursive cycles so that the required total runtime is shorten. The proposed CSE flow can save at most N-3 (N > 3) recursive loops for pattern searching and pattern elimination processes from the conventional CSE algorithm, where N stands for the maximum number of nonzero bits in all possible patterns from all coefficients. The conventional CSE algorithm examines patterns based on N nonzero bits through all the coefficient set. The searching loop is repeated for N, N-1, N-2…2 nonzero bit patterns. In our proposed flow, all possible common patterns with various lengths of nonzero bits are searched at one time. The pattern searching and frequency calculation loops are only performed when the new coefficient set is formed after pattern elimination process of all patterns with maximum frequency, which reduces the redundant recursive cycles of patterns search and frequency calculation from the conventional CSE algorithm. Furthermore, the commensurate amount of adders along the critical path is also achieved by the proposed method for pattern selection.
{"title":"A simplified flow for synthesizing digital FIR filters based on common subexpression elimination","authors":"Yu-Chi Tsao, K. Choi","doi":"10.1109/SOCDC.2010.5682943","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682943","url":null,"abstract":"Based on the conventional common subexpression elimination (CSE) algorithm, in this paper we propose a new flow, which reduces redundant recursive cycles so that the required total runtime is shorten. The proposed CSE flow can save at most N-3 (N > 3) recursive loops for pattern searching and pattern elimination processes from the conventional CSE algorithm, where N stands for the maximum number of nonzero bits in all possible patterns from all coefficients. The conventional CSE algorithm examines patterns based on N nonzero bits through all the coefficient set. The searching loop is repeated for N, N-1, N-2…2 nonzero bit patterns. In our proposed flow, all possible common patterns with various lengths of nonzero bits are searched at one time. The pattern searching and frequency calculation loops are only performed when the new coefficient set is formed after pattern elimination process of all patterns with maximum frequency, which reduces the redundant recursive cycles of patterns search and frequency calculation from the conventional CSE algorithm. Furthermore, the commensurate amount of adders along the critical path is also achieved by the proposed method for pattern selection.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122152543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682928
Giwon Kim, Jungsoo Kim, Tae-Rim Kim, C. Kyung
A mobile wireless camera (MWC) captures scene as it moves around, and then, stores the scene after compression. In this paper, we propose a novel method to extend battery lifetime by intermittently transmitting the compressed data to the base station (BS) through wireless transmission when the distance between MWC and BS is shorter than a given threshold distance; otherwise, compressed data are stored in the internal memory of MWC. We present an analytic method to determine the threshold distance based on the statistics of transmission distance and available memory capacity such that the lifetime of MWC is maximized while preserving all compressed data. Experimental results show that the proposed resource management method offers up to 79.72% (average 33.57%) lifetime improvement compared to the conventional method which transmits encoded data only after memory is full.
{"title":"Lifetime maximization of mobile wireless camera system","authors":"Giwon Kim, Jungsoo Kim, Tae-Rim Kim, C. Kyung","doi":"10.1109/SOCDC.2010.5682928","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682928","url":null,"abstract":"A mobile wireless camera (MWC) captures scene as it moves around, and then, stores the scene after compression. In this paper, we propose a novel method to extend battery lifetime by intermittently transmitting the compressed data to the base station (BS) through wireless transmission when the distance between MWC and BS is shorter than a given threshold distance; otherwise, compressed data are stored in the internal memory of MWC. We present an analytic method to determine the threshold distance based on the statistics of transmission distance and available memory capacity such that the lifetime of MWC is maximized while preserving all compressed data. Experimental results show that the proposed resource management method offers up to 79.72% (average 33.57%) lifetime improvement compared to the conventional method which transmits encoded data only after memory is full.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682876
Jian Chang, K. Man, E. Lim
A general procedure to calculate the stability of the multiport memory cell is proposed. Noise margins of the 4-port and 8-port SRAM cell are studied. A novel 8-port memory cell is proposed to reduce the read access time.
{"title":"Design of a novel 8-port memory cell","authors":"Jian Chang, K. Man, E. Lim","doi":"10.1109/SOCDC.2010.5682876","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682876","url":null,"abstract":"A general procedure to calculate the stability of the multiport memory cell is proposed. Noise margins of the 4-port and 8-port SRAM cell are studied. A novel 8-port memory cell is proposed to reduce the read access time.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"7 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115507439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682917
Debashis Dhar, Young-Ho Kwak, I. Jung, Chulwoo Kim
An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.
{"title":"An all digital time amplifier with interpolation scheme for low gain variation","authors":"Debashis Dhar, Young-Ho Kwak, I. Jung, Chulwoo Kim","doi":"10.1109/SOCDC.2010.5682917","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682917","url":null,"abstract":"An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115739692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reducing standby supply voltage to DRV can sharply decrease leakage power. In this paper, a feedback monitor scheme for standby VDD scaling is proposed. The feedback scheme utilizes the same memory cell to obtain exactly the same performance with SRAM core cells and thus to monitor approximate DRV tail of SRAM array. Based on Monte-Carlo DRV distribution along with its dependencies on body-bias and source-bias voltage, we add controlling options to regulate the DRV of monitor cells and then to approach the worst-case DRV of core cells. The feedback monitor scheme for detecting DRV is implemented with bank-based SRAM design. Simulation results on 55nm CMOS process indicates that for a 512KB SRAM, leakage power savings are achieved in different process corners compared to conventional SRAM structure.
{"title":"Leakage reduction of sub-55nm SRAM based on a feedback monitor scheme for standby voltage scaling","authors":"Chen Wu, Lijun Zhang, Zhenghao Lu, Yaqi Ma, Jianbin Zheng","doi":"10.1109/SOCDC.2010.5682907","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682907","url":null,"abstract":"Reducing standby supply voltage to DRV can sharply decrease leakage power. In this paper, a feedback monitor scheme for standby VDD scaling is proposed. The feedback scheme utilizes the same memory cell to obtain exactly the same performance with SRAM core cells and thus to monitor approximate DRV tail of SRAM array. Based on Monte-Carlo DRV distribution along with its dependencies on body-bias and source-bias voltage, we add controlling options to regulate the DRV of monitor cells and then to approach the worst-case DRV of core cells. The feedback monitor scheme for detecting DRV is implemented with bank-based SRAM design. Simulation results on 55nm CMOS process indicates that for a 512KB SRAM, leakage power savings are achieved in different process corners compared to conventional SRAM structure.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124359372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work describes a 6b 1.4GS/s 65nm CMOS DAC based on a current cell matrix with a 2-D INL bounded switching scheme. The proposed switching scheme reduces current matching errors in both row and column lines with a simple row-column decoder. The proposed area-efficient deglitching circuit minimizes the timing error of each current cell and reduces the required number of transistors by 40% compared to the conventional master-slave deglitching circuits. The prototype DAC with an active die area of 0.11mm2 shows an SFDR of 40.8dB and consumes 11.9mW at 1.0V and 1.4GS/s.
{"title":"A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC with a 2-D INL bounded switching scheme","authors":"Yigi Kwon, Seunghoon Lee, Young-Deuk Jeon, Jong-Kee Kwon","doi":"10.1109/SOCDC.2010.5682937","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682937","url":null,"abstract":"This work describes a 6b 1.4GS/s 65nm CMOS DAC based on a current cell matrix with a 2-D INL bounded switching scheme. The proposed switching scheme reduces current matching errors in both row and column lines with a simple row-column decoder. The proposed area-efficient deglitching circuit minimizes the timing error of each current cell and reduces the required number of transistors by 40% compared to the conventional master-slave deglitching circuits. The prototype DAC with an active die area of 0.11mm2 shows an SFDR of 40.8dB and consumes 11.9mW at 1.0V and 1.4GS/s.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121569163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682884
Youngho Ahn, Wonjin Kim, Ki-Seok Chung, Sea-Ho Kim, Hi-Seok Kim, T. Han
As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program effectively in a distributed fashion on asymmetric memory architecture is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade-off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods.
{"title":"A novel load balancing method for multi-core with non-uniform memory architecture","authors":"Youngho Ahn, Wonjin Kim, Ki-Seok Chung, Sea-Ho Kim, Hi-Seok Kim, T. Han","doi":"10.1109/SOCDC.2010.5682884","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682884","url":null,"abstract":"As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program effectively in a distributed fashion on asymmetric memory architecture is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade-off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116835507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A buck converter to control the supply voltage and a Power Amplifier (PA) for the Wireless Local Area Network (WLAN) application are presented in this paper. By using the buck converter the efficiency improvement in low power mode of the PA can be achieved. The buck converter is implemented in TSMC 0.35 μm CMOS process. The maximum efficiency of 98% is shown at 3.4 V of the output voltage of the buck converter, and the efficiency of 90% is achieved for 2 V with the load resistance of 12 Ω. The maximum ripple across the overall output voltage range is less than 12 mV. The WLAN PA is implemented in WIN 2 μm InGaP HBT process. The maximum linear output power of 22 dBm is obtained for the Error Vector Magnitude (EVM) of 4% with 64QAM OFDM signal at 2.5 GHz. The Power Added Efficiency (PAE) is 20% at 22 dBm.
{"title":"DC-DC converter for WLAN power amplifier","authors":"Trung-Sinh Dang, Anh-Dung Tran, Minwoo Cho, Sang‐Woong Yoon","doi":"10.1109/SOCDC.2010.5682893","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682893","url":null,"abstract":"A buck converter to control the supply voltage and a Power Amplifier (PA) for the Wireless Local Area Network (WLAN) application are presented in this paper. By using the buck converter the efficiency improvement in low power mode of the PA can be achieved. The buck converter is implemented in TSMC 0.35 μm CMOS process. The maximum efficiency of 98% is shown at 3.4 V of the output voltage of the buck converter, and the efficiency of 90% is achieved for 2 V with the load resistance of 12 Ω. The maximum ripple across the overall output voltage range is less than 12 mV. The WLAN PA is implemented in WIN 2 μm InGaP HBT process. The maximum linear output power of 22 dBm is obtained for the Error Vector Magnitude (EVM) of 4% with 64QAM OFDM signal at 2.5 GHz. The Power Added Efficiency (PAE) is 20% at 22 dBm.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123135566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682881
Soojin Kim, Kyeongsoon Cho
This paper describes the architecture and design of 2.5Gb/s non-PLL-type all-digital clock recovery circuit. The proposed circuit is non-PLL-type and designed in fully digital style to provide faster acquisition time and better scalability and portability. Output jitter would not be accumulated since the proposed circuit recovers output clock for every transition of input data. Furthermore, it can recover the final output clock from potential candidate clock signals without any special elaborated techniques and the acquisition time is fast enough. The proposed circuit is designed using 130nm, 1.2V CMOS technology and simulated for 27 −1 pseudo random bit sequence data at 2.5Gb/s with HSpice circuit simulator. The phase shifts in recovered clock for input data skew is within ±40ps, and peak-to-peak jitter and RMS jitter are 49ps and 4.5ps, respectively.
{"title":"Design of 2.5Gb/s non-PLL-type all-digital clock recovery circuit","authors":"Soojin Kim, Kyeongsoon Cho","doi":"10.1109/SOCDC.2010.5682881","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682881","url":null,"abstract":"This paper describes the architecture and design of 2.5Gb/s non-PLL-type all-digital clock recovery circuit. The proposed circuit is non-PLL-type and designed in fully digital style to provide faster acquisition time and better scalability and portability. Output jitter would not be accumulated since the proposed circuit recovers output clock for every transition of input data. Furthermore, it can recover the final output clock from potential candidate clock signals without any special elaborated techniques and the acquisition time is fast enough. The proposed circuit is designed using 130nm, 1.2V CMOS technology and simulated for 27 −1 pseudo random bit sequence data at 2.5Gb/s with HSpice circuit simulator. The phase shifts in recovered clock for input data skew is within ±40ps, and peak-to-peak jitter and RMS jitter are 49ps and 4.5ps, respectively.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122557586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682970
Y. Takeuchi, K. Sakanushi, M. Imai
This paper introduces a generation method of Application-domain Specific Instruction-set Processors (ASIP) and shows an design example. ASIP is a processor which has some extended instructions specific to application domain. First, advantage of ASIC is explained. Then, some processor generation approaches explained, and an ASIP development environment called ASIP Meister is introduced. Finally, design example shows some effectiveness of ASIP.
{"title":"Generation of application-domain Specific Instruction-set Processors","authors":"Y. Takeuchi, K. Sakanushi, M. Imai","doi":"10.1109/SOCDC.2010.5682970","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682970","url":null,"abstract":"This paper introduces a generation method of Application-domain Specific Instruction-set Processors (ASIP) and shows an design example. ASIP is a processor which has some extended instructions specific to application domain. First, advantage of ASIC is explained. Then, some processor generation approaches explained, and an ASIP development environment called ASIP Meister is introduced. Finally, design example shows some effectiveness of ASIP.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115750804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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