Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682939
S. Raghunath, Byeong Kil Lee
In today's information technology trends, all kinds of digital and multimedia technologies are converging into single mobile internet devices (MID). This digital convergence trend is being accelerated by deep sub-micron technology and the concept of system-on-chip design. In SoC design, reconfigurable soft-IPs are widely used than the hard-IPs to obtain more optimized design toward a system or platform. To decide optimized configuration of the soft-IPs, early-stage design exploration is required. Also, choosing appropriate workloads and workload reduction methodology are very crucial for accurate and fast estimation in design exploration. In this paper, we propose a methodology to reduce the amount of workloads used for early-stage power estimation. We explore two scenarios in our analysis for effective workload reduction: (i) instruction-distribution-based workload reduction; (ii) demand-based workload reduction. Based on our experiment, power estimation with the reduced-workload shows more accurate and faster than with conventional reduction method (Simpoint). We conclude that workload reduction technologies which are customized for demanded performance metric are highly required for effective and faster performance evaluation at each design stage — especially in SoC design.
{"title":"Effective workload reduction for early-stage power estimation","authors":"S. Raghunath, Byeong Kil Lee","doi":"10.1109/SOCDC.2010.5682939","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682939","url":null,"abstract":"In today's information technology trends, all kinds of digital and multimedia technologies are converging into single mobile internet devices (MID). This digital convergence trend is being accelerated by deep sub-micron technology and the concept of system-on-chip design. In SoC design, reconfigurable soft-IPs are widely used than the hard-IPs to obtain more optimized design toward a system or platform. To decide optimized configuration of the soft-IPs, early-stage design exploration is required. Also, choosing appropriate workloads and workload reduction methodology are very crucial for accurate and fast estimation in design exploration. In this paper, we propose a methodology to reduce the amount of workloads used for early-stage power estimation. We explore two scenarios in our analysis for effective workload reduction: (i) instruction-distribution-based workload reduction; (ii) demand-based workload reduction. Based on our experiment, power estimation with the reduced-workload shows more accurate and faster than with conventional reduction method (Simpoint). We conclude that workload reduction technologies which are customized for demanded performance metric are highly required for effective and faster performance evaluation at each design stage — especially in SoC design.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682883
M. Rasoulzadeh, M. Ghaznavi-Ghoushchi
The operational amplifiers (Op-Amps) are the essential building blocks of many electronic circuits with wide applications. However, the operational amplifiers suffer from oscillation on their output (especially when are used in feedback loops) which leads to instability. This problem could be seen in step response of operational amplifiers as percent overshoot (P.O.). In this paper, a novel Posicast-based method is proposed to cancel the step response oscillation of operational amplifiers which experience pulse like inputs and therefore improve their settling time (Ts). The proposed method is applied on five different operational amplifiers (two-stage and three-stage) topologies and the results are simulated with HSPICE. The simulation results show a significant reduction in overshoot (96% average) and improvement in settling time (81% average) of the operational amplifiers.
{"title":"A novel method for oscillation canceling of CMOS opeational amplifires using Posicast","authors":"M. Rasoulzadeh, M. Ghaznavi-Ghoushchi","doi":"10.1109/SOCDC.2010.5682883","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682883","url":null,"abstract":"The operational amplifiers (Op-Amps) are the essential building blocks of many electronic circuits with wide applications. However, the operational amplifiers suffer from oscillation on their output (especially when are used in feedback loops) which leads to instability. This problem could be seen in step response of operational amplifiers as percent overshoot (P.O.). In this paper, a novel Posicast-based method is proposed to cancel the step response oscillation of operational amplifiers which experience pulse like inputs and therefore improve their settling time (Ts). The proposed method is applied on five different operational amplifiers (two-stage and three-stage) topologies and the results are simulated with HSPICE. The simulation results show a significant reduction in overshoot (96% average) and improvement in settling time (81% average) of the operational amplifiers.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114828440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682882
Kangyeop Choo, Woojae Lee, Seonghwan Cho
This paper presents a PVT tolerant BPF for bio-medical applications, which operate at very low frequencies. As the BPF used in this area has a very large time constant, the cut-off frequency of the BPF is very susceptible to PVT variations. In order to avoid such variation, the proposed architecture uses a replica LPF and negative feedback to enable a PVT invariant time constant. Simulation result shows that the variation of the frequency response of the proposed BPF remains under 1% with the following PVT variations: process (ss, tt, ff), voltage (1.1V to 2.0V) and temperature (0°C to 100°C). The circuit has been implemented using 0.13μm CMOS technology with a supply voltage of 1.2V and 3.3V and it consumes 200nW.
{"title":"A PVT tolerant BPF using turn-off MOSFET for bio applications in 0.13μm CMOS","authors":"Kangyeop Choo, Woojae Lee, Seonghwan Cho","doi":"10.1109/SOCDC.2010.5682882","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682882","url":null,"abstract":"This paper presents a PVT tolerant BPF for bio-medical applications, which operate at very low frequencies. As the BPF used in this area has a very large time constant, the cut-off frequency of the BPF is very susceptible to PVT variations. In order to avoid such variation, the proposed architecture uses a replica LPF and negative feedback to enable a PVT invariant time constant. Simulation result shows that the variation of the frequency response of the proposed BPF remains under 1% with the following PVT variations: process (ss, tt, ff), voltage (1.1V to 2.0V) and temperature (0°C to 100°C). The circuit has been implemented using 0.13μm CMOS technology with a supply voltage of 1.2V and 3.3V and it consumes 200nW.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122601589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682942
Ingoo Heo, Sanghyun Park, Jinyong Lee, Y. Paek
For high video quality and high compression rate, H.264, the latest standard of video compression, is widely used. Motion estimation is well known application that reduces temporal redundancy and the most computation-intensive part of the standard. In order to improve the performance of motion estimation, various approaches were suggested, such as novel motion estimation algorithms, Application Specific Integrated Circuit(ASIC)s and Application Specific Instruction set Processor(ASIP)s. Among them, ASIP approach became popular because it can narrow the gap between ASICs and General Purpose programmable Processors (GPP) in terms of performance, power, cost and flexibility. ASIP gains flexibility since it is based on programmable processor, and reasonable performance by adding application specific instructions. In this paper, we introduce an ASIP for motion estimation inherited from our previous ASIP for H.264 intra prediction [5]. The proposed ASIP design shows sufficient throughput for QCIF format using Three Step Search(TSS) algorithm and little area increase about 11% compared to [5] while H.264 intra prediction is still enabled.
{"title":"An ASIP approach for motion estimation reusing resources for H.264 intra prediction","authors":"Ingoo Heo, Sanghyun Park, Jinyong Lee, Y. Paek","doi":"10.1109/SOCDC.2010.5682942","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682942","url":null,"abstract":"For high video quality and high compression rate, H.264, the latest standard of video compression, is widely used. Motion estimation is well known application that reduces temporal redundancy and the most computation-intensive part of the standard. In order to improve the performance of motion estimation, various approaches were suggested, such as novel motion estimation algorithms, Application Specific Integrated Circuit(ASIC)s and Application Specific Instruction set Processor(ASIP)s. Among them, ASIP approach became popular because it can narrow the gap between ASICs and General Purpose programmable Processors (GPP) in terms of performance, power, cost and flexibility. ASIP gains flexibility since it is based on programmable processor, and reasonable performance by adding application specific instructions. In this paper, we introduce an ASIP for motion estimation inherited from our previous ASIP for H.264 intra prediction [5]. The proposed ASIP design shows sufficient throughput for QCIF format using Three Step Search(TSS) algorithm and little area increase about 11% compared to [5] while H.264 intra prediction is still enabled.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129651775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682984
R. Secareanu, O. Hartin, J. Feddeler, R. Moseley, J. Shepherd, B. Vrignon, Jian Yang, Qiang Li, Hongwei Zhao, Waley Li, Linpeng Wei, E. Salman, Richard Wang, D. Blomberg, P. Parris
External stresses, such as those generated due to Electrical Fast Transient (EFT) events, generate over-voltages which may result in reliability failures at the IClevel either in the form of recoverable or permanent damage of the IC. In the present paper, the relationship between the technology characteristics within a design framework and the permanent failures that such an EFT event can produce are discussed. Solutions to minimize the impact of such EFT events are presented.
{"title":"Impact of low-doped substrate areas on the reliability of circuits subject to EFT events","authors":"R. Secareanu, O. Hartin, J. Feddeler, R. Moseley, J. Shepherd, B. Vrignon, Jian Yang, Qiang Li, Hongwei Zhao, Waley Li, Linpeng Wei, E. Salman, Richard Wang, D. Blomberg, P. Parris","doi":"10.1109/SOCDC.2010.5682984","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682984","url":null,"abstract":"External stresses, such as those generated due to Electrical Fast Transient (EFT) events, generate over-voltages which may result in reliability failures at the IClevel either in the form of recoverable or permanent damage of the IC. In the present paper, the relationship between the technology characteristics within a design framework and the permanent failures that such an EFT event can produce are discussed. Solutions to minimize the impact of such EFT events are presented.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682897
H. Roh, J. Roh, Q. Z. D. Duanquanzhen
A 0.6-V, 8-μW bandgap reference without BJTs is realized in the standard CMOS 0.13μm technology. All MOS transistors bandgap reference circuit with very low supply voltage 0.6V is designed. The chopper stabilization technique is used to improve the accuracy of the bandgap reference voltage. The measurement results have confirmed that the chopper stabilization technique reduces bandgap voltage error from 100mV to 30mV comparing to the one without chopper stabilization technique.
{"title":"All MOS transistors bandgap reference using chopper stabilization technique","authors":"H. Roh, J. Roh, Q. Z. D. Duanquanzhen","doi":"10.1109/SOCDC.2010.5682897","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682897","url":null,"abstract":"A 0.6-V, 8-μW bandgap reference without BJTs is realized in the standard CMOS 0.13μm technology. All MOS transistors bandgap reference circuit with very low supply voltage 0.6V is designed. The chopper stabilization technique is used to improve the accuracy of the bandgap reference voltage. The measurement results have confirmed that the chopper stabilization technique reduces bandgap voltage error from 100mV to 30mV comparing to the one without chopper stabilization technique.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130718336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682955
Yimeng Zhang, Leona Okamura, Nan Wang, T. Yoshihara
In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.
{"title":"A 160MHz 4-bit pipeline multiplier using charge recovery logic technology","authors":"Yimeng Zhang, Leona Okamura, Nan Wang, T. Yoshihara","doi":"10.1109/SOCDC.2010.5682955","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682955","url":null,"abstract":"In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133224386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682976
Seong-Wha Hong, HongJin Kim, Kangyoon Lee, Jeongin Cheon, Dae-Hoon Han
This paper presents a novel dead-time generation method of the clock generator for the resonant converter system. The new dead-time generator, which is incorporated to implement the accurate dead-time independent of the output frequency of the clock generator, is designed to prevent cross conduction problem for half-bridge type resonant converter circuit. Dead-time variation range is from 50 ns to 2 μs.
{"title":"A novel dead-time generation method of clock generator for resonant power transfer system","authors":"Seong-Wha Hong, HongJin Kim, Kangyoon Lee, Jeongin Cheon, Dae-Hoon Han","doi":"10.1109/SOCDC.2010.5682976","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682976","url":null,"abstract":"This paper presents a novel dead-time generation method of the clock generator for the resonant converter system. The new dead-time generator, which is incorporated to implement the accurate dead-time independent of the output frequency of the clock generator, is designed to prevent cross conduction problem for half-bridge type resonant converter circuit. Dead-time variation range is from 50 ns to 2 μs.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114447560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682956
Chang-Ha Jeon, Jae-Kyung Lee, Dong-Hyun Seo, Jeong-Hun Kim, Jin-Gyun Chung, Chul-Dong Lee
Interpolation filters are widely used in many communication and multimedia applications. Recently, FIR interpolation method using supplementary filters was proposed to improve the performances of polynomial interpolation methods. In this paper, we propose a weighted interpolation method using supplementary filter which can be efficiently applied to XRF spectroscopy. It is shown that the proposed method achieves more accurate results compared with conventional interpolation filters with reduced hardware cost. The proposed system is implemented and tested using Altera Excalibur FPGA in an SoC design kit.
{"title":"Design of weighted interpolation circuit using supplementary filter","authors":"Chang-Ha Jeon, Jae-Kyung Lee, Dong-Hyun Seo, Jeong-Hun Kim, Jin-Gyun Chung, Chul-Dong Lee","doi":"10.1109/SOCDC.2010.5682956","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682956","url":null,"abstract":"Interpolation filters are widely used in many communication and multimedia applications. Recently, FIR interpolation method using supplementary filters was proposed to improve the performances of polynomial interpolation methods. In this paper, we propose a weighted interpolation method using supplementary filter which can be efficiently applied to XRF spectroscopy. It is shown that the proposed method achieves more accurate results compared with conventional interpolation filters with reduced hardware cost. The proposed system is implemented and tested using Altera Excalibur FPGA in an SoC design kit.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682974
K. Park, Joohwan Lee, Sungho Kang
Programmable memory built-in self-tests (BIST) have increased test flexibility but result in large area overhead. In this research, a new finite state machine (FSM) based programmable memory BIST that can select march algorithms was proposed in order to overcome this problem. The proposed BIST efficiently generates various march algorithms utilizing an extended address counter while also taking into consideration the characteristics of the march algorithms. The experimental results of this research indicated that the proposed BIST improved test flexibility and resulted in a smaller area overhead, as compared to the results of previous studies.
{"title":"An area efficient programmable built-in self-test for embedded memories using an extended address counter","authors":"K. Park, Joohwan Lee, Sungho Kang","doi":"10.1109/SOCDC.2010.5682974","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682974","url":null,"abstract":"Programmable memory built-in self-tests (BIST) have increased test flexibility but result in large area overhead. In this research, a new finite state machine (FSM) based programmable memory BIST that can select march algorithms was proposed in order to overcome this problem. The proposed BIST efficiently generates various march algorithms utilizing an extended address counter while also taking into consideration the characteristics of the march algorithms. The experimental results of this research indicated that the proposed BIST improved test flexibility and resulted in a smaller area overhead, as compared to the results of previous studies.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122055033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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