Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00031
V. Radulescu, S. Andrei, A. Cheng
The concept of graceful degradation in mixed-criticality real-time systems is still struggling to reach a widely accepted, global view. Numerous results have emerged in this field during the last years, but there is still a lot of work to do. This paper comes with an addition to a recent work [2] in the field of scheduling in semi-clairvoyant systems: it introduces a new criterion for determining which low criticality jobs should be switched upon a system criticality mode transition.
{"title":"Work-in-Progress Abstract: A New Criterion for Job Switching in Semi-Clairvoyant Systems","authors":"V. Radulescu, S. Andrei, A. Cheng","doi":"10.1109/RTCSA52859.2021.00031","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00031","url":null,"abstract":"The concept of graceful degradation in mixed-criticality real-time systems is still struggling to reach a widely accepted, global view. Numerous results have emerged in this field during the last years, but there is still a lot of work to do. This paper comes with an addition to a recent work [2] in the field of scheduling in semi-clairvoyant systems: it introduces a new criterion for determining which low criticality jobs should be switched upon a system criticality mode transition.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"1 1","pages":"198-200"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88947540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00029
Jung-Hoon Kim
A flash translation layer (FTL) of NAND flash-based storage occasionally conducts a garbage collection causing long-wait situations to a host system. To avert that long latency, the host system using a black-box model has chased the storage performance. On the other hand, other storage systems have required expensive storage hardware or depended on idle timing. This paper proposes an FTL-aware host system extracting the FTL metadata from the storage during runtime to overcome these constraints. Furthermore, this novel host system predicts the garbage collection and directs the storage to lower the long latency in advance. The experiment results show the alleviation of the long latency against the legacy host system.
{"title":"An FTL-Aware Host System Alleviating Severe Long Latency of NAND Flash-based Storage","authors":"Jung-Hoon Kim","doi":"10.1109/RTCSA52859.2021.00029","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00029","url":null,"abstract":"A flash translation layer (FTL) of NAND flash-based storage occasionally conducts a garbage collection causing long-wait situations to a host system. To avert that long latency, the host system using a black-box model has chased the storage performance. On the other hand, other storage systems have required expensive storage hardware or depended on idle timing. This paper proposes an FTL-aware host system extracting the FTL metadata from the storage during runtime to overcome these constraints. Furthermore, this novel host system predicts the garbage collection and directs the storage to lower the long latency in advance. The experiment results show the alleviation of the long latency against the legacy host system.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"16 1","pages":"189-194"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74522478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00024
Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia, F. Brandner, M. Jan
Correctness is an important concern during the development of real-time systems. In addition to the functional correctness, the timing behavior is often formally verified in order to ensure that correct results are delivered in-time for all possible execution conditions. The timing behavior of real-time software is thus often validated through a rigorous timing analysis that aims at determining the worst-case execution time.Timing anomalies present a major obstacle during the validation of timing properties on modern computer platforms. Out-of-order execution and concurrent accesses to shared resources may sometimes lead to – at first sight – surprising timing behavior. Several (semi-)formal definitions have been proposed in the literature in order to capture such situations. However, as we present in this work, none of the existing definitions appears to be precise enough to be systematically used for detecting timing anomalies in modern processors with out-of-order execution.
{"title":"Is This Still Normal? Putting Definitions of Timing Anomalies to the Test","authors":"Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia, F. Brandner, M. Jan","doi":"10.1109/RTCSA52859.2021.00024","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00024","url":null,"abstract":"Correctness is an important concern during the development of real-time systems. In addition to the functional correctness, the timing behavior is often formally verified in order to ensure that correct results are delivered in-time for all possible execution conditions. The timing behavior of real-time software is thus often validated through a rigorous timing analysis that aims at determining the worst-case execution time.Timing anomalies present a major obstacle during the validation of timing properties on modern computer platforms. Out-of-order execution and concurrent accesses to shared resources may sometimes lead to – at first sight – surprising timing behavior. Several (semi-)formal definitions have been proposed in the literature in order to capture such situations. However, as we present in this work, none of the existing definitions appears to be precise enough to be systematically used for detecting timing anomalies in modern processors with out-of-order execution.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"1 1","pages":"139-148"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76516261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00013
Keisuke Nishimura, T. Ishikawa, Hiroshi Sasaki, S. Kato
The problem of real-time scheduling based on the Directed Acyclic Graph (DAG) task model has been extensively studied in the literature. Most of the studies are aimed at the development of efficient scheduling algorithms to reduce deadline misses and/or improve schedulability bounds on the given task system. In order to guarantee real-time performance of the DAG task model in practice, the latency imposed on the communication between the DAG nodes must be systematically taken into account. This paper aims at demystifying the latency of the Robot Operating System (ROS) as a practical DAG task model, which leverages the publish/subscribe mechanism to send and receive data between the nodes. To this end we present the ROS-Aware Publish/Subscribe Latency Evaluation Tool (RAPLET) which is designed to measure and visualize the details of the publish/subscribe latency in ROS. RAPLET consists of (i) the LD PRELOAD scheme that inserts function hooks in user-land and (ii) the extended Berkeley Packet Filter (eBPF) scheme that monitors the run-queue level and the network states in kernel-land. The performance analysis on ROS applications, including a real-world autonomous driving software, is performed using RAPLET to demonstrate that the publish/subscribe latency imposed on inter-node communication can be demystified and reasoned with respect to system issues including the message size and network bandwidth consumption.
{"title":"RAPLET: Demystifying Publish/Subscribe Latency for ROS Applications","authors":"Keisuke Nishimura, T. Ishikawa, Hiroshi Sasaki, S. Kato","doi":"10.1109/RTCSA52859.2021.00013","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00013","url":null,"abstract":"The problem of real-time scheduling based on the Directed Acyclic Graph (DAG) task model has been extensively studied in the literature. Most of the studies are aimed at the development of efficient scheduling algorithms to reduce deadline misses and/or improve schedulability bounds on the given task system. In order to guarantee real-time performance of the DAG task model in practice, the latency imposed on the communication between the DAG nodes must be systematically taken into account. This paper aims at demystifying the latency of the Robot Operating System (ROS) as a practical DAG task model, which leverages the publish/subscribe mechanism to send and receive data between the nodes. To this end we present the ROS-Aware Publish/Subscribe Latency Evaluation Tool (RAPLET) which is designed to measure and visualize the details of the publish/subscribe latency in ROS. RAPLET consists of (i) the LD PRELOAD scheme that inserts function hooks in user-land and (ii) the extended Berkeley Packet Filter (eBPF) scheme that monitors the run-queue level and the network states in kernel-land. The performance analysis on ROS applications, including a real-world autonomous driving software, is performed using RAPLET to demonstrate that the publish/subscribe latency imposed on inter-node communication can be demystified and reasoned with respect to system issues including the message size and network bandwidth consumption.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"10 1","pages":"41-50"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80061808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00021
N. Aswathy, H. Kapoor, A. Sarkar
Phase Change Memory (PCM) has emerged as a viable alternative to traditional DRAM memories especially in real-time embedded systems, due to their higher density and lower leakage power dissipation. However, PCM comes with its own drawbacks. Although, the performances of DRAM and PCM are comparable for memory reads, PCM is about three times slower in terms of write latency, and suffers from significantly lower write endurance. The high write latency of PCM may be detrimental to delivered QoS and may lead to deadline misses in real-time systems. To circumvent the problem, this paper proposes a novel memory scheduling scheme which employs separate write request buffer in order to prioritize reads over writes. The read requests are scheduled using an urgency based scheduler where urgency depends on allowable response times of tasks. The write requests are serviced when there are no pending reads using a similar urgency based scheduler as used for read requests. Experimental evaluation using standard benchmarks reveal that the proposed scheme is able to achieve better normalized QoS compared to existing scheduling techniques for PCM and comparable access latencies with respect to DRAM.
{"title":"A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems","authors":"N. Aswathy, H. Kapoor, A. Sarkar","doi":"10.1109/RTCSA52859.2021.00021","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00021","url":null,"abstract":"Phase Change Memory (PCM) has emerged as a viable alternative to traditional DRAM memories especially in real-time embedded systems, due to their higher density and lower leakage power dissipation. However, PCM comes with its own drawbacks. Although, the performances of DRAM and PCM are comparable for memory reads, PCM is about three times slower in terms of write latency, and suffers from significantly lower write endurance. The high write latency of PCM may be detrimental to delivered QoS and may lead to deadline misses in real-time systems. To circumvent the problem, this paper proposes a novel memory scheduling scheme which employs separate write request buffer in order to prioritize reads over writes. The read requests are scheduled using an urgency based scheduler where urgency depends on allowable response times of tasks. The write requests are serviced when there are no pending reads using a similar urgency based scheduler as used for read requests. Experimental evaluation using standard benchmarks reveal that the proposed scheme is able to achieve better normalized QoS compared to existing scheduling techniques for PCM and comparable access latencies with respect to DRAM.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"37 1","pages":"109-118"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89166658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00010
S. Roy, A. Sarkar, Rahul Gangopadhyay
Cyber-Physical Systems, including those in the automotive domain, are often designed by assigning to each task an appropriate criticality-based reward value which is acquired by the system on its successful execution. Additionally, each task may have multiple implementations designated as service-levels, with higher service-levels producing more accurate results and contributing to higher rewards for the system. This work proposes strategies for co-scheduling a set of periodic tasks with multiple service-levels, on homogeneous processors and system buses. The problem is modeled as a Multi-dimensional Multiple-Choice Knapsack formulation (MMCKP) with the objective of maximizing overall system level rewards. A Dynamic Programming (DP) solution is proposed to solve the MMCKP. It was observed that although the DP based solution produces optimal results, its complexity is highly sensitive to the number of tasks, processors, buses as well as to the number of task service-levels, which severely restricts scalability of the strategy. Therefore, we have also proposed a fast yet efficient heuristic algorithm called Accurate Low Overhead Level Allocator (ALOLA), which attempts to achieve the same objective. Our simulation based experimental evaluation shows that even on moderately large systems consisting of 90 tasks with 5 service-levels each, 16 processors and 4 buses, while MMCKP incurs a run-time of more than 1 hour 20 minutes and approximately 68 GB main memory, ALOLA takes only about 196 $mu s$ (speedup of the order of 106 times) and less than 1 MB of memory. Moreover, while being fast, ALOLA is also efficient being able to control performance degradations to at most 13% compared to the optimal results produced by MMCKP. We use an automated flight control system employed in modern avionic systems, a real-world application to illustrate the general applicability of our proposed scheme.
{"title":"Processor and Bus Co-scheduling Strategies for Real-time Tasks with Multiple Service-levels","authors":"S. Roy, A. Sarkar, Rahul Gangopadhyay","doi":"10.1109/RTCSA52859.2021.00010","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00010","url":null,"abstract":"Cyber-Physical Systems, including those in the automotive domain, are often designed by assigning to each task an appropriate criticality-based reward value which is acquired by the system on its successful execution. Additionally, each task may have multiple implementations designated as service-levels, with higher service-levels producing more accurate results and contributing to higher rewards for the system. This work proposes strategies for co-scheduling a set of periodic tasks with multiple service-levels, on homogeneous processors and system buses. The problem is modeled as a Multi-dimensional Multiple-Choice Knapsack formulation (MMCKP) with the objective of maximizing overall system level rewards. A Dynamic Programming (DP) solution is proposed to solve the MMCKP. It was observed that although the DP based solution produces optimal results, its complexity is highly sensitive to the number of tasks, processors, buses as well as to the number of task service-levels, which severely restricts scalability of the strategy. Therefore, we have also proposed a fast yet efficient heuristic algorithm called Accurate Low Overhead Level Allocator (ALOLA), which attempts to achieve the same objective. Our simulation based experimental evaluation shows that even on moderately large systems consisting of 90 tasks with 5 service-levels each, 16 processors and 4 buses, while MMCKP incurs a run-time of more than 1 hour 20 minutes and approximately 68 GB main memory, ALOLA takes only about 196 $mu s$ (speedup of the order of 106 times) and less than 1 MB of memory. Moreover, while being fast, ALOLA is also efficient being able to control performance degradations to at most 13% compared to the optimal results produced by MMCKP. We use an automated flight control system employed in modern avionic systems, a real-world application to illustrate the general applicability of our proposed scheme.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"46 1","pages":"21-30"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75347546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-01DOI: 10.4018/ijertcs.2021070104
A. M. H. Sad, Md Mashrur Sakib Choyon, Abu Hasnat Md Rhydwan, Kawshik Shikder, C. A. Hossain
In recent years, the demand of kiosk devices has increased significantly for relaying information in organizations, institutions, or any other service centers. They have become a better alternative for traditional human assistance or reception desks. However, there are no dynamic operating systems or user interfaces available for kiosk devices. This paper represents a development of an operating system for kiosk devices called ‘Nekray', which was built on Linux Kernel environment. It was designed to be dynamic, fast, user-friendly, and user interactive. The developed operating system avails the option to change the data of its features as per requirement. It also supports plug and play feature and can be installed in any low-cost hardware board. Furthermore, built-in AI is also a part of the developed system that performs its features through image processing. The system maintains the privacy and interactive transition of data to its users on kiosk devices.
{"title":"Nekray","authors":"A. M. H. Sad, Md Mashrur Sakib Choyon, Abu Hasnat Md Rhydwan, Kawshik Shikder, C. A. Hossain","doi":"10.4018/ijertcs.2021070104","DOIUrl":"https://doi.org/10.4018/ijertcs.2021070104","url":null,"abstract":"In recent years, the demand of kiosk devices has increased significantly for relaying information in organizations, institutions, or any other service centers. They have become a better alternative for traditional human assistance or reception desks. However, there are no dynamic operating systems or user interfaces available for kiosk devices. This paper represents a development of an operating system for kiosk devices called ‘Nekray', which was built on Linux Kernel environment. It was designed to be dynamic, fast, user-friendly, and user interactive. The developed operating system avails the option to change the data of its features as per requirement. It also supports plug and play feature and can be installed in any low-cost hardware board. Furthermore, built-in AI is also a part of the developed system that performs its features through image processing. The system maintains the privacy and interactive transition of data to its users on kiosk devices.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"1 1","pages":""},"PeriodicalIF":0.7,"publicationDate":"2021-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70457969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/RTCSA50079.2020.9203632
Yewon Jo, Suhyeon Yoo, H. Bahn
A new task scheduling algorithm that schedules mixed task set consisting of real-time and interactive tasks is presented. Our algorithm aims at minimizing the power consumption of the system with the reasonable response time of interactive tasks as well as the deadline guarantees of real-time tasks. Experimental results show that the proposed algorithm improves the power consumption by 23% on average.
{"title":"Student Session:Power-Saving Integrated Task Scheduling in Multicore and Hybrid Memory Environment","authors":"Yewon Jo, Suhyeon Yoo, H. Bahn","doi":"10.1109/RTCSA50079.2020.9203632","DOIUrl":"https://doi.org/10.1109/RTCSA50079.2020.9203632","url":null,"abstract":"A new task scheduling algorithm that schedules mixed task set consisting of real-time and interactive tasks is presented. Our algorithm aims at minimizing the power consumption of the system with the reasonable response time of interactive tasks as well as the deadline guarantees of real-time tasks. Experimental results show that the proposed algorithm improves the power consumption by 23% on average.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"87 1","pages":"1-2"},"PeriodicalIF":0.7,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86722133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/RTCSA50079.2020.9203667
Philippe Glanon, S. Azaiez, C. Mraidha
This paper tackles the scheduling of loop-intensive applications modeled by synchronous dataflow graphs (SDFGs) on heterogeneous multiprocessor architectures under resource and communication constraints. Scheduling an application graph on multiprocessor architectures under resource constraints is a well-known NP-hard problem widely addressed in the previous decades with the goal of optimizing different performance metrics such as latency, memory allocations, energy consumption, throughput, etc. In this paper, we focus on the study of cyclic scheduling strategies and specifically the software pipelined schedules of SDFGs under the resource and communication constraints of heterogeneous multiprocessor architectures and we made two major contributions. The first contribution is an integer linear programming (ILP) model for the exact resolution of the scheduling problem and the second contribution is a time-efficient heuristic that generates scheduling solutions close to the optimal solutions generated with our ILP model.
{"title":"Cyclic Scheduling of Loop-Intensive Applications on Heterogeneous Multiprocessor Architectures","authors":"Philippe Glanon, S. Azaiez, C. Mraidha","doi":"10.1109/RTCSA50079.2020.9203667","DOIUrl":"https://doi.org/10.1109/RTCSA50079.2020.9203667","url":null,"abstract":"This paper tackles the scheduling of loop-intensive applications modeled by synchronous dataflow graphs (SDFGs) on heterogeneous multiprocessor architectures under resource and communication constraints. Scheduling an application graph on multiprocessor architectures under resource constraints is a well-known NP-hard problem widely addressed in the previous decades with the goal of optimizing different performance metrics such as latency, memory allocations, energy consumption, throughput, etc. In this paper, we focus on the study of cyclic scheduling strategies and specifically the software pipelined schedules of SDFGs under the resource and communication constraints of heterogeneous multiprocessor architectures and we made two major contributions. The first contribution is an integer linear programming (ILP) model for the exact resolution of the scheduling problem and the second contribution is a time-efficient heuristic that generates scheduling solutions close to the optimal solutions generated with our ILP model.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"57 1","pages":"1-10"},"PeriodicalIF":0.7,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74512723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/RTCSA50079.2020.9203646
John Cavicchio, N. Fisher
The benefits of the limited preemption scheduling model serve to minimize preemption overhead while enabling cooperative scheduling between real-time tasks. Preemption point placement (PPP) algorithms are employed to select a suitable subset of preemption locations for limited preemption scheduling that optimize task worst case execution time. Similarly, preemption threshold scheduling enhances schedulability in a fully-preemptive environment by taking advantage of execution time slack in a task set by adjusting preemption thresholds to permit tasks to completely execute non-preemptively where possible. The ability to execute non-preemptively offers reduced cache related preemption delay (CRPD) further enhancing limited preemption schedulability. In this work, we integrate limited preemption scheduling using preemption placement with preemption threshold scheduling to realize further task set schedulability benefits. A case study using synthetically generated tasksets will demonstrate the significantly improved (up to a 30% increase in breakdown utilization) schedulability benefits of our proposed integrated PPP and optimal threshold assignment (OTA) algorithm.
有限抢占调度模型的好处是在支持实时任务之间的协作调度的同时，最大限度地减少了抢占开销。采用PPP (Preemption point placement)算法选择合适的抢占位置子集进行有限的抢占调度，优化任务最坏情况下的执行时间。类似地，抢占阈值调度通过调整抢占阈值以允许任务在可能的情况下完全非抢占地执行，从而利用任务集中的执行时间空闲，从而增强了完全抢占环境中的可调度性。非抢占执行的能力减少了与缓存相关的抢占延迟(CRPD)，进一步增强了有限的抢占可调度性。在这项工作中，我们将使用抢占放置的有限抢占调度与抢占阈值调度相结合，以实现进一步的任务集可调度性优势。使用综合生成任务集的案例研究将展示我们提出的集成PPP和最优阈值分配(OTA)算法的可调度性优势的显着改善(故障利用率提高30%)。
{"title":"Integrating Preemption Thresholds with Limited Preemption Scheduling","authors":"John Cavicchio, N. Fisher","doi":"10.1109/RTCSA50079.2020.9203646","DOIUrl":"https://doi.org/10.1109/RTCSA50079.2020.9203646","url":null,"abstract":"The benefits of the limited preemption scheduling model serve to minimize preemption overhead while enabling cooperative scheduling between real-time tasks. Preemption point placement (PPP) algorithms are employed to select a suitable subset of preemption locations for limited preemption scheduling that optimize task worst case execution time. Similarly, preemption threshold scheduling enhances schedulability in a fully-preemptive environment by taking advantage of execution time slack in a task set by adjusting preemption thresholds to permit tasks to completely execute non-preemptively where possible. The ability to execute non-preemptively offers reduced cache related preemption delay (CRPD) further enhancing limited preemption schedulability. In this work, we integrate limited preemption scheduling using preemption placement with preemption threshold scheduling to realize further task set schedulability benefits. A case study using synthetically generated tasksets will demonstrate the significantly improved (up to a 30% increase in breakdown utilization) schedulability benefits of our proposed integrated PPP and optimal threshold assignment (OTA) algorithm.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"449 1","pages":"1-10"},"PeriodicalIF":0.7,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79686673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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