Yoichi Wakaba, S. Wakabayashi, Shinobu Nagayama, Masato Inagi
This paper proposes a method using partial reconfiguration to realize a compact regular expression matching engine, which can update a pattern quickly. In the proposed method, a set of partial circuits, each of which handles a different class of regular expressions, are provided in advance. When a regular expression pattern is given, a compact matching engine dedicated to the pattern is implemented on FPGA by combining the partial circuits according to the given pattern using partial reconfiguration. The method can update a pattern quickly, since it does not need re-design of a circuit. Experimental results show that the proposed method reduces 60% circuit size compared with the previous method without increasing the pattern updating time significantly.
{"title":"An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating","authors":"Yoichi Wakaba, S. Wakabayashi, Shinobu Nagayama, Masato Inagi","doi":"10.2197/ipsjtsldm.7.110","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.7.110","url":null,"abstract":"This paper proposes a method using partial reconfiguration to realize a compact regular expression matching engine, which can update a pattern quickly. In the proposed method, a set of partial circuits, each of which handles a different class of regular expressions, are provided in advance. When a regular expression pattern is given, a compact matching engine dedicated to the pattern is implemented on FPGA by combining the partial circuits according to the given pattern using partial reconfiguration. The method can update a pattern quickly, since it does not need re-design of a circuit. Experimental results show that the proposed method reduces 60% circuit size compared with the previous method without increasing the pattern updating time significantly.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86109074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Efficient Algorithm for 3D NoC Architecture Optimization","authors":"Xin Jiang, Ran Zhang, Takahiro Watanabe","doi":"10.2197/ipsjtsldm.6.34","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.34","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87300161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Intra-frame encoding is useful for many video applications such as security surveillance, digital cinema, and video conferencing because it supports random access to every video frame for easy editing and has low computational complexity that results in low hardware cost. H.264/AVC, which is the most popular video coding standard today, also defines novel intra-coding tools to achieve high compression performance at the expense of significantly increased computational complexity. We present a VLSI design for H.264/AVC intra-frame encoder. The paper summaries several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4 × 4 luma blocks, integrate a high-performance hardwired CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized with a TSMC 130 nm CMOS cell library, our design requires 194.1 K gates at 108 MHz and consumes 19.8 mW to encode 1080p (1920 × 1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. We suggest a figure of merit called Design Efficiency for fair comparison of different works. Experimental results show that the proposed design is more efficient than prior arts.
{"title":"VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding","authors":"Huang-Chih Kuo, Y. Lin","doi":"10.2197/ipsjtsldm.6.76","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.76","url":null,"abstract":"Intra-frame encoding is useful for many video applications such as security surveillance, digital cinema, and video conferencing because it supports random access to every video frame for easy editing and has low computational complexity that results in low hardware cost. H.264/AVC, which is the most popular video coding standard today, also defines novel intra-coding tools to achieve high compression performance at the expense of significantly increased computational complexity. We present a VLSI design for H.264/AVC intra-frame encoder. The paper summaries several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4 × 4 luma blocks, integrate a high-performance hardwired CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized with a TSMC 130 nm CMOS cell library, our design requires 194.1 K gates at 108 MHz and consumes 19.8 mW to encode 1080p (1920 × 1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. We suggest a figure of merit called Design Efficiency for fair comparison of different works. Experimental results show that the proposed design is more efficient than prior arts.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78802015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, J. Bormann, Markus Wedler, Minh D. Nguyen, D. Stoffel, W. Kunz
: This paper describes a method to generate a computational model for formal verification of hardware- dependent software in embedded systems. The computational model of the combined HW / SW system is a program netlist (PN) consisting of instruction cells connected in a directed acyclic graph that compactly represents all execution paths of the software. The model can be easily integrated into SAT-based verification environments such as those based on Bounded Model Checking (BMC). The proposed construction of the model allows for an e ffi cient reasoning of the SAT solver over entire execution paths. Program netlists are compositional. The paper presents how they can be com- bined to model interrupt-driven systems. We demonstrate the e ffi ciency of our approach by presenting experimental results from the formal verification of an industrial LIN (Local Interconnect Network) bus node, implemented as a software driver on a 32-bit RISC machine.
{"title":"A New Formal Verification Approach for Hardware-dependent Embedded System Software","authors":"Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, J. Bormann, Markus Wedler, Minh D. Nguyen, D. Stoffel, W. Kunz","doi":"10.2197/ipsjtsldm.6.135","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.135","url":null,"abstract":": This paper describes a method to generate a computational model for formal verification of hardware- dependent software in embedded systems. The computational model of the combined HW / SW system is a program netlist (PN) consisting of instruction cells connected in a directed acyclic graph that compactly represents all execution paths of the software. The model can be easily integrated into SAT-based verification environments such as those based on Bounded Model Checking (BMC). The proposed construction of the model allows for an e ffi cient reasoning of the SAT solver over entire execution paths. Program netlists are compositional. The paper presents how they can be com- bined to model interrupt-driven systems. We demonstrate the e ffi ciency of our approach by presenting experimental results from the formal verification of an industrial LIN (Local Interconnect Network) bus node, implemented as a software driver on a 32-bit RISC machine.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87111110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sangyoung Park, Younghyun Kim, Jaehyun Park, N. Chang
Semiconductor scaling makes the individual part can no longer share the same supply voltage, and some chips even require multiple different supply voltage levels. Different input and output voltage standard specification of each device make use of multiple supply voltage levels. Various devices such as display, RF, USB, SD card, etc. increase the number of supply voltage levels. Moreover, analog devices often do not allow sharing power supply due to coupling noise. However, those components are commonly powered by a single power source such as a battery. Consequently, power converters such as onand off-chip switching-mode DC–DC converters, low-dropout linear regulators and charge pumps are largely populated even on a single circuit board. Efficiency of the power converters is known to be high enough and often ignored during power management policy development. However, their actual conversion efficiency varies significantly according to device activity and power mode, which sometimes results in substantially lower efficiency than the value provided in datasheets. Moreover, hardware designers generally optimize the power converters for the maximum power supply current of the device and even perform over-design while the actual device power consumption during runtime could be largely offset from the energy-optimal operating point. This tutorial paper covers a wide range of topics on power converter-aware design and introduces several design practices; i) power converter basics and the conversion efficiency, ii) power converter voltage transition overhead, iii) power converter-aware design of embedded systems, and iv) maximum energy transfer of energy harvesting devices.
{"title":"Power Converter-aware Design of Electronics Systems","authors":"Sangyoung Park, Younghyun Kim, Jaehyun Park, N. Chang","doi":"10.2197/ipsjtsldm.6.2","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.2","url":null,"abstract":"Semiconductor scaling makes the individual part can no longer share the same supply voltage, and some chips even require multiple different supply voltage levels. Different input and output voltage standard specification of each device make use of multiple supply voltage levels. Various devices such as display, RF, USB, SD card, etc. increase the number of supply voltage levels. Moreover, analog devices often do not allow sharing power supply due to coupling noise. However, those components are commonly powered by a single power source such as a battery. Consequently, power converters such as onand off-chip switching-mode DC–DC converters, low-dropout linear regulators and charge pumps are largely populated even on a single circuit board. Efficiency of the power converters is known to be high enough and often ignored during power management policy development. However, their actual conversion efficiency varies significantly according to device activity and power mode, which sometimes results in substantially lower efficiency than the value provided in datasheets. Moreover, hardware designers generally optimize the power converters for the maximum power supply current of the device and even perform over-design while the actual device power consumption during runtime could be largely offset from the energy-optimal operating point. This tutorial paper covers a wide range of topics on power converter-aware design and introduces several design practices; i) power converter basics and the conversion efficiency, ii) power converter voltage transition overhead, iii) power converter-aware design of embedded systems, and iv) maximum energy transfer of energy harvesting devices.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88357464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuko Hara-Azumi, Toshinobu Matsuba, H. Tomiyama, S. Honda, H. Takada
For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology.
{"title":"Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks","authors":"Yuko Hara-Azumi, Toshinobu Matsuba, H. Tomiyama, S. Honda, H. Takada","doi":"10.2197/ipsjtsldm.6.122","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.122","url":null,"abstract":"For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90253966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
: 2D / 3D packing optimization is facing big challenges to get better solution with less runtime. In this paper, we propose a new variation of adaptive simulated annealing (ASA) to solve packing problem. In the traditional ASA, the parameters that control temperature scheduling and random step selection are adjusted according to search progress. In the proposed ASA, a guide with adaptive probabilities is used to automatically select moving methods, including crossover to improve its e ffi ciency. The interesting point is the traditional SA with crossover is ine ffi cient, while the proposed ASA with crossover is e ffi cient due to the adaptive guide. Based on the experiment using MCNC, ami49 X and ami98 3D benchmarks, the computational performance is considerably improved. In the case of area minimization, the results gotten by the proposed ASA are normally better than the published data of 2D packing. In the case of volume minimization for 3D packing, the results gotten by the proposed ASA are better than the data of traditional ASA and SA.
{"title":"A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization","authors":"Yiqiang Sheng, A. Takahashi","doi":"10.2197/ipsjtsldm.6.94","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.94","url":null,"abstract":": 2D / 3D packing optimization is facing big challenges to get better solution with less runtime. In this paper, we propose a new variation of adaptive simulated annealing (ASA) to solve packing problem. In the traditional ASA, the parameters that control temperature scheduling and random step selection are adjusted according to search progress. In the proposed ASA, a guide with adaptive probabilities is used to automatically select moving methods, including crossover to improve its e ffi ciency. The interesting point is the traditional SA with crossover is ine ffi cient, while the proposed ASA with crossover is e ffi cient due to the adaptive guide. Based on the experiment using MCNC, ami49 X and ami98 3D benchmarks, the computational performance is considerably improved. In the case of area minimization, the results gotten by the proposed ASA are normally better than the published data of 2D packing. In the case of volume minimization for 3D packing, the results gotten by the proposed ASA are better than the data of traditional ASA and SA.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78724809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents two acceleration techniques of fault simulation for analyzing soft error propagation in sequential circuits. One is an exact technique and the other is a heuristic technique. Since these techniques are independent on how the logic functions of circuits are evaluated, they can be combined with other techniques which accelerate evaluations of the logic functions of circuits, such as event-driven simulation, single pattern parallel fault propagation (SPPFP). Experimental results show that applying the exact technique makes a fault simulator with event-driven simulation and SPPFP 30–143 times faster. A fault simulator with the exact technique finished for several large-scale circuits in 4.6 hours or less, while a fault simulator without the exact technique could not finish for such circuits in 72 hours. Furthermore, applying the heuristic technique makes a fault simulator with the exact technique about 7–17 times faster with only 0.5–2.2% estimation error.
{"title":"Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits","authors":"Taiga Takata, Masayoshi Yoshimura, Y. Matsunaga","doi":"10.2197/ipsjtsldm.6.127","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.127","url":null,"abstract":"This paper presents two acceleration techniques of fault simulation for analyzing soft error propagation in sequential circuits. One is an exact technique and the other is a heuristic technique. Since these techniques are independent on how the logic functions of circuits are evaluated, they can be combined with other techniques which accelerate evaluations of the logic functions of circuits, such as event-driven simulation, single pattern parallel fault propagation (SPPFP). Experimental results show that applying the exact technique makes a fault simulator with event-driven simulation and SPPFP 30–143 times faster. A fault simulator with the exact technique finished for several large-scale circuits in 4.6 hours or less, while a fault simulator without the exact technique could not finish for such circuits in 72 hours. Furthermore, applying the heuristic technique makes a fault simulator with the exact technique about 7–17 times faster with only 0.5–2.2% estimation error.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78392951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The IP-based storage systems often require bandwidth intensive access to storage devices, thus they exhibit high CPU utilization and low throughput when executed in a principally software implementation. This is especially evident for multi-Gbps networks where the impact of computational overhead is so pronounced that the current state of the art processors cannot take advantage of the capacity of the network. In this paper we propose new iSCSI Offload Engine architecture for high data rate storage networking. Based on our analysis of open source Open-iSCSI initiator, we offload the most computationally intensive and the most executed functions in a common case scenario, while other functions are implemented in a modified Open-iSCSI initiator on a general purpose processor. Our architecture overcomes the performance limitations imposed by a single processor which runs on 15x higher operating frequency than our accelerator. It exhibits very low CPU utilization of approximately 3% on the host CPU, which is 10–15x reduction compared with software implementation. The maximum transmission throughput is 7.81 Gbps, while reception throughput is 7.34 Gbps, which is 2 times speedup over software. The new architecture also shows comparable performance with Chelsio T110 ASIC-based HBA, and has more flexibility.
{"title":"Design and Implementation of IP-based iSCSI Offload Engine on an FPGA","authors":"Amila Akagic, H. Amano","doi":"10.2197/ipsjtsldm.6.112","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.112","url":null,"abstract":"The IP-based storage systems often require bandwidth intensive access to storage devices, thus they exhibit high CPU utilization and low throughput when executed in a principally software implementation. This is especially evident for multi-Gbps networks where the impact of computational overhead is so pronounced that the current state of the art processors cannot take advantage of the capacity of the network. In this paper we propose new iSCSI Offload Engine architecture for high data rate storage networking. Based on our analysis of open source Open-iSCSI initiator, we offload the most computationally intensive and the most executed functions in a common case scenario, while other functions are implemented in a modified Open-iSCSI initiator on a general purpose processor. Our architecture overcomes the performance limitations imposed by a single processor which runs on 15x higher operating frequency than our accelerator. It exhibits very low CPU utilization of approximately 3% on the host CPU, which is 10–15x reduction compared with software implementation. The maximum transmission throughput is 7.81 Gbps, while reception throughput is 7.34 Gbps, which is 2 times speedup over software. The new architecture also shows comparable performance with Chelsio T110 ASIC-based HBA, and has more flexibility.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85014173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. We have reported a secure and testable scan design approach by using extended shift registers called "SR- equivalents" that are functionally equivalent but not structurally equivalent to shift registers(14), (15), (16), (17), (18). In this paper, to further extend the class of SR-equivalents we introduce a wider class of circuits called "SR-quasi- equivalents" which still satisfy the testability and security similar to SR-equivalents. To estimate the security level, we clarify the cardinality of each equivalent class in SR-quasi-equivalents for several linear structural circuits, and also present the actual number of SR-quasi-equivalents obtained by the enhanced program SREEP.
{"title":"Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents","authors":"Katsuya Fujiwara, H. Fujiwara, H. Tamamoto","doi":"10.2197/ipsjtsldm.6.27","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.27","url":null,"abstract":"Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. We have reported a secure and testable scan design approach by using extended shift registers called \"SR- equivalents\" that are functionally equivalent but not structurally equivalent to shift registers(14), (15), (16), (17), (18). In this paper, to further extend the class of SR-equivalents we introduce a wider class of circuits called \"SR-quasi- equivalents\" which still satisfy the testability and security similar to SR-equivalents. To estimate the security level, we clarify the cardinality of each equivalent class in SR-quasi-equivalents for several linear structural circuits, and also present the actual number of SR-quasi-equivalents obtained by the enhanced program SREEP.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89295142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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