Pub Date : 2020-06-01DOI: 10.1109/drc50226.2020.9150531
F. Mehmood, T. Mikolajick, U. Schroeder
A century ago ferroelectricity was discovered by J. Valasek[1] which can be used in non-volatile memory applications based on two energetically stable distinct electric polarization states. The conventional perovskite based ferroelectric materials suffer from CMOS incompatibility and scalability issues, hence cannot be used in state of the art scaled CMOS technologies. In 2011, ferroelectricity was reported in CMOS compatible scaled doped HfO2 films [2-3], which can solve the integration issues of perovskites based ferroelectrics. Among the HfO2 based ferroelectric materials, the mixed oxide of HfO2 and ZrO2 (Hf0.5Zr0.5O2) exhibits good ferroelectric properties with a wide process window and CMOS back-end compatible thermal budget.
{"title":"Reliability improvement of ferroelectric Hf0.5Zr0.5O2 thin films by Lanthanum doping for FeRAM applications","authors":"F. Mehmood, T. Mikolajick, U. Schroeder","doi":"10.1109/drc50226.2020.9150531","DOIUrl":"https://doi.org/10.1109/drc50226.2020.9150531","url":null,"abstract":"A century ago ferroelectricity was discovered by J. Valasek[1] which can be used in non-volatile memory applications based on two energetically stable distinct electric polarization states. The conventional perovskite based ferroelectric materials suffer from CMOS incompatibility and scalability issues, hence cannot be used in state of the art scaled CMOS technologies. In 2011, ferroelectricity was reported in CMOS compatible scaled doped HfO2 films [2-3], which can solve the integration issues of perovskites based ferroelectrics. Among the HfO2 based ferroelectric materials, the mixed oxide of HfO2 and ZrO2 (Hf0.5Zr0.5O2) exhibits good ferroelectric properties with a wide process window and CMOS back-end compatible thermal budget.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125033981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135150
J. Stearns, G. Moddel
Geometric diodes have the potential to provide ultra-fast rectification [1] , which can be used in rectennas for high-efficiency conversion of infrared signals into DC electrical power. We present for the first time simulations of the high frequency characteristics of these devices, to supplement previous measurements at 28 THz. The operating principle of the geometric diode is shown in Fig. 1 . Charge carriers are funneled in one direction more easily than the other, giving rise to diode behavior. To facilitate the geometric effect, ballistic transport is needed, which requires the mean-free path length of charge carriers to be on the order of, or larger than, critical device dimensions [2] . To be fabricable, these dimensions must be on the order of at least tens of nanometers which makes graphene, with room- temperature mean-free path lengths approaching 1 μm [3] , an attractive material choice. In this size regime, the possibility of high frequency operation is possible as charge transport is not limited by diffusive scattering. We developed a Monte Carlo simulator to compute high frequency current-voltage characteristics for a graphene geometric diode. We find that the diode behavior extends into the terahertz range with a cutoff falling near graphene’s damping parameter as predicted by Drude conductivity.
{"title":"High Frequency Characteristics of Graphene Geometric Diodes","authors":"J. Stearns, G. Moddel","doi":"10.1109/DRC50226.2020.9135150","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135150","url":null,"abstract":"Geometric diodes have the potential to provide ultra-fast rectification [1] , which can be used in rectennas for high-efficiency conversion of infrared signals into DC electrical power. We present for the first time simulations of the high frequency characteristics of these devices, to supplement previous measurements at 28 THz. The operating principle of the geometric diode is shown in Fig. 1 . Charge carriers are funneled in one direction more easily than the other, giving rise to diode behavior. To facilitate the geometric effect, ballistic transport is needed, which requires the mean-free path length of charge carriers to be on the order of, or larger than, critical device dimensions [2] . To be fabricable, these dimensions must be on the order of at least tens of nanometers which makes graphene, with room- temperature mean-free path lengths approaching 1 μm [3] , an attractive material choice. In this size regime, the possibility of high frequency operation is possible as charge transport is not limited by diffusive scattering. We developed a Monte Carlo simulator to compute high frequency current-voltage characteristics for a graphene geometric diode. We find that the diode behavior extends into the terahertz range with a cutoff falling near graphene’s damping parameter as predicted by Drude conductivity.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116945835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135148
A. Tan, Li-Chen Wang, Y. Liao, J. Bae, C. Hu, S. Salahuddin
Ferroelectric (FE) FETs as nonvolatile memories have enjoyed a recent resurgence among emerging memory technologies due to the discovery of ferroelectricity in HfO 2 [1] . FE-HfO 2 offers attractive qualities such as CMOS compatibility, fast read/write speed, excellent retention, and scalability [2] . However, as write endurance remains a concern, various techniques have been proposed to improve endurance; among them, popular ones include engineering of the interfacial layer (IL), modulating the FE oxide properties, and changing the gate electrode [ 2 - 5 ]. In this work, we demonstrate for the first time a systematic, reliable, and rapid method to qualitatively predict the FE endurance of prospective gate stack designs prior to running a full FeFET fabrication process. MOSCAPs incorporating FE gate stacks (∼ 4.5 nm) realized via a one-step lithography process on highly doped Si are compared against real endurance results from SOI FeFETs incorporating the same FE oxides. The FeFETs demonstrated in this work boast impressive programmability (0.4 - 0.5V memory window at ±3.3V, 1 µ s) and a strong potential for further scalability.
{"title":"Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET","authors":"A. Tan, Li-Chen Wang, Y. Liao, J. Bae, C. Hu, S. Salahuddin","doi":"10.1109/DRC50226.2020.9135148","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135148","url":null,"abstract":"Ferroelectric (FE) FETs as nonvolatile memories have enjoyed a recent resurgence among emerging memory technologies due to the discovery of ferroelectricity in HfO 2 [1] . FE-HfO 2 offers attractive qualities such as CMOS compatibility, fast read/write speed, excellent retention, and scalability [2] . However, as write endurance remains a concern, various techniques have been proposed to improve endurance; among them, popular ones include engineering of the interfacial layer (IL), modulating the FE oxide properties, and changing the gate electrode [ 2 - 5 ]. In this work, we demonstrate for the first time a systematic, reliable, and rapid method to qualitatively predict the FE endurance of prospective gate stack designs prior to running a full FeFET fabrication process. MOSCAPs incorporating FE gate stacks (∼ 4.5 nm) realized via a one-step lithography process on highly doped Si are compared against real endurance results from SOI FeFETs incorporating the same FE oxides. The FeFETs demonstrated in this work boast impressive programmability (0.4 - 0.5V memory window at ±3.3V, 1 µ s) and a strong potential for further scalability.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114448007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135175
E. Brown, W.-D. Zhang, P. Fakhimi, T. A. Growden, P. R. Berger
Resonant tunneling diodes (RTDs) have come full-circle in the past 10 years after their demonstration in the early 1990s as the fastest room-temperature semiconductor oscillator, displaying experimental results up to 712 GHz and f max values exceeding 1.0 THz [1] . Now the RTD is once again the preeminent electronic oscillator above 1.0 THz and is being implemented as a coherent source [2] and a self-oscillating mixer [3] , amongst other applications. This paper concerns RTD electroluminescence - an effect that has been studied very little in the past 30+ years of RTD development, and not at room temperature. We present experiments and modeling of an n-type In 0 .53Ga 0 .47As/AlAs double-barrier RTD operating as a cross-gap light emitter at ~300K. The MBE-growth stack is shown in Fig. 1(a) . A 15-μm-diam-mesa device was defined by standard planar processing including a top annular ohmic contact with a 5-μm-diam pinhole in the center to couple out enough of the internal emission for accurate free-space power measurements [4] . The emission spectra have the behavior displayed in Fig. 1(b) , parameterized by bias voltage (V B ). The long wavelength emission edge is at λ = 1684 nm - close to the In 0.53 Ga 0 . 47 As bandgap energy of U g ≈ 0.75 eV at 300 K. The spectral peaks for V B = 2.8 and 3.0 V both occur around λ = 1550 nm (hv = 0.75 eV), so blue-shifted relative to the peak of the "ideal", bulk InGaAs emission spectrum shown in Fig. 1(b) [5] . These results are consistent with the model displayed in Fig. 1(c) , whereby the broad emission peak is attributed to the radiative recombination between electrons accumulated on the emitter side, and holes generated on the emitter side by interband tunneling with current density J interr . The blue-shifted main peak is attributed to the quantum-size effect on the emitter side, which creates a radiative recombination rate R N,2 comparable to the band-edge cross-gap rate R N,1 . Further support for this model is provided by the shorter wavelength and weaker emission peak shown in Fig. 1(b) around λ = 1148 nm. Our quantum mechanical calculations attribute this to radiative recombination R R,3 in the RTD quantum well between the electron ground-state level E 1,e , and the hole level E 1,h .
{"title":"RTD Light Emission around 1550 nm with IQE up to 6% at 300 K","authors":"E. Brown, W.-D. Zhang, P. Fakhimi, T. A. Growden, P. R. Berger","doi":"10.1109/DRC50226.2020.9135175","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135175","url":null,"abstract":"Resonant tunneling diodes (RTDs) have come full-circle in the past 10 years after their demonstration in the early 1990s as the fastest room-temperature semiconductor oscillator, displaying experimental results up to 712 GHz and f max values exceeding 1.0 THz [1] . Now the RTD is once again the preeminent electronic oscillator above 1.0 THz and is being implemented as a coherent source [2] and a self-oscillating mixer [3] , amongst other applications. This paper concerns RTD electroluminescence - an effect that has been studied very little in the past 30+ years of RTD development, and not at room temperature. We present experiments and modeling of an n-type In 0 .53Ga 0 .47As/AlAs double-barrier RTD operating as a cross-gap light emitter at ~300K. The MBE-growth stack is shown in Fig. 1(a) . A 15-μm-diam-mesa device was defined by standard planar processing including a top annular ohmic contact with a 5-μm-diam pinhole in the center to couple out enough of the internal emission for accurate free-space power measurements [4] . The emission spectra have the behavior displayed in Fig. 1(b) , parameterized by bias voltage (V B ). The long wavelength emission edge is at λ = 1684 nm - close to the In 0.53 Ga 0 . 47 As bandgap energy of U g ≈ 0.75 eV at 300 K. The spectral peaks for V B = 2.8 and 3.0 V both occur around λ = 1550 nm (hv = 0.75 eV), so blue-shifted relative to the peak of the \"ideal\", bulk InGaAs emission spectrum shown in Fig. 1(b) [5] . These results are consistent with the model displayed in Fig. 1(c) , whereby the broad emission peak is attributed to the radiative recombination between electrons accumulated on the emitter side, and holes generated on the emitter side by interband tunneling with current density J interr . The blue-shifted main peak is attributed to the quantum-size effect on the emitter side, which creates a radiative recombination rate R N,2 comparable to the band-edge cross-gap rate R N,1 . Further support for this model is provided by the shorter wavelength and weaker emission peak shown in Fig. 1(b) around λ = 1148 nm. Our quantum mechanical calculations attribute this to radiative recombination R R,3 in the RTD quantum well between the electron ground-state level E 1,e , and the hole level E 1,h .","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135180
Chia-Chun Yen, An-Hung Tai, Yu-Chieh Liu, C. Yeh, C. Liu
The double layer (DL) TFT consists of an IGZO channel layer with no oxygen flow (NOF) and an IGZO barrier layer with oxygen flow (OF). The DL-TFT demonstrates the field-effect mobility of 19 cm2/V-s, which is 1.6X of the NOF and the OF singe-layer TFTs (SL-TFTs) at the overdrive voltage of 18V and the drain voltage of 0.1V. The conduction band difference between NOF and OF IGZO is 0.28 eV, which was obtained by Tauc method, X-Ray photoelectron spectroscopy (XPS), and Kevin probe force microscopy (KPFM). The carriers in the DL-TFT are confined in the NOF layer by quantum confinement, where the OF layer serves as the barrier to reduce the Coulomb scattering between the channel electrons and oxide charge, and the surface roughness scattering from the IGZO/oxide interface. The results of positive bias temperature instability (PBTI) show that the threshold voltage shift of the DL-TFT is between the individual SL-TFT, and the DL-TFT is close to the lower one of the two SL-TFTs.
{"title":"Mobility Enhancement and Reliability Characterization of Back-Channel-Etch Amorphous InGaZnO TFT with Double Layers","authors":"Chia-Chun Yen, An-Hung Tai, Yu-Chieh Liu, C. Yeh, C. Liu","doi":"10.1109/DRC50226.2020.9135180","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135180","url":null,"abstract":"The double layer (DL) TFT consists of an IGZO channel layer with no oxygen flow (NOF) and an IGZO barrier layer with oxygen flow (OF). The DL-TFT demonstrates the field-effect mobility of 19 cm2/V-s, which is 1.6X of the NOF and the OF singe-layer TFTs (SL-TFTs) at the overdrive voltage of 18V and the drain voltage of 0.1V. The conduction band difference between NOF and OF IGZO is 0.28 eV, which was obtained by Tauc method, X-Ray photoelectron spectroscopy (XPS), and Kevin probe force microscopy (KPFM). The carriers in the DL-TFT are confined in the NOF layer by quantum confinement, where the OF layer serves as the barrier to reduce the Coulomb scattering between the channel electrons and oxide charge, and the surface roughness scattering from the IGZO/oxide interface. The results of positive bias temperature instability (PBTI) show that the threshold voltage shift of the DL-TFT is between the individual SL-TFT, and the DL-TFT is close to the lower one of the two SL-TFTs.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127763171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135164
Aditi Agarwal, Kijeong Han, B. Baliga
The body diode of a SiC power MOSFET is not suitable for current conduction in the third quadrant due high on-state voltage drop, large reverse recovery losses [1] , and possibility of bipolar degradation [2] . Integrating a Junction Barrier Schottky (JBS) diode with the MOSFET (called JBSFET) solves these issues [3] , [4] for 1.2 kV devices. This paper reports experimental data on 2.3 kV JBSFETs with different cell topologies (Linear, Hexagonal and Octagonal) for the first time at this larger voltage capability .
{"title":"2.3 kV 4H-SiC Accumulation-channel JBSFETs: Experimental Comparison of Linear, Hexagonal and Octagonal Cell Topologies","authors":"Aditi Agarwal, Kijeong Han, B. Baliga","doi":"10.1109/DRC50226.2020.9135164","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135164","url":null,"abstract":"The body diode of a SiC power MOSFET is not suitable for current conduction in the third quadrant due high on-state voltage drop, large reverse recovery losses [1] , and possibility of bipolar degradation [2] . Integrating a Junction Barrier Schottky (JBS) diode with the MOSFET (called JBSFET) solves these issues [3] , [4] for 1.2 kV devices. This paper reports experimental data on 2.3 kV JBSFETs with different cell topologies (Linear, Hexagonal and Octagonal) for the first time at this larger voltage capability .","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121249958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135171
J. Sakhuja, S. Lashkare, V. Saraswat, U. Ganguly
Resistive Random-Access Memory (ReRAM) devices with filamentary and non-filamentary resistive switching (RS) mechanisms are extensively explored for Neuromorphic applications to cater to the present-day dataintensive computing requirements. In filamentary RRAMs, the electric field and Joule heating dependent threshold switching is well established ( Fig. 1a ) [1] . Alternatively, electric-field driven ionic transport was responsible for nonfilamentary memory characteristics ( Fig. 1b ) [2] . In recent studies, self-heating-based mechanism in addition to ionic transport has been suggested in non-filamentary devices ( Fig. 1c ) [3] . This boosts thermally activated ionic drift, thereby enhancing the switching behavior within the device. Different techniques like the incorporation of heater elements or thermally insulating layers such as GST to improve heat confinement within the stack has been proposed to improve device characteristics [4] . Recently, highly non-linear I-V characteristics have been demonstrated in PMO based RRAM in its Low Resistance State (LRS). The PMO material has very low thermal conductivity (0.5W/m-K), which facilitates thermal feedback leading to non-linearity (NL). Further, independent of enhanced RS, two capabilities of PMO-RRAM devices have been demonstrated. Firstly, NL enabled selector-less memory operations, which are highly attractive in crossbar memory arrays ( Fig. 1d ) [5] . Secondly, it facilitates oscillations based on NL related NDR from thermal runaway( Fig. 1e ) [6] , [7] . Thus, investigating & engineering the NL is of significant interest. In this paper, we modify the thermal circuit of the PMO RRAM device stack by changing isolation SiO 2 thickness, keeping the rest of the electronic/ionic aspects of the RRAM structure identical. We show~ 38% reduction in threshold voltage in DC and an 8x improvement in heating transients as a response to thermal circuit engineering.
{"title":"Thermal Engineering of Volatile Switching in PrMnO3 RRAM: Non-Linearity in DC IV Characteristics and Transient Switching Speed","authors":"J. Sakhuja, S. Lashkare, V. Saraswat, U. Ganguly","doi":"10.1109/DRC50226.2020.9135171","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135171","url":null,"abstract":"Resistive Random-Access Memory (ReRAM) devices with filamentary and non-filamentary resistive switching (RS) mechanisms are extensively explored for Neuromorphic applications to cater to the present-day dataintensive computing requirements. In filamentary RRAMs, the electric field and Joule heating dependent threshold switching is well established ( Fig. 1a ) [1] . Alternatively, electric-field driven ionic transport was responsible for nonfilamentary memory characteristics ( Fig. 1b ) [2] . In recent studies, self-heating-based mechanism in addition to ionic transport has been suggested in non-filamentary devices ( Fig. 1c ) [3] . This boosts thermally activated ionic drift, thereby enhancing the switching behavior within the device. Different techniques like the incorporation of heater elements or thermally insulating layers such as GST to improve heat confinement within the stack has been proposed to improve device characteristics [4] . Recently, highly non-linear I-V characteristics have been demonstrated in PMO based RRAM in its Low Resistance State (LRS). The PMO material has very low thermal conductivity (0.5W/m-K), which facilitates thermal feedback leading to non-linearity (NL). Further, independent of enhanced RS, two capabilities of PMO-RRAM devices have been demonstrated. Firstly, NL enabled selector-less memory operations, which are highly attractive in crossbar memory arrays ( Fig. 1d ) [5] . Secondly, it facilitates oscillations based on NL related NDR from thermal runaway( Fig. 1e ) [6] , [7] . Thus, investigating & engineering the NL is of significant interest. In this paper, we modify the thermal circuit of the PMO RRAM device stack by changing isolation SiO 2 thickness, keeping the rest of the electronic/ionic aspects of the RRAM structure identical. We show~ 38% reduction in threshold voltage in DC and an 8x improvement in heating transients as a response to thermal circuit engineering.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117181835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135159
Mehdi Saremi, A. Pal, Liu Jiang, E. Bazizi, Helen Lee, Xi-Wei Lin, B. Alexander, Buvna Ayyagari-Sangamalli
Development of a new complex technology such as 3D NAND requires significant efforts in terms of materials screening, process tuning, and device design leading to fabrication and characterization of many test wafers with significant time-to-market cost. In this context, modeling can help accelerate 3D NAND technology development. Therefore, in this work, modeling platform is used to investigate such devices. Cross-talk (or cell-to-cell interference) is one of the major concerns in NAND technology, preventing its further scaling. To reduce crosstalk between neighboring cells in this paper, we analyze a 3D NAND structure with separated charge trap regions and compare its performance with the conventional device having continuous charge trap region.
{"title":"Modeling and Optimization of Advanced 3D NAND Memory","authors":"Mehdi Saremi, A. Pal, Liu Jiang, E. Bazizi, Helen Lee, Xi-Wei Lin, B. Alexander, Buvna Ayyagari-Sangamalli","doi":"10.1109/DRC50226.2020.9135159","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135159","url":null,"abstract":"Development of a new complex technology such as 3D NAND requires significant efforts in terms of materials screening, process tuning, and device design leading to fabrication and characterization of many test wafers with significant time-to-market cost. In this context, modeling can help accelerate 3D NAND technology development. Therefore, in this work, modeling platform is used to investigate such devices. Cross-talk (or cell-to-cell interference) is one of the major concerns in NAND technology, preventing its further scaling. To reduce crosstalk between neighboring cells in this paper, we analyze a 3D NAND structure with separated charge trap regions and compare its performance with the conventional device having continuous charge trap region.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117093304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135183
Ahmad Zubair, J. Niroula, N. Chowdhury, Yuhao Zhang, J. Lemettinen, T. Palacios
By 2030, about 80% of all US electricity is expected to flow through power electronics. This will require power electronic devices and circuits with much higher efficiency and smaller form-factor than today’s silicon-based systems. III-Nitride semiconductors and other ultra-wide bandgap materials are ideal platforms for the new generation of power electronics thanks to the combination of excellent transport properties and the high critical electric field enabled by their wide bandgap [1] . This talk will discuss recent progress in our group in developing high voltage power transistors and diodes based on wide bandgap materials.
{"title":"Materials and Technology Issues for the Next Generation of Power Electronic Devices","authors":"Ahmad Zubair, J. Niroula, N. Chowdhury, Yuhao Zhang, J. Lemettinen, T. Palacios","doi":"10.1109/DRC50226.2020.9135183","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135183","url":null,"abstract":"By 2030, about 80% of all US electricity is expected to flow through power electronics. This will require power electronic devices and circuits with much higher efficiency and smaller form-factor than today’s silicon-based systems. III-Nitride semiconductors and other ultra-wide bandgap materials are ideal platforms for the new generation of power electronics thanks to the combination of excellent transport properties and the high critical electric field enabled by their wide bandgap [1] . This talk will discuss recent progress in our group in developing high voltage power transistors and diodes based on wide bandgap materials.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"515 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120886967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135147
R. S. Khan, A. H. Talukder, F. Dirisaglik, A. Gokirmak, H. Silva
Phase change memory (PCM) is a high speed, high endurance, high density non-volatile memory technology that utilizes chalcogenide materials such as Ge 2 Sb 2 Te 5 (GST) that can be electrically cycled between highly resistive amorphous and low resistance crystalline phases. The resistance of the amorphous phase of PCM cells increase (drift) in time following a power law [1] , which increases the memory window in time but limits in the implementation of multi-bit-per-cell PCM. There has been a number of theories explaining the origin of drift [1] – [4] , mostly attributing it to structural relaxation, a thermally activated rearrangement of atoms in the amorphous structure [2] . Most of the studies on resistance drift are based on experiments at or above room temperature, where multiple processes may be occurring simultaneously. In this work, we melt-quenched amorphized GST line cells with widths ~120-140 nm, lengths ~390-500 nm, and thickness ~50nm ( Fig. 1 ) and monitored the current-voltage (I-V) characteristics using a parameter analyzer ( Fig. 2 ) in 85 K to 350 K range. We extracted the drift co-efficient from the slope of the resistance vs. time plots (using low-voltage measurements) and observed resistance drift in the 125 K -300 K temperature range ( Fig. 3 ). We found an approximately linear increase in drift coefficient as a function of temperature from ~ 0.07 at 125 K to ~ 0.11 at 200 K and approximately constant drift coefficients in the 200 K to 300 K range ( Fig. 3 inset). These results suggest that structural relaxations alone cannot account for resistance drift, additional mechanisms are contributing to this phenomenon [5] , [6] .
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