Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135155
A. Kumar, K. N. Nazif, P. Ramesh, K. Saraswat
Doping of two-dimensional (2D) transition metal dichalcogenides (TMDs) is needed to adjust the threshold voltage (V T ) and to increase the current drive by reducing both the channel and sheet resistances [1] . However, doping in TMDs often results in a sharp degradation in the on-off ratio of the field-effect transistors (FETs) [2] , [3] . Tungsten disulfide (WS 2 ) is a layered TMD with a large band-gap (> 2 eV in bilayers [4] ). We show a stable n-type doping technique using sub-stoichiometric Aluminum oxide (AlO X ) [5] in exfoliated bilayer WS 2 transistors which results in the highest reported per-layer on-current for WS 2 (80 µA/µm per layer) while retaining the high on-off ratio (10 8 ) and low off-current (≈ 5x10 -13 A/μm). Modelling these devices reveals a large interfacial trap density (1×10 13 cm 2 eV -1 ) and a high Schottky barrier height (SBH) at the contacts (0.4 eV).
需要掺杂二维(2D)过渡金属二硫族化合物(TMDs)来调整阈值电压(V T)，并通过降低通道和片电阻来增加电流驱动[1]。然而，在tmd中掺杂往往会导致场效应晶体管(fet)的通断比急剧下降[2]，[3]。二硫化钨(ws2)是一种层状TMD，具有较大的带隙(在双层中> 2ev[4])。我们展示了一种稳定的n型掺杂技术，使用亚化学计量氧化铝(AlO X)[5]在剥离双层ws2晶体管中获得了最高的每层导通电流(每层80 μ a /μm)，同时保持了高通断比(10 8)和低导通电流(≈5 × 10 -13 a /μm)。对这些器件进行建模后发现，它们具有较大的界面陷阱密度(1×10 13 cm 2 eV -1)和高肖特基势垒高度(SBH)。
{"title":"Doped WS2 transistors with large on-off ratio and high on-current","authors":"A. Kumar, K. N. Nazif, P. Ramesh, K. Saraswat","doi":"10.1109/DRC50226.2020.9135155","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135155","url":null,"abstract":"Doping of two-dimensional (2D) transition metal dichalcogenides (TMDs) is needed to adjust the threshold voltage (V T ) and to increase the current drive by reducing both the channel and sheet resistances [1] . However, doping in TMDs often results in a sharp degradation in the on-off ratio of the field-effect transistors (FETs) [2] , [3] . Tungsten disulfide (WS 2 ) is a layered TMD with a large band-gap (> 2 eV in bilayers [4] ). We show a stable n-type doping technique using sub-stoichiometric Aluminum oxide (AlO X ) [5] in exfoliated bilayer WS 2 transistors which results in the highest reported per-layer on-current for WS 2 (80 µA/µm per layer) while retaining the high on-off ratio (10 8 ) and low off-current (≈ 5x10 -13 A/μm). Modelling these devices reveals a large interfacial trap density (1×10 13 cm 2 eV -1 ) and a high Schottky barrier height (SBH) at the contacts (0.4 eV).","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123245531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135176
Ahmad Zubair, J. Perozek, J. Niroula, O. Aktas, V. Odnoblyudov, T. Palacios
GaN vertical power FinFETs are promising high voltage switches for the next generation of high-frequency power electronics applications. Thanks to a vertical fin channel, the device offers excellent electrostatic and threshold voltage control, eliminating the need for epitaxial regrowth 1 or p-type doping 2 unlike other vertical GaN power transistors. Vertical GaN FinFETs with 1200 V breakdown voltage (BV), 5 A current rating and excellent switching figure of merit have been demonstrated recently on free-standing GaN substrates 3 . Despite this promising performance, the commercialization of these devices has been limited by the high cost ($50-$100/cm 2 ) and small diameter (~ 2 inch) of free-standing GaN substrates. The use of GaN-on-Si wafers could reduce the substrate cost by ×1000, however the growth of the thick (~10 μm or thicker) drift layers required for kV class applications is extremely challenging on Si. Alternatively, GaN grown on engineered substrates (QST ® ) with a matched thermal expansion coefficient could enable low-cost vertical GaN FinFETs with thick (>10 μm) drift layers and large wafer diameters (8-12 inch). In this work, we demonstrate GaN power FinFETs on engineered substrates for the first time.
{"title":"First Demonstration of GaN Vertical Power FinFETs on Engineered Substrate","authors":"Ahmad Zubair, J. Perozek, J. Niroula, O. Aktas, V. Odnoblyudov, T. Palacios","doi":"10.1109/DRC50226.2020.9135176","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135176","url":null,"abstract":"GaN vertical power FinFETs are promising high voltage switches for the next generation of high-frequency power electronics applications. Thanks to a vertical fin channel, the device offers excellent electrostatic and threshold voltage control, eliminating the need for epitaxial regrowth 1 or p-type doping 2 unlike other vertical GaN power transistors. Vertical GaN FinFETs with 1200 V breakdown voltage (BV), 5 A current rating and excellent switching figure of merit have been demonstrated recently on free-standing GaN substrates 3 . Despite this promising performance, the commercialization of these devices has been limited by the high cost ($50-$100/cm 2 ) and small diameter (~ 2 inch) of free-standing GaN substrates. The use of GaN-on-Si wafers could reduce the substrate cost by ×1000, however the growth of the thick (~10 μm or thicker) drift layers required for kV class applications is extremely challenging on Si. Alternatively, GaN grown on engineered substrates (QST ® ) with a matched thermal expansion coefficient could enable low-cost vertical GaN FinFETs with thick (>10 μm) drift layers and large wafer diameters (8-12 inch). In this work, we demonstrate GaN power FinFETs on engineered substrates for the first time.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128432008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135168
C. Kuo, Shui-Jinn Wang, Po-Ting Chen, R. Ko
Introduction: Recently, the use of high surface-to-volume ratio sensing materials, such as TiO 2 , ZnO, and NiO nanostructures, used for pH sensing were demonstrated [ 1 – 4 ]. High response over 44.5 mV/pH was obtained, which was explained as being attributed to increase ion adsorption sites of sensing electrodes (SEs). In this work, pH SEs with improved sensing performance based on hydrothermal growth (HTG) of NiO NSs on Hierarchically roughened Si substrates, which could significantly increase the ion adsorption sites, are proposed and demonstrated. A dual roughening scheme to form pyramidal cones and Si nanowires (Si NWs) consecutively is employed. For comparison, pH sensing performance of SEs with a different combination of the Si NWs, KOH-etched Si substrates, and HTG NiO NSs are also investigated and the benefit of the nanostructures is analyzed. Possible mechanism governing the enhancement in pH sensing response is also proposed and discussed.
{"title":"Near-Nernstian pH Sensors Based on Hydrothermally Grown NiO Nanosheets on Hierarchically Roughened Si Substrates","authors":"C. Kuo, Shui-Jinn Wang, Po-Ting Chen, R. Ko","doi":"10.1109/DRC50226.2020.9135168","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135168","url":null,"abstract":"Introduction: Recently, the use of high surface-to-volume ratio sensing materials, such as TiO 2 , ZnO, and NiO nanostructures, used for pH sensing were demonstrated [ 1 – 4 ]. High response over 44.5 mV/pH was obtained, which was explained as being attributed to increase ion adsorption sites of sensing electrodes (SEs). In this work, pH SEs with improved sensing performance based on hydrothermal growth (HTG) of NiO NSs on Hierarchically roughened Si substrates, which could significantly increase the ion adsorption sites, are proposed and demonstrated. A dual roughening scheme to form pyramidal cones and Si nanowires (Si NWs) consecutively is employed. For comparison, pH sensing performance of SEs with a different combination of the Si NWs, KOH-etched Si substrates, and HTG NiO NSs are also investigated and the benefit of the nanostructures is analyzed. Possible mechanism governing the enhancement in pH sensing response is also proposed and discussed.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"351 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116517596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135173
D. Ji, B. Ercan, Jia Zhuang, Lei Gu, J. Rivas-Davila, S. Chowdhury
Wide bandgap semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC), have bandgap energies larger than 3 eV with high breakdown electric fields, showing the advantage on powerful IMPATT diodes. SiC IMPATT diodes have been successfully demonstrated and shown excellent performances in X-band applications [1] , [2] . Although a few theoretical studies have shown the great potential of GaN for powerful IMPATT diodes [3] , [4] , no experimental study has been reported so far. Taking advantage of the single crystalline GaN substrates enabling high quality GaN films, avalanche capability has been demonstrated [5] – [9] . In this study, we demonstrated a GaN-based IMPATT diode experimentally by using a n-i-p epitaxial structure grown on a bulk GaN substrate.
{"title":"Demonstration of GaN Impact Ionization Avalanche Transit-Time (IMPATT) Diode","authors":"D. Ji, B. Ercan, Jia Zhuang, Lei Gu, J. Rivas-Davila, S. Chowdhury","doi":"10.1109/DRC50226.2020.9135173","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135173","url":null,"abstract":"Wide bandgap semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC), have bandgap energies larger than 3 eV with high breakdown electric fields, showing the advantage on powerful IMPATT diodes. SiC IMPATT diodes have been successfully demonstrated and shown excellent performances in X-band applications [1] , [2] . Although a few theoretical studies have shown the great potential of GaN for powerful IMPATT diodes [3] , [4] , no experimental study has been reported so far. Taking advantage of the single crystalline GaN substrates enabling high quality GaN films, avalanche capability has been demonstrated [5] – [9] . In this study, we demonstrated a GaN-based IMPATT diode experimentally by using a n-i-p epitaxial structure grown on a bulk GaN substrate.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123077861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135187
Xiaohan Wu, Ruijing Ge, D. Akinwande, Jack C. Lee
Various two-dimensional materials, such as graphene oxide, solution-processed or phase-change transitional metal dichalcogenides (TMDs), degraded black phosphorus and multilayer hexagonal boron nitride (h-BN) [ 1 - 5 ], have been reported to exhibit non-volatile resistance switching (NVRS) phenomenon, in which the resistance can be reversibly switched between a high resistance state (HRS) and a low resistance state (LRS) through external electrical bias and maintained without power supply. Recently, we reported the observation of NVRS in single-layer TMDs and h-BN atomristors (memristor effect in atomically thin nanomaterials) with forming-free characteristic, large on/off current ratio (up to 10 7 ) and fast switching speed (< 15 ns) [ 6 - 8 ]. Here, to investigate the switching mechanisms in the 2D monolayers, we introduced a new electrical characterization method by current sweeping to illustrate the detailed information hidden in the commonly used voltage-sweep curves, showing multiple transition steps in the SET process. Moreover, by varying the SET compliance current in voltage-sweep measurement, multiple resistance states can be obtained with a range of five orders of magnitude. These results provide strong evidence for the previously reported conductive-bridge-like model of 2D atomristors [8] , and enable further applications in multi-bit data storage and analog-like neuromorphic computing.
{"title":"Understanding of Multiple Resistance States by Current-sweep Measurement and Compliance Current Modulation in 2D MoS2-based Non-volatile Resistance Switching Devices","authors":"Xiaohan Wu, Ruijing Ge, D. Akinwande, Jack C. Lee","doi":"10.1109/DRC50226.2020.9135187","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135187","url":null,"abstract":"Various two-dimensional materials, such as graphene oxide, solution-processed or phase-change transitional metal dichalcogenides (TMDs), degraded black phosphorus and multilayer hexagonal boron nitride (h-BN) [ 1 - 5 ], have been reported to exhibit non-volatile resistance switching (NVRS) phenomenon, in which the resistance can be reversibly switched between a high resistance state (HRS) and a low resistance state (LRS) through external electrical bias and maintained without power supply. Recently, we reported the observation of NVRS in single-layer TMDs and h-BN atomristors (memristor effect in atomically thin nanomaterials) with forming-free characteristic, large on/off current ratio (up to 10 7 ) and fast switching speed (< 15 ns) [ 6 - 8 ]. Here, to investigate the switching mechanisms in the 2D monolayers, we introduced a new electrical characterization method by current sweeping to illustrate the detailed information hidden in the commonly used voltage-sweep curves, showing multiple transition steps in the SET process. Moreover, by varying the SET compliance current in voltage-sweep measurement, multiple resistance states can be obtained with a range of five orders of magnitude. These results provide strong evidence for the previously reported conductive-bridge-like model of 2D atomristors [8] , and enable further applications in multi-bit data storage and analog-like neuromorphic computing.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127930944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135167
Sebastian Lukas, S. Kataria, M. Prechtl, Oliver Hartwig, A. Meledin, J. Mayer, D. Neumaier, G. Duesberg, M. Lemme
Platinum diselenide (PtSe 2 ) is a promising two-dimensional (2D) material of the noble-metal dichalcogenides (NMDCs), a subgroup of the transition-metal dichalcogenides (TMDCs). It has been shown to exhibit a high negative piezoresistive gauge factor (GF) [1] and a charge carrier mobility of up to 210 cm 2 /Vs while being air-stable for many months [2] . It can be grown at CMOS-compatible temperatures by thermally assisted conversion (TAC) [3] . PtSe 2 can be tuned from a semiconductor to a semimetal by varying the number of layers [4] – [7] . Experimental data of electronic devices based on PtSe 2 show large variations in the electronic properties that cannot be explained by the material thickness alone. Here, we show that the nanocrystalline structure of TAC-grown PtSe 2 films greatly influences the electronic properties of PtSe 2 -based devices.
二硒化铂(PtSe 2)是过渡金属二硫化物(TMDCs)亚族贵金属二硫化物(NMDCs)中一种很有前途的二维(2D)材料。它已被证明具有高负压阻测量因子(GF)[1]和高达210 cm 2 /Vs的电荷载流子迁移率，同时具有数月的空气稳定性[2]。它可以通过热辅助转换(TAC)在cmos兼容的温度下生长[3]。通过改变层数可以将PtSe 2从半导体调谐到半金属[4]-[7]。基于PtSe 2的电子器件的实验数据显示，其电子性能的巨大变化不能仅用材料厚度来解释。在这里，我们发现tac生长的PtSe 2薄膜的纳米晶结构对PtSe 2基器件的电子性能有很大的影响。
{"title":"Correlation of Material Structure and Electronic Properties in 2D Platinum-Diselenide-based Devices","authors":"Sebastian Lukas, S. Kataria, M. Prechtl, Oliver Hartwig, A. Meledin, J. Mayer, D. Neumaier, G. Duesberg, M. Lemme","doi":"10.1109/DRC50226.2020.9135167","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135167","url":null,"abstract":"Platinum diselenide (PtSe 2 ) is a promising two-dimensional (2D) material of the noble-metal dichalcogenides (NMDCs), a subgroup of the transition-metal dichalcogenides (TMDCs). It has been shown to exhibit a high negative piezoresistive gauge factor (GF) [1] and a charge carrier mobility of up to 210 cm 2 /Vs while being air-stable for many months [2] . It can be grown at CMOS-compatible temperatures by thermally assisted conversion (TAC) [3] . PtSe 2 can be tuned from a semiconductor to a semimetal by varying the number of layers [4] – [7] . Experimental data of electronic devices based on PtSe 2 show large variations in the electronic properties that cannot be explained by the material thickness alone. Here, we show that the nanocrystalline structure of TAC-grown PtSe 2 films greatly influences the electronic properties of PtSe 2 -based devices.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128108057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135151
Yi-Ping Huang, Ching-Sung Lee, W. Hsu
GaN-based HEMTs feature a lot of superior material properties, including high electron mobility, wide band-gap, and large breakdown field. These properties are very suitable for power electronic applications. However, due to the high two dimensional electron gas (2DEG) density, a conventional GaN HEMT is an inherently normally-on device. Considering safety design in the power electronic systems, high performance normally-off GaN HEMT s are needed [1] . FinFet (tri-gate) structure has recently been applied to GaN HEMTs for the normally-off operation. However, a conventional FinFet (tri-gate) GaN HEMT requires very small channel widths to achieve the normally-off operation. This needs very critical process conditions and could cause the on-resistance (R on ) to be obviouslhy degraded [2] . In this study, an InAlN/GaN fin-MOSHEMT combined with fluorine treatment is demonstrated. It doesn’t require very small channel widths to achieve a normally-off HEMT while having excellent performances.
{"title":"Normally-Off InAlN/GaN Fin-MOSHEMT with Fluorine Treatment","authors":"Yi-Ping Huang, Ching-Sung Lee, W. Hsu","doi":"10.1109/DRC50226.2020.9135151","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135151","url":null,"abstract":"GaN-based HEMTs feature a lot of superior material properties, including high electron mobility, wide band-gap, and large breakdown field. These properties are very suitable for power electronic applications. However, due to the high two dimensional electron gas (2DEG) density, a conventional GaN HEMT is an inherently normally-on device. Considering safety design in the power electronic systems, high performance normally-off GaN HEMT s are needed [1] . FinFet (tri-gate) structure has recently been applied to GaN HEMTs for the normally-off operation. However, a conventional FinFet (tri-gate) GaN HEMT requires very small channel widths to achieve the normally-off operation. This needs very critical process conditions and could cause the on-resistance (R on ) to be obviouslhy degraded [2] . In this study, an InAlN/GaN fin-MOSHEMT combined with fluorine treatment is demonstrated. It doesn’t require very small channel widths to achieve a normally-off HEMT while having excellent performances.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130526450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135165
Wenjian Liu, I. Sayed, B. Romanczyk, N. Hatui, Jana Georgieva, Haoran Li, S. Keller, U. Mishra
N-polar GaN based HEMTs have demonstrated superior performance for solid-state millimeter wave power amplifiers [1] , [2] . To further improve the high-frequency and high-power performance in N-polar GaN HEMTs, using a small gate length while preserving a good aspect ratio is critical. Currently, N-polar HEMTs utilize a thin gate dielectric to reduce gate leakage. This reduces the aspect ratio. Therefore, removing the gate dielectrics, i.e. using Schottky-HEMTs in N-polar GaN is very attractive to pursue highly scaled and high-performance devices. Previous studies [3] – [6] have shown that the barrier heights between the gate metals and N-polar GaN are relatively low and the reverse leakages may be too high to be used in practical Schottky-HEMTs. Here, we report the first investigation of ruthenium (Ru) on N-polar GaN Schottky barrier. The device shows near-ideal Schottky characteristic under reverse bias and forward bias . The barrier height values at various temperatures extracted from the forward bias region and the reverse bias region agree well. The extracted barrier height is 0.77 eV at room temperature. The reverse leakage is ultralow with ~10 -6 A/cm 2 at -5 V and follows ideal thermionic behavior .
{"title":"Near-ideal Ru/N-polar GaN Schottky diode with ultralow reverse leakage","authors":"Wenjian Liu, I. Sayed, B. Romanczyk, N. Hatui, Jana Georgieva, Haoran Li, S. Keller, U. Mishra","doi":"10.1109/DRC50226.2020.9135165","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135165","url":null,"abstract":"N-polar GaN based HEMTs have demonstrated superior performance for solid-state millimeter wave power amplifiers [1] , [2] . To further improve the high-frequency and high-power performance in N-polar GaN HEMTs, using a small gate length while preserving a good aspect ratio is critical. Currently, N-polar HEMTs utilize a thin gate dielectric to reduce gate leakage. This reduces the aspect ratio. Therefore, removing the gate dielectrics, i.e. using Schottky-HEMTs in N-polar GaN is very attractive to pursue highly scaled and high-performance devices. Previous studies [3] – [6] have shown that the barrier heights between the gate metals and N-polar GaN are relatively low and the reverse leakages may be too high to be used in practical Schottky-HEMTs. Here, we report the first investigation of ruthenium (Ru) on N-polar GaN Schottky barrier. The device shows near-ideal Schottky characteristic under reverse bias and forward bias . The barrier height values at various temperatures extracted from the forward bias region and the reverse bias region agree well. The extracted barrier height is 0.77 eV at room temperature. The reverse leakage is ultralow with ~10 -6 A/cm 2 at -5 V and follows ideal thermionic behavior .","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130794532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/drc50226.2020.9135162
G. Rughoobur, J. Zhao, L. Jain, Ahmad Zubair, T. Palacios, J. Kong, A. Akinwande
A vacuum channel transistor is the ultimate wide band-gap structure with potential for high Johnson figure of merit (~10 14 V/s) due to no electron scattering and no impact ionization/breakdown [1] , [2] . Hence, nanoscale vacuum channel transistors (NVCTs) can possibly outperform solid-state transistors in terms of speed, breakdown voltage and reliability in harsh environments [1] . Carriers are injected into the channel by electron tunneling across a barrier narrowed by an electric field. Such electron sources can be realized using nanoscale gated Si field emitter arrays (FEAs) with high packing densities (≥10 8 /cm 2 ) and self-aligned apertures which have low turn-on voltage (8.5 V), low operating voltage, high current density (150 A/cm 2 ) and long lifetime (>300 hours) [3] . The barrier height is nonetheless sensitive to adsorption/desorption of gas molecules, resulting in large current variations in poor vacuum, which can also generate energetic ions that erode the emitter. Hence FEAs require costly and bulky ultra-high vacuum (UHV) systems for reliability [4] . Using multi-layers of graphene (Gr) that withstand high pressure gradients and, are transparent to electrons, but impervious to gas molecules, can enable operation of these FEAs in poor vacuum [5] , [6] . In this paper, Gr layers are used to encapsulate such FEAs with two self-aligned gates ( Fig. 1 ); this structure allows an independent control of the bias applied to the Gr layer, and significantly reduces the volume to be encapsulated.
{"title":"Enabling Atmospheric Operation of Nanoscale Vacuum Channel Transistors","authors":"G. Rughoobur, J. Zhao, L. Jain, Ahmad Zubair, T. Palacios, J. Kong, A. Akinwande","doi":"10.1109/drc50226.2020.9135162","DOIUrl":"https://doi.org/10.1109/drc50226.2020.9135162","url":null,"abstract":"A vacuum channel transistor is the ultimate wide band-gap structure with potential for high Johnson figure of merit (~10 14 V/s) due to no electron scattering and no impact ionization/breakdown [1] , [2] . Hence, nanoscale vacuum channel transistors (NVCTs) can possibly outperform solid-state transistors in terms of speed, breakdown voltage and reliability in harsh environments [1] . Carriers are injected into the channel by electron tunneling across a barrier narrowed by an electric field. Such electron sources can be realized using nanoscale gated Si field emitter arrays (FEAs) with high packing densities (≥10 8 /cm 2 ) and self-aligned apertures which have low turn-on voltage (8.5 V), low operating voltage, high current density (150 A/cm 2 ) and long lifetime (>300 hours) [3] . The barrier height is nonetheless sensitive to adsorption/desorption of gas molecules, resulting in large current variations in poor vacuum, which can also generate energetic ions that erode the emitter. Hence FEAs require costly and bulky ultra-high vacuum (UHV) systems for reliability [4] . Using multi-layers of graphene (Gr) that withstand high pressure gradients and, are transparent to electrons, but impervious to gas molecules, can enable operation of these FEAs in poor vacuum [5] , [6] . In this paper, Gr layers are used to encapsulate such FEAs with two self-aligned gates ( Fig. 1 ); this structure allows an independent control of the bias applied to the Gr layer, and significantly reduces the volume to be encapsulated.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133442017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135184
Woojin Choi, V. Balasubramanian, P. Asbeck, S. Dayeh
In today’s radio-frequency (RF) systems, linearity of amplifiers is a key concern due to presence of significant numbers of in-band interferers in the crowded spectrum. GaN high electron mobility transistors (HEMTs) can provide low noise front-end amplifiers, but state-of-the-art GaN HEMTs still possess non-linearity exhibited by a transconductance, g m , roll-off from its peak due to the dynamic source access resistance and other factors [1] . The dynamic range figure-of-merit (DRFOM) for low noise amplifiers (LNAs) [2] , OIP3/(F-1)P DC , where OIP3 is the output 3 rd -order intercept point (OIP3), P DC is the DC power, and F is the noise factor, is still limited to ~1.7 in mmwave GaN transistors [3] . Joglekar et al. attempted to increase linearity by using different Fin widths resulted in flat g m of ~2 V [1] ; linearity figures of merit were not properly assessed. Here, we demonstrate a novel method to synthesize g m plateau over a 6 V gate overdrive and a record DRFOM of 10.1 in GaN HEMTs at 30 GHz.
在当今的射频(RF)系统中，由于在拥挤的频谱中存在大量带内干扰，放大器的线性度是一个关键问题。GaN高电子迁移率晶体管(hemt)可以提供低噪声的前端放大器，但由于动态源接入电阻和其他因素，最先进的GaN hemt仍然具有非线性，表现为跨导，g / m，从峰值滚降[1]。在毫米波GaN晶体管[3]中，低噪声放大器(lna)[2]的动态范围品质因数(DRFOM) OIP3/(F-1)P DC，其中OIP3为输出3阶截距点(OIP3)， P DC为直流功率，F为噪声因子，仍然限制在~1.7。Joglekar等人试图通过使用不同的翅片宽度来增加线性度，导致平面g = ~2 V [1];优点的线性数字没有得到适当的评估。在这里，我们展示了一种新的方法，在30 GHz的GaN hemt中，在6v栅极超速驱动上合成了gm平台，并记录了10.1的DRFOM。
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