Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135185
Jun Tao, Debarghya Sarkar, Sizhe Weng, Hyun Uk Chae, Ragib Ahsan, R. Kapadia
Heterogeneous integration of high-quality crystalline semiconductor materials and devices compatible with the back end of line (BEOL) CMOS wafers are fundamentally limited by two factors: (i) the lack of a crystalline growth surface and (ii) the <400 ° C thermal budget. Here, we demonstrate a platform for monolithic integration III-V devices directly on amorphous substrates at a growth temperature of 300 ° C by low temperature templated liquid phase (LT-TLP) method. Furthermore, we demonstrate that degenerately doped materials can also be directly grown at <400 °C via LT-TLP, establishing the building blocks for high performance back end devices.
{"title":"A Platform for Monolithic Back End of Line III-V Integration","authors":"Jun Tao, Debarghya Sarkar, Sizhe Weng, Hyun Uk Chae, Ragib Ahsan, R. Kapadia","doi":"10.1109/DRC50226.2020.9135185","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135185","url":null,"abstract":"Heterogeneous integration of high-quality crystalline semiconductor materials and devices compatible with the back end of line (BEOL) CMOS wafers are fundamentally limited by two factors: (i) the lack of a crystalline growth surface and (ii) the <400 ° C thermal budget. Here, we demonstrate a platform for monolithic integration III-V devices directly on amorphous substrates at a growth temperature of 300 ° C by low temperature templated liquid phase (LT-TLP) method. Furthermore, we demonstrate that degenerately doped materials can also be directly grown at <400 °C via LT-TLP, establishing the building blocks for high performance back end devices.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133285819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135146
M. B. Khan, Sayantani Ghosh, S. Prucnal, T. Mauersberger, R. Hübner, M. Simon, T. Mikolajick, A. Erbe, Y. Georgiev
For decades the miniaturization of logic circuitry was a result of down scaling of the field effect transistor (FET). This scaling has reached its end and, therefore, new device materials and concepts have been under research for the last years. One approach is to increase the functionality of an individual device rather than scaling down its size. Such a device concept is the reconfigurable FET (RFET), which can be configured to n- or p- polarity dynamically [1] .
{"title":"Towards Scalable Reconfigurable Field Effect Transistor using Flash Lamp Annealing","authors":"M. B. Khan, Sayantani Ghosh, S. Prucnal, T. Mauersberger, R. Hübner, M. Simon, T. Mikolajick, A. Erbe, Y. Georgiev","doi":"10.1109/DRC50226.2020.9135146","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135146","url":null,"abstract":"For decades the miniaturization of logic circuitry was a result of down scaling of the field effect transistor (FET). This scaling has reached its end and, therefore, new device materials and concepts have been under research for the last years. One approach is to increase the functionality of an individual device rather than scaling down its size. Such a device concept is the reconfigurable FET (RFET), which can be configured to n- or p- polarity dynamically [1] .","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127949999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135182
Eldad Bahat Treidel, O. Hilt, H. Christopher, A. Klehr, A. Ginolas, A. Liero, J. Würfl
Vertical GaN based MISFETs for high voltage power switching applications have the potential to outperform Si and SiC based competitors in terms of power density and switching speed [1] – [3] . In this work the development of vertical GaN MISFET technology is focused on pulsed laser driving applications with maximum voltages < 100 V ( Fig. 1 ). Drivers for pulsed lasers are required to deliver very high currents up to 250 A in very short pulse lengths of 3 ns to 10 ns [4] . Vertical GaN MISFETs are in particular suited for realizing the required very steep current slopes due to their low output capacitance and gate charge figure of merits, C OSS × R ON and Q G * R ON . Further, the vertical GaN transistor topology enables a compact assembly of the laser diode die directly on top of the GaN transistor die to achieve an ultimately small current loop inductance ( Fig. 1 ) in the laser drive circuit. Additionally, the vertical device concept allows aggressive device scaling and enables a high current density per unit area [5] . On the other hand, the channel conductivity under inversion conditions may be compromised by high insulator channel interface defect density. This would result in low mobility and low carrier density. In this work devices with different gate trench orientation to the a- and m- GaN lattice planes grown on ammono-thermal substrate [8] are studied. Fig. 2 explains the location of the respective planes in the lattice and the convention of crystal cut to identify them on the wafer. Recently, it was demonstrated that devices grown on sapphire and on Si substrates with gate trench parallel to the GaN m -plane have superior conduction properties [6] – [7] ; however this is in contradiction to our finding. The epitaxial layers are grown by MOVPE. The epitaxial stack consists of 3.2 gm n + -GaN drain substrate contact layer, 5.3 gm n - -GaN (1.4 × 10 17 cm -3 ) drift layer, 300 nm p -GaN (1.5 × 10 17 cm -3 ) blocking layer followed by 500 nm n -GaN (1 × 10 18 cm -3 ) source cap [5] . The device process sequence follows the "ohmic contacts first" concept. For simplifying electrical characterization an additional top side drain ohmic contact is formed on the wafer front side along with the source ohmic contact in a coplanar pad configuration. Next a 25 nm Al 2 O 3 gate insulator is deposited by PEALD on the opened trench sidewall. The gate electrode consists of a sputtered TiW film reinforced with electroplated Au. For electrical evaluation two similar devices types with gate trenches parallel to the crystal m -plane and a -plane are measured. The transistors have a hexagonal cell design with the same gate width of 32.0 mm and ~305 mm / mm 2 gate density ( Fig. 3 ). The devices are electrically characterized using simultaneous 200 μs gate and drain pulses. Fig. 4 summarizes the wafer level median bidirectional sweep transfer and output characteristics of the vertical GaN MISFETs measured on the two devices types. While the m -plane devices
图7还显示了不同激发水平下约905 nm的发射波长。
{"title":"The influence of the gate trench orientation to the crystal plane on the conduction properties of vertical GaN MISFETs for laser driving applications","authors":"Eldad Bahat Treidel, O. Hilt, H. Christopher, A. Klehr, A. Ginolas, A. Liero, J. Würfl","doi":"10.1109/DRC50226.2020.9135182","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135182","url":null,"abstract":"Vertical GaN based MISFETs for high voltage power switching applications have the potential to outperform Si and SiC based competitors in terms of power density and switching speed [1] – [3] . In this work the development of vertical GaN MISFET technology is focused on pulsed laser driving applications with maximum voltages < 100 V ( Fig. 1 ). Drivers for pulsed lasers are required to deliver very high currents up to 250 A in very short pulse lengths of 3 ns to 10 ns [4] . Vertical GaN MISFETs are in particular suited for realizing the required very steep current slopes due to their low output capacitance and gate charge figure of merits, C OSS × R ON and Q G * R ON . Further, the vertical GaN transistor topology enables a compact assembly of the laser diode die directly on top of the GaN transistor die to achieve an ultimately small current loop inductance ( Fig. 1 ) in the laser drive circuit. Additionally, the vertical device concept allows aggressive device scaling and enables a high current density per unit area [5] . On the other hand, the channel conductivity under inversion conditions may be compromised by high insulator channel interface defect density. This would result in low mobility and low carrier density. In this work devices with different gate trench orientation to the a- and m- GaN lattice planes grown on ammono-thermal substrate [8] are studied. Fig. 2 explains the location of the respective planes in the lattice and the convention of crystal cut to identify them on the wafer. Recently, it was demonstrated that devices grown on sapphire and on Si substrates with gate trench parallel to the GaN m -plane have superior conduction properties [6] – [7] ; however this is in contradiction to our finding. The epitaxial layers are grown by MOVPE. The epitaxial stack consists of 3.2 gm n + -GaN drain substrate contact layer, 5.3 gm n - -GaN (1.4 × 10 17 cm -3 ) drift layer, 300 nm p -GaN (1.5 × 10 17 cm -3 ) blocking layer followed by 500 nm n -GaN (1 × 10 18 cm -3 ) source cap [5] . The device process sequence follows the \"ohmic contacts first\" concept. For simplifying electrical characterization an additional top side drain ohmic contact is formed on the wafer front side along with the source ohmic contact in a coplanar pad configuration. Next a 25 nm Al 2 O 3 gate insulator is deposited by PEALD on the opened trench sidewall. The gate electrode consists of a sputtered TiW film reinforced with electroplated Au. For electrical evaluation two similar devices types with gate trenches parallel to the crystal m -plane and a -plane are measured. The transistors have a hexagonal cell design with the same gate width of 32.0 mm and ~305 mm / mm 2 gate density ( Fig. 3 ). The devices are electrically characterized using simultaneous 200 μs gate and drain pulses. Fig. 4 summarizes the wafer level median bidirectional sweep transfer and output characteristics of the vertical GaN MISFETs measured on the two devices types. While the m -plane devices","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135160
Y. Illarionov, A. Banshchikov, T. Knobloch, D. Polyushkin, S. Wachter, V. Fedorov, S. Suturin, M. Stöger-Pollach, T. Mueller, M. Vexler, N. Sokolov, T. Grasser
Two-dimensional (2D) electronics can enable FETs down to a few nanometers. However, these devices require scalable insulators which should form high-quality interfaces with 2D channels and maintain low gate leakage currents for sub-1nm equivalent oxide thickness (EOT). Previously used amorphous oxides result in poor interfaces with 2D materials, while hBN has mediocre dielectric properties ( ε < 5, E g = 6eV) [1] . As a promising alternative, we suggest the use of the crystalline ionic insulator CaF 2 ( ε = 8.43, E g = 12.1eV) which forms van der Waals interfaces with 2D semiconductors [2] . At the moment, CaF 2 can be grown by molecular-beam epitaxy (MBE) down to a few nanometers thickness [3] and appears promising for chemical vapour deposition (CVD) [4] and atomic-layer deposition (ALD) [5] . Here we discuss our recent progress [3] , [6] , [7] on ultra-thin CaF 2 which presents a universal platform for 2D devices. In particular, we demonstrate nanoscale MoS 2 FETs with L =50-60nm and a record-thin ~ 2nm CaF 2 insulator (EOT~ 0.9nm) which exhibits near-ideal subthreshold swing (SS).
{"title":"Crystalline Calcium Fluoride: A Record-Thin Insulator for Nanoscale 2D Electronics","authors":"Y. Illarionov, A. Banshchikov, T. Knobloch, D. Polyushkin, S. Wachter, V. Fedorov, S. Suturin, M. Stöger-Pollach, T. Mueller, M. Vexler, N. Sokolov, T. Grasser","doi":"10.1109/DRC50226.2020.9135160","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135160","url":null,"abstract":"Two-dimensional (2D) electronics can enable FETs down to a few nanometers. However, these devices require scalable insulators which should form high-quality interfaces with 2D channels and maintain low gate leakage currents for sub-1nm equivalent oxide thickness (EOT). Previously used amorphous oxides result in poor interfaces with 2D materials, while hBN has mediocre dielectric properties ( ε < 5, E g = 6eV) [1] . As a promising alternative, we suggest the use of the crystalline ionic insulator CaF 2 ( ε = 8.43, E g = 12.1eV) which forms van der Waals interfaces with 2D semiconductors [2] . At the moment, CaF 2 can be grown by molecular-beam epitaxy (MBE) down to a few nanometers thickness [3] and appears promising for chemical vapour deposition (CVD) [4] and atomic-layer deposition (ALD) [5] . Here we discuss our recent progress [3] , [6] , [7] on ultra-thin CaF 2 which presents a universal platform for 2D devices. In particular, we demonstrate nanoscale MoS 2 FETs with L =50-60nm and a record-thin ~ 2nm CaF 2 insulator (EOT~ 0.9nm) which exhibits near-ideal subthreshold swing (SS).","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131112969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135145
Matthew Hartensveld, Jing Zhang
The performance of Gallium Nitride (GaN) light emitting diodes (LEDs) continues to be limited due to poor hole activation in p-type GaN. In this work, the field effect is applied to an LED though integration of the p-type layer with a capacitor. Additional band bending created is used to modulate all the holes in the p-type layer, leading to enhanced external quantum efficiency (EQE). Due to the additional hole utilization, the EQE is improved by a dramatic 115% over the conventional LED. The capacitor integration additionally creates a method of voltage control for LED, instead of current control. With additional holes being utilized, the work further explores the device as a means to mitigate the efficiency droop problem of LEDs.
{"title":"Field Effect Light-Emitting Diode Integration for Enhanced Hole Utilization","authors":"Matthew Hartensveld, Jing Zhang","doi":"10.1109/DRC50226.2020.9135145","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135145","url":null,"abstract":"The performance of Gallium Nitride (GaN) light emitting diodes (LEDs) continues to be limited due to poor hole activation in p-type GaN. In this work, the field effect is applied to an LED though integration of the p-type layer with a capacitor. Additional band bending created is used to modulate all the holes in the p-type layer, leading to enhanced external quantum efficiency (EQE). Due to the additional hole utilization, the EQE is improved by a dramatic 115% over the conventional LED. The capacitor integration additionally creates a method of voltage control for LED, instead of current control. With additional holes being utilized, the work further explores the device as a means to mitigate the efficiency droop problem of LEDs.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124595180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135154
Yuan-chun Luo, Jae Hur, Panni Wang, A. Khan, Shimeng Yu
Hafnia and Zirconia oxide (HZO) based ferroelectric tunnel junction (FTJ) has attracted a lot of attention recently due to its energy-efficient, built-in-selector, multi-level-storage, and CMOS-compatible characteristics [1] – [3] . However, FTJ is limited by its low on-state current and small on/off ratio. Furthermore, their optimal programming conditions and operating principles, such as the relation between polarization and different current states, are not fully understood yet [4] [5] . Hence, in this paper, we fabricated and measured multi-state FTJ with on/off ratio > 100. Then, we built a device model, showing the relation between HZO polarization and multi-state current. With the simulated energy band diagrams, we have identified the reasons behind the two increasing rates of current as a function of voltage. Furthermore, we qualitatively explained the asymmetric programming conditions with resistor division model and energy band diagrams.
{"title":"Modeling Multi-states in Ferroelectric Tunnel Junction","authors":"Yuan-chun Luo, Jae Hur, Panni Wang, A. Khan, Shimeng Yu","doi":"10.1109/DRC50226.2020.9135154","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135154","url":null,"abstract":"Hafnia and Zirconia oxide (HZO) based ferroelectric tunnel junction (FTJ) has attracted a lot of attention recently due to its energy-efficient, built-in-selector, multi-level-storage, and CMOS-compatible characteristics [1] – [3] . However, FTJ is limited by its low on-state current and small on/off ratio. Furthermore, their optimal programming conditions and operating principles, such as the relation between polarization and different current states, are not fully understood yet [4] [5] . Hence, in this paper, we fabricated and measured multi-state FTJ with on/off ratio > 100. Then, we built a device model, showing the relation between HZO polarization and multi-state current. With the simulated energy band diagrams, we have identified the reasons behind the two increasing rates of current as a function of voltage. Furthermore, we qualitatively explained the asymmetric programming conditions with resistor division model and energy band diagrams.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115394575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135157
Chih-Pin Lin, Hao-Hua Hsu, T. Hou
Being able to precisely control the carrier polarity and conductivity plays a vital role while developing future two-dimensional (2D) transition metal dichalcogenides (TMDs)-based devices. Achieving such controllability in TMD material, however, remains challenging as a result of the strong Fermi-level pinning with contact metals [1] . MoTe 2 , one of the group-VI TMDs, has high mobility, a moderate bandgap, and the lower energy difference between polymorphic semiconducting 2H and metallic 1T’ phases, allowing versatile electrical properties. It’s known that controlling the number of chalcogen defects in TMD considerably alters its electrical characteristics [2] , [3] . In this study, we report the results of engineering Te defects in MoTe 2 by plasma treatment where (1) 2H phase is stable at a Te/Mo ratio between 1.88 and 2.13, and (2) MoTe 2 transistors can be converted from p- to n-type conduction by the defect-induced conduction band edge (CBE) lowering.
{"title":"Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering","authors":"Chih-Pin Lin, Hao-Hua Hsu, T. Hou","doi":"10.1109/DRC50226.2020.9135157","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135157","url":null,"abstract":"Being able to precisely control the carrier polarity and conductivity plays a vital role while developing future two-dimensional (2D) transition metal dichalcogenides (TMDs)-based devices. Achieving such controllability in TMD material, however, remains challenging as a result of the strong Fermi-level pinning with contact metals [1] . MoTe 2 , one of the group-VI TMDs, has high mobility, a moderate bandgap, and the lower energy difference between polymorphic semiconducting 2H and metallic 1T’ phases, allowing versatile electrical properties. It’s known that controlling the number of chalcogen defects in TMD considerably alters its electrical characteristics [2] , [3] . In this study, we report the results of engineering Te defects in MoTe 2 by plasma treatment where (1) 2H phase is stable at a Te/Mo ratio between 1.88 and 2.13, and (2) MoTe 2 transistors can be converted from p- to n-type conduction by the defect-induced conduction band edge (CBE) lowering.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127182744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135186
S. De, M. Baig, Bo-Han Qiu, D. Lu, P. Sung, F. Hsueh, Yao-Jen Lee, C. Su
This paper reports detailed analysis on switching dynamics and device variability over a wide range of temperatures for deeply scaled (40nm gate length) tri-gate ferroelectric FETs with 10nm HZO fabricated using gate first process on SOI wafers. Our experimental results manifest, 99% ferroelectric switching at room temperature and at 233K. A memory window over 5V and strong gate length dependence of memory window is observed. Highly linear and symmetric multilevel switching characteristics makes our ferroelectric FETs suitable for neuromorphic applications, as demonstrated with neural network online training simulations.
{"title":"Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K","authors":"S. De, M. Baig, Bo-Han Qiu, D. Lu, P. Sung, F. Hsueh, Yao-Jen Lee, C. Su","doi":"10.1109/DRC50226.2020.9135186","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135186","url":null,"abstract":"This paper reports detailed analysis on switching dynamics and device variability over a wide range of temperatures for deeply scaled (40nm gate length) tri-gate ferroelectric FETs with 10nm HZO fabricated using gate first process on SOI wafers. Our experimental results manifest, 99% ferroelectric switching at room temperature and at 233K. A memory window over 5V and strong gate length dependence of memory window is observed. Highly linear and symmetric multilevel switching characteristics makes our ferroelectric FETs suitable for neuromorphic applications, as demonstrated with neural network online training simulations.","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132525493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135166
Asir Intisar Khan, A. Daus, E. Pop
Flexible electronics involving applications in wearable health monitoring systems such as electronic skin [1] and Internet-of-Things (e.g. environmental or food monitoring) require integrated memory and low power consumption [2] , [3] . Although phase-change memory (PCM) has already been adopted in commercial products and its process temperature (<200°C) is compatible with flexible substrates like polyimide (PI) [4] , integration concerns remain over its relatively high reset current ( I reset ) and power ( P reset ) [5] , including on flexible substrates [6] .
{"title":"Flexible Low-Power Superlattice-Like Phase Change Memory","authors":"Asir Intisar Khan, A. Daus, E. Pop","doi":"10.1109/DRC50226.2020.9135166","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135166","url":null,"abstract":"Flexible electronics involving applications in wearable health monitoring systems such as electronic skin [1] and Internet-of-Things (e.g. environmental or food monitoring) require integrated memory and low power consumption [2] , [3] . Although phase-change memory (PCM) has already been adopted in commercial products and its process temperature (<200°C) is compatible with flexible substrates like polyimide (PI) [4] , integration concerns remain over its relatively high reset current ( I reset ) and power ( P reset ) [5] , including on flexible substrates [6] .","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131066031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/DRC50226.2020.9135152
Chenhao Ren, M. Malakoutian, Siwei Li, S. Chowdhury
An increasing number of applications in power electronics, sensor signal conditioning, and RF communication are demanded to operate beyond 200°C (e.g., engine and geothermal wellbore monitoring). These applications require integrated circuits such as mixed-signal circuits featuring analog circuitry, analog to digital converters as well as embedded microcontrollers and on-chip memories. The Si-based complementary metal-oxide-semiconductor (CMOS) technology combining a P-type MOS (PMOS) and N-type MOS (NMOS) to achieve different logic functions is not reliable for stable and sustained operations at high temperatures (>125 °C) [1] . In this work, we report the successful development of a CMOS building block using wide bandgap (WBG) technology that demonstrated operations up to >350 °C. The CMOS was developed using two wide bandgap material systems known for their high-temperature capability: diamond and gallium nitride (GaN). The "PMOS" utilizes a hole channel FET achieved using a hydrogen-terminated diamond field-effect transistor (diamond FET) and the "NMOS" is made out of an electron channel GaN high electron mobility transistor (GaN HEMT) as shown in Figure 1 .
{"title":"Hydrogen-terminated diamond FET and GaN HEMT delivering CMOS inverter operation at high-temperature","authors":"Chenhao Ren, M. Malakoutian, Siwei Li, S. Chowdhury","doi":"10.1109/DRC50226.2020.9135152","DOIUrl":"https://doi.org/10.1109/DRC50226.2020.9135152","url":null,"abstract":"An increasing number of applications in power electronics, sensor signal conditioning, and RF communication are demanded to operate beyond 200°C (e.g., engine and geothermal wellbore monitoring). These applications require integrated circuits such as mixed-signal circuits featuring analog circuitry, analog to digital converters as well as embedded microcontrollers and on-chip memories. The Si-based complementary metal-oxide-semiconductor (CMOS) technology combining a P-type MOS (PMOS) and N-type MOS (NMOS) to achieve different logic functions is not reliable for stable and sustained operations at high temperatures (>125 °C) [1] . In this work, we report the successful development of a CMOS building block using wide bandgap (WBG) technology that demonstrated operations up to >350 °C. The CMOS was developed using two wide bandgap material systems known for their high-temperature capability: diamond and gallium nitride (GaN). The \"PMOS\" utilizes a hole channel FET achieved using a hydrogen-terminated diamond field-effect transistor (diamond FET) and the \"NMOS\" is made out of an electron channel GaN high electron mobility transistor (GaN HEMT) as shown in Figure 1 .","PeriodicalId":397182,"journal":{"name":"2020 Device Research Conference (DRC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128714149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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