Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482470
Subrata Das, P. Dasgupta, P. Fiser, Sudip Ghosh, D. K. Das
Minimization of power dissipation of VLSI circuits is one of the major concerns of recent digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher clock frequencies and larger die sizes. The primary contributors to power dissipation in digital circuits include leakage power, short-circuit power and switching power. Of these, power dissipation due to the circuit switching activity constitutes the major component. As such, an effective mechanism to minimize the power loss in such cases often involves the minimization of the switching activity. In this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of the digital circuits at logic optimization stage. The proposed algorithm is empirically tested for several standard digital circuits with Synopsys EDA tool and the results obtained are quite encouraging.
{"title":"A rule-based approach for minimizing power dissipation of digital circuits","authors":"Subrata Das, P. Dasgupta, P. Fiser, Sudip Ghosh, D. K. Das","doi":"10.1109/DDECS.2016.7482470","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482470","url":null,"abstract":"Minimization of power dissipation of VLSI circuits is one of the major concerns of recent digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher clock frequencies and larger die sizes. The primary contributors to power dissipation in digital circuits include leakage power, short-circuit power and switching power. Of these, power dissipation due to the circuit switching activity constitutes the major component. As such, an effective mechanism to minimize the power loss in such cases often involves the minimization of the switching activity. In this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of the digital circuits at logic optimization stage. The proposed algorithm is empirically tested for several standard digital circuits with Synopsys EDA tool and the results obtained are quite encouraging.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114482497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482474
Marek Lipovský, Ján Svarc, E. Gramatová, P. Fiser
The paper presents a new graphical platform for automatic test patterns generation and fault simulation for digital circuits. The platform integrates two existing academic tools for test pattern generation and fault simulation: ATALANTA and HOPE. Both tools use a specific format "bench" for circuit description which is not suitable in connection to professional CAD tools. Therefore, the platform has been extended by a new translator for mapping a VHDL digital circuit model to the format "bench". The platform contains also a separate random test patterns generator linked to the fault simulator HOPE and generation of test pairs for delay faults using the transition fault model. The new automatic test pattern generation platform provides a user-friendly environment suitable for education.
{"title":"A new user-friendly ATPG platform for digital circuits","authors":"Marek Lipovský, Ján Svarc, E. Gramatová, P. Fiser","doi":"10.1109/DDECS.2016.7482474","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482474","url":null,"abstract":"The paper presents a new graphical platform for automatic test patterns generation and fault simulation for digital circuits. The platform integrates two existing academic tools for test pattern generation and fault simulation: ATALANTA and HOPE. Both tools use a specific format \"bench\" for circuit description which is not suitable in connection to professional CAD tools. Therefore, the platform has been extended by a new translator for mapping a VHDL digital circuit model to the format \"bench\". The platform contains also a separate random test patterns generator linked to the fault simulator HOPE and generation of test pairs for delay faults using the transition fault model. The new automatic test pattern generation platform provides a user-friendly environment suitable for education.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482461
S. Shirinzadeh, Mathias Soeken, R. Drechsler
Resistive switching property enables various promising applications such as design of non-volatile in-memory computing devices which has attracted high attention to Resistive Random Access Memories (RRAMs). In this work, we present a multi-objective BDD optimization approach for RRAM based logic circuit design. Dissimilar to classical BDD optimization, evaluating the cost metrics of the circuits in this case does not only depend on the number of BDD nodes but is more advanced. We have utilized a non-dominated sorting genetic algorithm for bi-objective BDD optimization with respect to the number of required RRAMs and computational steps addressing the area and delay of the resulting circuits, respectively. The algorithm also allows preference to one of the objectives if it is of higher significance. Experimental results show that the proposed multi-objective genetic algorithm achieves considerable reduction in both aforementioned criteria in comparison with an existing approach.
{"title":"Multi-objective BDD optimization for RRAM based circuit design","authors":"S. Shirinzadeh, Mathias Soeken, R. Drechsler","doi":"10.1109/DDECS.2016.7482461","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482461","url":null,"abstract":"Resistive switching property enables various promising applications such as design of non-volatile in-memory computing devices which has attracted high attention to Resistive Random Access Memories (RRAMs). In this work, we present a multi-objective BDD optimization approach for RRAM based logic circuit design. Dissimilar to classical BDD optimization, evaluating the cost metrics of the circuits in this case does not only depend on the number of BDD nodes but is more advanced. We have utilized a non-dominated sorting genetic algorithm for bi-objective BDD optimization with respect to the number of required RRAMs and computational steps addressing the area and delay of the resulting circuits, respectively. The algorithm also allows preference to one of the objectives if it is of higher significance. Experimental results show that the proposed multi-objective genetic algorithm achieves considerable reduction in both aforementioned criteria in comparison with an existing approach.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131137040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482468
E. R. Wognsen, René Rydhof Hansen, K. Larsen, P. Koch
Software Defined Radio (SDR) devices are becoming increasingly popular due to their support for mode-, standard- and application-flexibility. At the same time however, the energy consumption of such devices typically suffers from the use of reconfigurable real-time platforms which are known to be severely power hungry. In this work we therefore show how to use tools and techniques developed by the formal methods community to minimize the energy consumption of Finite Impulse Response (FIR) filters which are extensively used in SDR front-ends. We conduct experiments with four different FIR filter structures where we initially derive data flow graphs and precedence graphs using the Synchronous Data Flow (SDF) notation. Based on actual measurements on the Altera Cyclone IV FPGA, we derive power and timing estimates for addition and multiplication, including idling power consumption. We next model the FIR structures in UPPAAL CORA and employ model checking to find energy-optimal solutions in linearly priced timed automata. In conclusion we state that there are significant energy-versus-time differences between the four structures when we experiment with varying numbers of adders and multipliers. Similarly, we find that idle power becomes an important parameter when a high number of functional units are allocated.
软件定义无线电(SDR)设备由于其对模式、标准和应用灵活性的支持而变得越来越流行。然而，与此同时，这种设备的能源消耗通常受到使用可重构实时平台的影响，众所周知，这些平台非常耗电。因此，在这项工作中，我们展示了如何使用正式方法社区开发的工具和技术来最大限度地减少在SDR前端广泛使用的有限脉冲响应(FIR)滤波器的能量消耗。我们使用四种不同的FIR滤波器结构进行实验，其中我们最初使用同步数据流(SDF)表示法导出数据流图和优先图。基于Altera Cyclone IV FPGA的实际测量，我们得出了加法和乘法的功率和时间估计，包括空转功耗。接下来，我们对UPPAAL CORA中的FIR结构建模，并使用模型检查来寻找线性定价时间自动机的能量最优解。综上所述，当我们用不同数量的加法器和乘法器进行实验时，这四种结构之间存在显著的能量与时间差异。同样，我们发现当分配大量功能单元时，空闲功率成为一个重要的参数。
{"title":"Energy-aware scheduling of FIR filter structures using a timed automata model","authors":"E. R. Wognsen, René Rydhof Hansen, K. Larsen, P. Koch","doi":"10.1109/DDECS.2016.7482468","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482468","url":null,"abstract":"Software Defined Radio (SDR) devices are becoming increasingly popular due to their support for mode-, standard- and application-flexibility. At the same time however, the energy consumption of such devices typically suffers from the use of reconfigurable real-time platforms which are known to be severely power hungry. In this work we therefore show how to use tools and techniques developed by the formal methods community to minimize the energy consumption of Finite Impulse Response (FIR) filters which are extensively used in SDR front-ends. We conduct experiments with four different FIR filter structures where we initially derive data flow graphs and precedence graphs using the Synchronous Data Flow (SDF) notation. Based on actual measurements on the Altera Cyclone IV FPGA, we derive power and timing estimates for addition and multiplication, including idling power consumption. We next model the FIR structures in UPPAAL CORA and employ model checking to find energy-optimal solutions in linearly priced timed automata. In conclusion we state that there are significant energy-versus-time differences between the four structures when we experiment with varying numbers of adders and multipliers. Similarly, we find that idle power becomes an important parameter when a high number of functional units are allocated.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124289599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482466
Aymen Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, M. Reorda
Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage. The main goal of this paper is to investigate the static test compaction of a given set of functional test programs. The investigation aims at understanding and determining how to select the best functional test program candidates to obtain the smallest set having the best fault coverage. Results carried out on two different microprocessors show that a 49% reduction in test length and a 28.7% reduction in test application time can be achieved.
{"title":"An effective approach for functional test programs compaction","authors":"Aymen Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, M. Reorda","doi":"10.1109/DDECS.2016.7482466","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482466","url":null,"abstract":"Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage. The main goal of this paper is to investigate the static test compaction of a given set of functional test programs. The investigation aims at understanding and determining how to select the best functional test program candidates to obtain the smallest set having the best fault coverage. Results carried out on two different microprocessors show that a 49% reduction in test length and a 28.7% reduction in test application time can be achieved.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127596043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482476
D. Shang, Yuqing Xu, K. Gao, F. Xia, A. Yakovlev
Capacitance sensors are widely used for sensing physical parameters. Conventional capacitance to digital methods use complex analog ADC techniques which are power hungry. Recently a fully digital solution was proposed with improved power consumption. This paper describes a number of problems in that solution, analyzes these problems, and proposes a new design free of these problems. A voltage senor as an example was designed based on the proposed capacitance to digital conversion in this paper. The new method achieves the same accuracy with less than half the circuit size, and 25% and 33% savings on power and energy consumption.
{"title":"Low power voltage sensing through capacitance to digital conversion","authors":"D. Shang, Yuqing Xu, K. Gao, F. Xia, A. Yakovlev","doi":"10.1109/DDECS.2016.7482476","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482476","url":null,"abstract":"Capacitance sensors are widely used for sensing physical parameters. Conventional capacitance to digital methods use complex analog ADC techniques which are power hungry. Recently a fully digital solution was proposed with improved power consumption. This paper describes a number of problems in that solution, analyzes these problems, and proposes a new design free of these problems. A voltage senor as an example was designed based on the proposed capacitance to digital conversion in this paper. The new method achieves the same accuracy with less than half the circuit size, and 25% and 33% savings on power and energy consumption.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128080589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482473
Ondrej Kachman, M. Baláz
Modern intelligent systems are often equipped with the low-power wireless sensor or actuator devices in their structure. These devices may need firmware updates once the system is deployed. Battery powered, physically inaccessible devices require energy effective updates. The problem of energy effective updates includes the differencing algorithms that generate small delta files. This paper presents the differencing algorithm that generates the delta files for the updates without an external memory. The proposed algorithm introduces optimizations that improve its performance over the existing solutions. The generated delta files are very small and the updates do not require external flash memory.
{"title":"Optimized differencing algorithm for firmware updates of low-power devices","authors":"Ondrej Kachman, M. Baláz","doi":"10.1109/DDECS.2016.7482473","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482473","url":null,"abstract":"Modern intelligent systems are often equipped with the low-power wireless sensor or actuator devices in their structure. These devices may need firmware updates once the system is deployed. Battery powered, physically inaccessible devices require energy effective updates. The problem of energy effective updates includes the differencing algorithms that generate small delta files. This paper presents the differencing algorithm that generates the delta files for the updates without an external memory. The proposed algorithm introduces optimizations that improve its performance over the existing solutions. The generated delta files are very small and the updates do not require external flash memory.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126830045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482479
A. E. Titov, N. Prokopenko, I. Pakhomov
The article gives a theoretical analysis of the generalized structure of precision instrumentation amplifiers (IA) of modern interfaces for sensor and diagnostic systems of robots and unmanned aerial vehicles (UAV), which operate, among others, on exposure to radiation and low temperatures. The main disadvantages of classical IA are determined from the common positions and the possible ways of their clearing are presented. The new architecture of radiation-hardened differential difference op-amp (DDA) based on "folded" cascode is developed for the application in sensor interfaces and its simulation results are given, taking into account the effect of disturbing factors.
{"title":"The design features of low-temperature radiation-hardened instrumentation amplifiers and sensor interfaces","authors":"A. E. Titov, N. Prokopenko, I. Pakhomov","doi":"10.1109/DDECS.2016.7482479","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482479","url":null,"abstract":"The article gives a theoretical analysis of the generalized structure of precision instrumentation amplifiers (IA) of modern interfaces for sensor and diagnostic systems of robots and unmanned aerial vehicles (UAV), which operate, among others, on exposure to radiation and low temperatures. The main disadvantages of classical IA are determined from the common positions and the possible ways of their clearing are presented. The new architecture of radiation-hardened differential difference op-amp (DDA) based on \"folded\" cascode is developed for the application in sensor interfaces and its simulation results are given, taking into account the effect of disturbing factors.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127923235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482448
Stefan Kristofík, M. Baláz
Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive area overhead and complexity of reconfiguration logic, etc. Current promising solutions for an efficient BISR architecture design are based on reconfigurable logic blocks (RLBs). In this paper, a new automated generator of the adequate BISR reconfiguration architecture is proposed. The generation process input is a simple description of arbitrary logic core already divided into RLBs and the generated output is the synthesizable HDL description of the BISR architecture for the core.
{"title":"Built-in self-repair architecture generator for digital cores","authors":"Stefan Kristofík, M. Baláz","doi":"10.1109/DDECS.2016.7482448","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482448","url":null,"abstract":"Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive area overhead and complexity of reconfiguration logic, etc. Current promising solutions for an efficient BISR architecture design are based on reconfigurable logic blocks (RLBs). In this paper, a new automated generator of the adequate BISR reconfiguration architecture is proposed. The generation process input is a simple description of arbitrary logic core already divided into RLBs and the generated output is the synthesizable HDL description of the BISR architecture for the core.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131198005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482481
A. Voyiatzis, K. Stefanidis, P. Kitsos
The detection of malicious hardware logic (hardware Trojan) requires test patterns that succeed in exciting the malicious logic part. Testing of all possible input patterns is often prohibitively expensive. As an alternative, we explored previously the applicability of the combinatorial testing principles. In this paper, we turn our focus on the efficiency of this approach for triggering the hidden malicious logic. We present a series of experiments with Trojan designs of various activation patterns and lengths that target a cryptographic module performing AES cryptography. Our findings indicate that the available test suites succeed in triggering the malicious logic in all cases requiring only a very small number of test vectors. Thus, it is an efficient means for detecting malicious hardware logic.
{"title":"Efficient triggering of Trojan hardware logic","authors":"A. Voyiatzis, K. Stefanidis, P. Kitsos","doi":"10.1109/DDECS.2016.7482481","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482481","url":null,"abstract":"The detection of malicious hardware logic (hardware Trojan) requires test patterns that succeed in exciting the malicious logic part. Testing of all possible input patterns is often prohibitively expensive. As an alternative, we explored previously the applicability of the combinatorial testing principles. In this paper, we turn our focus on the efficiency of this approach for triggering the hidden malicious logic. We present a series of experiments with Trojan designs of various activation patterns and lengths that target a cryptographic module performing AES cryptography. Our findings indicate that the available test suites succeed in triggering the malicious logic in all cases requiring only a very small number of test vectors. Thus, it is an efficient means for detecting malicious hardware logic.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125163153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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