Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482441
Jaroslav Borecký, Martin Kohlík, H. Kubátová
This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. The utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. The method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. The experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). These results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.
{"title":"Parity Waterfall method","authors":"Jaroslav Borecký, Martin Kohlík, H. Kubátová","doi":"10.1109/DDECS.2016.7482441","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482441","url":null,"abstract":"This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. The utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. The method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. The experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). These results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124947277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482450
D. Milovančev, P. Brandl, N. Vokić, B. Goll, K. Schneider-Hornstein, H. Zimmermann
Developing paradigm in high speed communication device is heterogeneous 3D integration of electronic components - designed on standard silicon wafers - and photonics, optimized in different processes. This paper shows the advantages of 3D integration and presents the measured results of two receivers fabricated in 0.35 μm SiGe BiCMOS technology. The first is a 10 Gbit/s regulated cascode (RGC) based receiver for optical communications and the second is a 200 Mbit/s TIA for monitoring the operating point of the photonic ring modulator.
{"title":"Optical receivers in 0.35 μm BiCMOS for heterogeneous 3D integration","authors":"D. Milovančev, P. Brandl, N. Vokić, B. Goll, K. Schneider-Hornstein, H. Zimmermann","doi":"10.1109/DDECS.2016.7482450","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482450","url":null,"abstract":"Developing paradigm in high speed communication device is heterogeneous 3D integration of electronic components - designed on standard silicon wafers - and photonics, optimized in different processes. This paper shows the advantages of 3D integration and presents the measured results of two receivers fabricated in 0.35 μm SiGe BiCMOS technology. The first is a 10 Gbit/s regulated cascode (RGC) based receiver for optical communications and the second is a 200 Mbit/s TIA for monitoring the operating point of the photonic ring modulator.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"471 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482452
S. Nimara, O. Boncalo, A. Amaricai, M. Popa
Implementation of Quasi-Cyclic (QC) Low Density Parity-Check (LDPC) decoder on FPGA devices has shown great interest in both wireless communication, as well as error correction for Flash memories. This paper presents an FPGA flooded LDPC decoder which uses multiple codeword processing for efficient memory utilization. It is based on a partially parallel implementation, which relies on memory blocks for message passing between the processing units. We obtain efficient memory utilization by packing multiple messages corresponding to multiple codewords into the same Block RAM word. The increase in throughput is linear with the number of processed codewords. The proposed LDPC decoder can process up to 9 codewords in parallel, for 4-bit message quantization, or up to 12 codewords, for 3-bit message quantization, without introducing significant memory overhead.
{"title":"FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization","authors":"S. Nimara, O. Boncalo, A. Amaricai, M. Popa","doi":"10.1109/DDECS.2016.7482452","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482452","url":null,"abstract":"Implementation of Quasi-Cyclic (QC) Low Density Parity-Check (LDPC) decoder on FPGA devices has shown great interest in both wireless communication, as well as error correction for Flash memories. This paper presents an FPGA flooded LDPC decoder which uses multiple codeword processing for efficient memory utilization. It is based on a partially parallel implementation, which relies on memory blocks for message passing between the processing units. We obtain efficient memory utilization by packing multiple messages corresponding to multiple codewords into the same Block RAM word. The increase in throughput is linear with the number of processed codewords. The proposed LDPC decoder can process up to 9 codewords in parallel, for 4-bit message quantization, or up to 12 codewords, for 3-bit message quantization, without introducing significant memory overhead.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132717359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482480
T. Vanat, F. Krizek, J. Ferencei, H. Kubátová
Single event upsets (SEU) are induced by an electric charge deposited in the material of the chip. The origin of the charge can be either from outside of the chip or it can be generated inside as a result of a nuclear reaction. We have measured the cross section of SEUs in FPGA using protons (directly ionizing particles) and neutrons (indirectly ionizing particles). Used energies up to 34 MeV are in the range, where the differences in the proton's ionizing power are most significant thanks to the Bragg peak. Measurements have shown, that the direct ionization is not the dominant effect causing SEU.
{"title":"Comparing proton and neutron induced SEU cross section in FPGA","authors":"T. Vanat, F. Krizek, J. Ferencei, H. Kubátová","doi":"10.1109/DDECS.2016.7482480","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482480","url":null,"abstract":"Single event upsets (SEU) are induced by an electric charge deposited in the material of the chip. The origin of the charge can be either from outside of the chip or it can be generated inside as a result of a nuclear reaction. We have measured the cross section of SEUs in FPGA using protons (directly ionizing particles) and neutrons (indirectly ionizing particles). Used energies up to 34 MeV are in the range, where the differences in the proton's ionizing power are most significant thanks to the Bragg peak. Measurements have shown, that the direct ionization is not the dominant effect causing SEU.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121191562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482446
Firas Kaddachi, Maha Kooli, G. D. Natale, A. Bosio, Mojtaba Ebrahimi, M. Tahoori
Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact the product time-to-market. In this paper, we propose a novel fault injection technique to evaluate the reliability of a computing system running a software at early design stage where the hardware architecture is not completely defined yet. The proposed approach efficiently operates on the original source code of the software in order to inject transient faults in the data or the instructions. To be accurate and to achieve a better characterization of the system, we simulate faults occurring in the system memory units such as the data cache and the RAM by developing a system emulator. To validate our approach, we compare the simulation results to those obtained with an FPGA-based fault injector. The similarity of the results proves the accuracy of our approach to evaluate system reliability with a gain in the execution time and without requiring a fully defined hardware system.
{"title":"System-level reliability evaluation through cache-aware software-based fault injection","authors":"Firas Kaddachi, Maha Kooli, G. D. Natale, A. Bosio, Mojtaba Ebrahimi, M. Tahoori","doi":"10.1109/DDECS.2016.7482446","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482446","url":null,"abstract":"Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact the product time-to-market. In this paper, we propose a novel fault injection technique to evaluate the reliability of a computing system running a software at early design stage where the hardware architecture is not completely defined yet. The proposed approach efficiently operates on the original source code of the software in order to inject transient faults in the data or the instructions. To be accurate and to achieve a better characterization of the system, we simulate faults occurring in the system memory units such as the data cache and the RAM by developing a system emulator. To validate our approach, we compare the simulation results to those obtained with an FPGA-based fault injector. The similarity of the results proves the accuracy of our approach to evaluate system reliability with a gain in the execution time and without requiring a fully defined hardware system.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124047699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482477
Michal Sovcík, Michal Matuska, D. Arbet, V. Stopjaková
Design of variable-gain amplifier (VGA), based on fully differential operational amplifier is presented. The proposed VGA topology was verified through simulations and analysis of main circuit parameters. The VGA is designed in 0.35 μm CMOS technology using Cadence environment and BSIM3 family of models. Designed circuit works with the power supply of 3.3 V. The simulation results show that gain bandwidth (GBW) of about 12 MHz (for capacitive load of 1 pF) and the total harmonic distortion of less than 1% for input amplitude 100 mV were achieved. Implemented feedback circuit is stable according to phase margin of 68.15°.
{"title":"CMOS variable-gain amplifier for low-frequency applications","authors":"Michal Sovcík, Michal Matuska, D. Arbet, V. Stopjaková","doi":"10.1109/DDECS.2016.7482477","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482477","url":null,"abstract":"Design of variable-gain amplifier (VGA), based on fully differential operational amplifier is presented. The proposed VGA topology was verified through simulations and analysis of main circuit parameters. The VGA is designed in 0.35 μm CMOS technology using Cadence environment and BSIM3 family of models. Designed circuit works with the power supply of 3.3 V. The simulation results show that gain bandwidth (GBW) of about 12 MHz (for capacitive load of 1 pF) and the total harmonic distortion of less than 1% for input amplitude 100 mV were achieved. Implemented feedback circuit is stable according to phase margin of 68.15°.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127494607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work proposes a chaotically injected timing technique (CITT) for ring-based oscillators. The quality of clock signal affects the normal motion of the entire circuit. In many oscillators and clock generators show the performance comparison through jitters and phase noise. The injection-locked ring-based oscillators have advantages of jitters, phase noise and area cost. However, there is a contingent effect, injected spur. By adopting the CITT, the injected phase pattern can be randomized and break the periodicity of injected signal to solve the high injected spur effect. The CITT can reduce the level of phase noise by 29 dB compared to the free-run oscillator. The experiment chip of the proposed CITT is implemented by 90 nm CMOS process. The measured output frequency is 5 GHz at supply voltage of 1 V. The level of phase noise is -99 dBc at frequency offset of 1 MHz under injected frequency of 1 GHz.
{"title":"A chaotically injected timing technique for ring-based oscillators","authors":"Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang","doi":"10.1109/DDECS.2016.7482467","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482467","url":null,"abstract":"This work proposes a chaotically injected timing technique (CITT) for ring-based oscillators. The quality of clock signal affects the normal motion of the entire circuit. In many oscillators and clock generators show the performance comparison through jitters and phase noise. The injection-locked ring-based oscillators have advantages of jitters, phase noise and area cost. However, there is a contingent effect, injected spur. By adopting the CITT, the injected phase pattern can be randomized and break the periodicity of injected signal to solve the high injected spur effect. The CITT can reduce the level of phase noise by 29 dB compared to the free-run oscillator. The experiment chip of the proposed CITT is implemented by 90 nm CMOS process. The measured output frequency is 5 GHz at supply voltage of 1 V. The level of phase noise is -99 dBc at frequency offset of 1 MHz under injected frequency of 1 GHz.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127638110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482444
Muhammad Waqas Chaudhary, A. Heinig
In recent years, 2.5D integration of ICs on Interposer is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this needs either a very high number of slow channels or numerous high speed channels. To find an optimum number and speed of interposer channels is an important task. In conventional PCB data communication systems, very high speed serial data transmission circuits are used which take a lot of area and power. While in 2.5D systems, area-power are strict constraints and the interposer channel is drastically different from PCB channel in terms of its electrical properties. To enable high bandwidth chip-to-chip interposer communication with low area-power requirements, it is mandatory to co-design the interposer channel and IO circuit. To address the issue, this paper discusses the electrical properties of 2.5D channel segments along with a co-design methodology targeting optimum area-power cost for maximum bandwidth current mode logic differential driver.
{"title":"Co-design of CML IO and Interposer channel for low area and power signaling","authors":"Muhammad Waqas Chaudhary, A. Heinig","doi":"10.1109/DDECS.2016.7482444","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482444","url":null,"abstract":"In recent years, 2.5D integration of ICs on Interposer is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this needs either a very high number of slow channels or numerous high speed channels. To find an optimum number and speed of interposer channels is an important task. In conventional PCB data communication systems, very high speed serial data transmission circuits are used which take a lot of area and power. While in 2.5D systems, area-power are strict constraints and the interposer channel is drastically different from PCB channel in terms of its electrical properties. To enable high bandwidth chip-to-chip interposer communication with low area-power requirements, it is mandatory to co-design the interposer channel and IO circuit. To address the issue, this paper discusses the electrical properties of 2.5D channel segments along with a co-design methodology targeting optimum area-power cost for maximum bandwidth current mode logic differential driver.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123759648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482463
A. Simevski, K. Schleisiek, V. Petrovic, N. Beller, Patryk Skoncej, G. Schoof, M. Krstic
The significance of low cost small satellites used for scientific research and practical applications continuously grows. Current satellite OBC (On-Board Computer) microcontrollers have integrated various digital peripherals and interfaces. However, a common Real Time Unit (RTU) requires interfacing to simple analogue sensors and actuators. Here we present a novel RTU microcontroller which includes a 13-bit Analog-to-Digital Converter (ADC) and two 12-bit Digital-to-Analog Converters (DAC). Furthermore, it includes a 32KB internal SRAM memory and a 32 KB internal flash memory. This enables an easy construction of a software-controlled embedded system which is easily interfaced to existing hardware sensors and actuators. The chip is produced in IHP 250 nm technology using radiation hardening by design. The operating frequency is 80 MHz. A 3-bit clock divider, as well as clock- and power-gating are used for reducing power consumption which is measured to be 0,8 W in operation.
{"title":"Implementation of a real time unit for satellite applications","authors":"A. Simevski, K. Schleisiek, V. Petrovic, N. Beller, Patryk Skoncej, G. Schoof, M. Krstic","doi":"10.1109/DDECS.2016.7482463","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482463","url":null,"abstract":"The significance of low cost small satellites used for scientific research and practical applications continuously grows. Current satellite OBC (On-Board Computer) microcontrollers have integrated various digital peripherals and interfaces. However, a common Real Time Unit (RTU) requires interfacing to simple analogue sensors and actuators. Here we present a novel RTU microcontroller which includes a 13-bit Analog-to-Digital Converter (ADC) and two 12-bit Digital-to-Analog Converters (DAC). Furthermore, it includes a 32KB internal SRAM memory and a 32 KB internal flash memory. This enables an easy construction of a software-controlled embedded system which is easily interfaced to existing hardware sensors and actuators. The chip is produced in IHP 250 nm technology using radiation hardening by design. The operating frequency is 80 MHz. A 3-bit clock divider, as well as clock- and power-gating are used for reducing power consumption which is measured to be 0,8 W in operation.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131304850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482447
A. Koczor, Lukasz Matoga, P. Penkala, A. Pawlak
The paper presents a scalable architecture for fast emulation of Systems-on-Chip. It is implemented on a dedicated modular FPGA-based hardware platform. This verification eco-system presents a new approach to improve efficiency of the verification process through hardware-based acceleration of tests. The system consists of dedicated hardware modules and third-party; easy-to-get evaluation boards to provide an affordable solution for SMEs with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, and connectors, the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. It provides a debug capability which enables quick identification and elimination of implementation bugs. The paper also reports on the use of the emulation environment in FPGA-in-the-Loop simulation. This solution may be applied to a broad range of applications.
{"title":"Verification approach based on emulation technology","authors":"A. Koczor, Lukasz Matoga, P. Penkala, A. Pawlak","doi":"10.1109/DDECS.2016.7482447","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482447","url":null,"abstract":"The paper presents a scalable architecture for fast emulation of Systems-on-Chip. It is implemented on a dedicated modular FPGA-based hardware platform. This verification eco-system presents a new approach to improve efficiency of the verification process through hardware-based acceleration of tests. The system consists of dedicated hardware modules and third-party; easy-to-get evaluation boards to provide an affordable solution for SMEs with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, and connectors, the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. It provides a debug capability which enables quick identification and elimination of implementation bugs. The paper also reports on the use of the emulation environment in FPGA-in-the-Loop simulation. This solution may be applied to a broad range of applications.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130709121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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