Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482457
Matej Rakus, V. Stopjaková, D. Arbet
In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage of a standard MOS device. Bulk-driven current mirror topologies were compared to their gate-driven equivalents in terms of main properties and output characteristics. The achieved results prove that the bulk-driven design technique is very promising towards ultra low-voltage analog ICs.
{"title":"Comparison of gate-driven and bulk-driven current mirror topologies","authors":"Matej Rakus, V. Stopjaková, D. Arbet","doi":"10.1109/DDECS.2016.7482457","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482457","url":null,"abstract":"In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage of a standard MOS device. Bulk-driven current mirror topologies were compared to their gate-driven equivalents in terms of main properties and output characteristics. The achieved results prove that the bulk-driven design technique is very promising towards ultra low-voltage analog ICs.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124629671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482451
Paweł Narczyk, Krzysztof Siwiec, W. Pleskacz
An analog front-end, with a new temperature calibration method, for an accurate temperature measurement of a human body has been presented. The discussed AFE consists of a current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and on-chip temperature calibration resistor. Human body temperature can be measured in the range from +25 °C to +45 °C at the operating temperature of an IC in the range from -40 °C to +125 °C with 0.1 °C precision. The presented analog front-end consumes no more than 180 uW and was designed in UMC CMOS 130 nm technology.
{"title":"Precision human body temperature measurement based on thermistor sensor","authors":"Paweł Narczyk, Krzysztof Siwiec, W. Pleskacz","doi":"10.1109/DDECS.2016.7482451","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482451","url":null,"abstract":"An analog front-end, with a new temperature calibration method, for an accurate temperature measurement of a human body has been presented. The discussed AFE consists of a current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and on-chip temperature calibration resistor. Human body temperature can be measured in the range from +25 °C to +45 °C at the operating temperature of an IC in the range from -40 °C to +125 °C with 0.1 °C precision. The presented analog front-end consumes no more than 180 uW and was designed in UMC CMOS 130 nm technology.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122777809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482462
O. Schrape, A. Koczor, P. Penkala, V. Petrovic, M. Krstic
One of the main reasons why Synthetic Aperture Radar (SAR) is an attractive solution for earth surface screening applications is its reliability independent on the weather conditions. This paper presents the implementation details of digital beamforming baseband core processor for such a SAR system. The processor chip is part of a distributed beamforming network (DBFN) of 16 baseband processors where each one processes data obtained from four 210MSPS ADC cores. Due to requirements related to space environment, the baseband is implemented in radiation-tolerant manner in order to temper single event effects (SEE). Instead of full-chip protection, the baseband processor uses only partially radhard flip-flops. This trade-off saves 25.87 % of silicon area based on gate-level synthesis results. A prototype is produced in a low-cost variant of a 0.25 μm BiCMOS process. First measurement results show an average operating current of 445.49 mA at a clock speed of 210 MHz and a 2.5 V power supply.
{"title":"Implementation of DBFN processor for Synthetic Aperture Radar application","authors":"O. Schrape, A. Koczor, P. Penkala, V. Petrovic, M. Krstic","doi":"10.1109/DDECS.2016.7482462","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482462","url":null,"abstract":"One of the main reasons why Synthetic Aperture Radar (SAR) is an attractive solution for earth surface screening applications is its reliability independent on the weather conditions. This paper presents the implementation details of digital beamforming baseband core processor for such a SAR system. The processor chip is part of a distributed beamforming network (DBFN) of 16 baseband processors where each one processes data obtained from four 210MSPS ADC cores. Due to requirements related to space environment, the baseband is implemented in radiation-tolerant manner in order to temper single event effects (SEE). Instead of full-chip protection, the baseband processor uses only partially radhard flip-flops. This trade-off saves 25.87 % of silicon area based on gate-level synthesis results. A prototype is produced in a low-cost variant of a 0.25 μm BiCMOS process. First measurement results show an average operating current of 445.49 mA at a clock speed of 210 MHz and a 2.5 V power supply.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129018033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482459
Aitzan Sari, M. Psarakis
Soft processors in SRAM-based FPGAs are gaining acceptance as enabling technology for building embedded systems in several market domains, even for critical applications such as space, transportation and medical devices. However, due to the high vulnerability of SRAM-based FPGAs to single-event upsets (SEUs), which is expected to be aggravated in the future, as FPGA devices are moving aggressively to the nanometer regime, the hardening of soft processors against soft errors will become a major design issue especially for critical applications. Most SEU mitigation approaches proposed in the past are based on the triplication or duplication techniques, thus imposing significant area and performance overheads. A more detailed analysis of the soft error sensitivity of FPGA soft processor and their faulty behavior will enable the development of efficient, low-cost hardening techniques. To this end, we present a fault injection platform based on an open-source CAD framework (RapidSmith) for the analysis of soft error effects in Xilinx FPGA soft processors. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. An on-chip microcontroller is used to inject and correct soft errors in the configuration memory and monitor target processor behavior. It includes a custom peripheral to monitor and record specific processor signals (e.g. exception signals, performance counters) which may manifest the effects of soft errors. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor. The novelty of the framework is it's availability as open-source fault-injection tool designed to target soft processors and the introduction of fault identification by using performance counter.
{"title":"A fault injection platform for the analysis of soft error effects in FPGA soft processors","authors":"Aitzan Sari, M. Psarakis","doi":"10.1109/DDECS.2016.7482459","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482459","url":null,"abstract":"Soft processors in SRAM-based FPGAs are gaining acceptance as enabling technology for building embedded systems in several market domains, even for critical applications such as space, transportation and medical devices. However, due to the high vulnerability of SRAM-based FPGAs to single-event upsets (SEUs), which is expected to be aggravated in the future, as FPGA devices are moving aggressively to the nanometer regime, the hardening of soft processors against soft errors will become a major design issue especially for critical applications. Most SEU mitigation approaches proposed in the past are based on the triplication or duplication techniques, thus imposing significant area and performance overheads. A more detailed analysis of the soft error sensitivity of FPGA soft processor and their faulty behavior will enable the development of efficient, low-cost hardening techniques. To this end, we present a fault injection platform based on an open-source CAD framework (RapidSmith) for the analysis of soft error effects in Xilinx FPGA soft processors. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. An on-chip microcontroller is used to inject and correct soft errors in the configuration memory and monitor target processor behavior. It includes a custom peripheral to monitor and record specific processor signals (e.g. exception signals, performance counters) which may manifest the effects of soft errors. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor. The novelty of the framework is it's availability as open-source fault-injection tool designed to target soft processors and the introduction of fault identification by using performance counter.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121342420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482439
D. Arbet, M. Kovác, L. Nagy, V. Stopjaková, J. Brenkus
In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.
{"title":"Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology","authors":"D. Arbet, M. Kovác, L. Nagy, V. Stopjaková, J. Brenkus","doi":"10.1109/DDECS.2016.7482439","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482439","url":null,"abstract":"In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129413288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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