With the advent of portable and high-density microelectronic devices, the power dissipation of integrated circuits has become a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. As an introduction to the other papers in this session, this paper gives a tutorial presentation of the issues involved in power estimation.
{"title":"Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits","authors":"F. Najm","doi":"10.1145/217474.217598","DOIUrl":"https://doi.org/10.1145/217474.217598","url":null,"abstract":"With the advent of portable and high-density microelectronic devices, the power dissipation of integrated circuits has become a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. As an introduction to the other papers in this session, this paper gives a tutorial presentation of the issues involved in power estimation.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126949939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel approach to deriving area and delay estimates for high level synthesis using machine learning techniques to model layout tools. This approach captures the relationships between general design features (e.g., topology, connectivity, common input, and common output) and layout concepts (e.g., relative placement). Experimentation illustrates the effectiveness of this approach for a variety of real-world designs.
{"title":"Deriving Efficient Area and Delay Estimates by Modeling Layout Tools","authors":"D. Gelosh, D. Setliff","doi":"10.1145/217474.217562","DOIUrl":"https://doi.org/10.1145/217474.217562","url":null,"abstract":"This paper presents a novel approach to deriving area and delay estimates for high level synthesis using machine learning techniques to model layout tools. This approach captures the relationships between general design features (e.g., topology, connectivity, common input, and common output) and layout concepts (e.g., relative placement). Experimentation illustrates the effectiveness of this approach for a variety of real-world designs.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128419474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method for the efficient computation of accurate reduced-order models of large linear circuits is described. The method, called MPVL, employs a novel block Lanczos algorithm to compute matrix Padé approximations of matrix-valued network transfer functions. The reduced-order models, computed to the required level of accuracy, are used to speed up the analysis of circuits containing large linear blocks. The linear blocks are replaced by their reduced-order models, and the resulting smaller circuit can be analyzed with general-purpose simulators, with significant savings in simulation time and, practically, no loss of accuracy.
{"title":"Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm","authors":"P. Feldmann, R. Freund","doi":"10.1145/217474.217573","DOIUrl":"https://doi.org/10.1145/217474.217573","url":null,"abstract":"A method for the efficient computation of accurate reduced-order models of large linear circuits is described. The method, called MPVL, employs a novel block Lanczos algorithm to compute matrix Padé approximations of matrix-valued network transfer functions. The reduced-order models, computed to the required level of accuracy, are used to speed up the analysis of circuits containing large linear blocks. The linear blocks are replaced by their reduced-order models, and the resulting smaller circuit can be analyzed with general-purpose simulators, with significant savings in simulation time and, practically, no loss of accuracy.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade-off between flexibility and cost. However, existing code generation methods are hampered by the combination of tight timing and resource constraints, imposed by the throughput requirements of DSP algorithms together with a fixed core architecture. In this paper, we present a method to model resource and instruction set conflicts uniformly and statically before scheduling. With the model we exploit the combination of all possible constraints, instead of being hampered by them. The approach results in an exact and run time efficient method to solve the instruction scheduling problem, which is illustrated by real life examples.
{"title":"Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores","authors":"A. Timmer, M. Strik, J. V. Meerbergen, J. Jess","doi":"10.1145/217474.217595","DOIUrl":"https://doi.org/10.1145/217474.217595","url":null,"abstract":"Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade-off between flexibility and cost. However, existing code generation methods are hampered by the combination of tight timing and resource constraints, imposed by the throughput requirements of DSP algorithms together with a fixed core architecture. In this paper, we present a method to model resource and instruction set conflicts uniformly and statically before scheduling. With the model we exploit the combination of all possible constraints, instead of being hampered by them. The approach results in an exact and run time efficient method to solve the instruction scheduling problem, which is illustrated by real life examples.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127853052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aharon Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, Moshe Molcho, G. Shurek
A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon.
{"title":"Test Program Generation for Functional Verification of PowePC Processors in IBM","authors":"Aharon Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, Moshe Molcho, G. Shurek","doi":"10.1145/217474.217542","DOIUrl":"https://doi.org/10.1145/217474.217542","url":null,"abstract":"A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126216818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present theory and a novel, implicit algorithm for functional disjoint decomposition of multiple-output functions. While a Boolean function usually has a huge number of decomposition functions, we show that not all of them are useful for multiple-output decomposition. We therefore introduce the concept of preferable decomposition functions, which are sufficient for optimal multiple-output decomposition. We describe how to implicitly compute all preferable decomposition functions of a single-output, and how to identify all common preferable decomposition functions of a multiple-output function. Due to the implicit computation in all steps, the algorithm is very efficient. Applied to FPGA synthesis, the method combines the typically separated steps of common subfunction extraction and technology mapping. Experimental results show significant reductions in area.
{"title":"Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm","authors":"B. Wurth, K. Eckl, K. Antreich","doi":"10.1145/217474.217506","DOIUrl":"https://doi.org/10.1145/217474.217506","url":null,"abstract":"We present theory and a novel, implicit algorithm for functional disjoint decomposition of multiple-output functions. While a Boolean function usually has a huge number of decomposition functions, we show that not all of them are useful for multiple-output decomposition. We therefore introduce the concept of preferable decomposition functions, which are sufficient for optimal multiple-output decomposition. We describe how to implicitly compute all preferable decomposition functions of a single-output, and how to identify all common preferable decomposition functions of a multiple-output function. Due to the implicit computation in all steps, the algorithm is very efficient. Applied to FPGA synthesis, the method combines the typically separated steps of common subfunction extraction and technology mapping. Experimental results show significant reductions in area.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128206720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes algorithms for automatic layout synthesis of leaf cells in 1-d and in a new 1-1/2-d layout style, useful for non-dual circuit styles. The graph theory based algorithms use concepts set forth by Euler and Hamilton to achieve two tasks. The transistor placement algorithm uses the Euler's theorem, while the placement of the groups of the transistors is achieved by using Hamiltonian graphs. Results show that the algorithms produce extremely competent layouts when compared to other algorithms in the literature and manual layouts.
{"title":"Automatic Layout Synthesis of Leaf Cells","authors":"S. Rekhi, J. D. Trotter, D. Linder","doi":"10.1145/217474.217540","DOIUrl":"https://doi.org/10.1145/217474.217540","url":null,"abstract":"This paper describes algorithms for automatic layout synthesis of leaf cells in 1-d and in a new 1-1/2-d layout style, useful for non-dual circuit styles. The graph theory based algorithms use concepts set forth by Euler and Hamilton to achieve two tasks. The transistor placement algorithm uses the Euler's theorem, while the placement of the groups of the transistors is achieved by using Hamiltonian graphs. Results show that the algorithms produce extremely competent layouts when compared to other algorithms in the literature and manual layouts.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130170349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit. The synthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for synthesis of testable circuits. Experimental results demonstrate reductions in the number of gates and paths and increased path delay fault testability. The random pattern testability for stuck-at faults remains unchanged.
{"title":"On Synthesis-for-Testability of Combinational Logic Circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1145/217474.217518","DOIUrl":"https://doi.org/10.1145/217474.217518","url":null,"abstract":"We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit. The synthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for synthesis of testable circuits. Experimental results demonstrate reductions in the number of gates and paths and increased path delay fault testability. The random pattern testability for stuck-at faults remains unchanged.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132853708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of design for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is desirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications.
{"title":"An Algorithm for Incremental Timing Analysis","authors":"Jin-fuw Lee, D. Tang","doi":"10.1145/217474.217613","DOIUrl":"https://doi.org/10.1145/217474.217613","url":null,"abstract":"In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of design for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is desirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133201648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.
{"title":"Residue BDD and Its Application to the Verification of Arithmetic Circuits","authors":"S. Kimura","doi":"10.1145/217474.217584","DOIUrl":"https://doi.org/10.1145/217474.217584","url":null,"abstract":"The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"10556 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131092396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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