Local don't cares of an internal node expressed in terms of its immediate inputs are usually of interest. One can directly apply any two-level minimizer on the on-set and the local don't cares set to simplify an internal node. In this paper, we propose a memory efficient technique to calculate local don't cares of internal nodes in a combinational circuit. Our technique of calculating local don't cares makes use of automatic test pattern generation (ATPG) approach which allows us to identify quickly whether a cube in the local space is a don't care or not. Unlike other approaches which construct an intermediate form of don't cares in terms of the primary inputs, our technique directly computes the don't care cubes in the local space. This gives us a significant advantage over the previous approaches in memory usage. Experimental results on MCNC benchmarks are very encouraging.
本地不关心用直接输入表示的内部节点通常是感兴趣的。可以直接在on-set和local not care set上应用任何两级最小化器来简化内部节点。在本文中，我们提出了一种在组合电路中计算局部不关心内部节点的高效存储技术。我们计算局部无关的技术使用了自动测试模式生成(ATPG)方法，该方法允许我们快速识别局部空间中的立方体是否为无关。不像其他方法，根据主要输入构建一个中间形式的“不在乎”，我们的技术直接计算局部空间中的“不在乎”立方体。这使我们在内存使用方面比以前的方法有显著的优势。MCNC基准的实验结果非常令人鼓舞。
{"title":"An Efficient Algorithm for Local Don't Care Sets Calculation","authors":"Malgorzata Marek-Sadowska Shih-Chieh Chang","doi":"10.1109/dac.1995.250047","DOIUrl":"https://doi.org/10.1109/dac.1995.250047","url":null,"abstract":"Local don't cares of an internal node expressed in terms of its immediate inputs are usually of interest. One can directly apply any two-level minimizer on the on-set and the local don't cares set to simplify an internal node. In this paper, we propose a memory efficient technique to calculate local don't cares of internal nodes in a combinational circuit. Our technique of calculating local don't cares makes use of automatic test pattern generation (ATPG) approach which allows us to identify quickly whether a cube in the local space is a don't care or not. Unlike other approaches which construct an intermediate form of don't cares in terms of the primary inputs, our technique directly computes the don't care cubes in the local space. This gives us a significant advantage over the previous approaches in memory usage. Experimental results on MCNC benchmarks are very encouraging.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114175216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ian Perryman Janick Bergeron Stacy Nichols Mario Dufre Allan Silburt
This paper describes a functional hardware verification methodology for ASIC intensive products. It spans the ASIC, board, and system level, enabling simulation of the design concurrent with ASIC and board development. The simulation strategy relies on rapid development of behavioural models of ASICs to enable work to proceed in parallel and to achieve the necessary simulation efficiency. The results from a project on which the methodology was used are presented. The process provided early visibility of over 200 issues in the system of which 32 were critical to the successful conformance and timely completion of the project.
{"title":"Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation","authors":"Ian Perryman Janick Bergeron Stacy Nichols Mario Dufre Allan Silburt","doi":"10.1109/dac.1995.250003","DOIUrl":"https://doi.org/10.1109/dac.1995.250003","url":null,"abstract":"This paper describes a functional hardware verification methodology for ASIC intensive products. It spans the ASIC, board, and system level, enabling simulation of the design concurrent with ASIC and board development. The simulation strategy relies on rapid development of behavioural models of ASICs to enable work to proceed in parallel and to achieve the necessary simulation efficiency. The results from a project on which the methodology was used are presented. The process provided early visibility of over 200 issues in the system of which 32 were critical to the successful conformance and timely completion of the project.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"36 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113934255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order to exploit all the potential of the fabrication process. In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value. It is thus possible to select the desired level of confidence for the worst-case evaluation of digital IC designs with good accuracy. The results of the Assigned Probability Technique (APT) are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method.
{"title":"An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard cells","authors":"A. Fabbro, B. Franzini, L. Croce, C. Guardiani","doi":"10.1145/217474.217614","DOIUrl":"https://doi.org/10.1145/217474.217614","url":null,"abstract":"The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order to exploit all the potential of the fabrication process. In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value. It is thus possible to select the desired level of confidence for the worst-case evaluation of digital IC designs with good accuracy. The results of the Assigned Probability Technique (APT) are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117239433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Chandna, C. Kibler, Richard B. Brown, M. Roberts, K. Sakallah
This paper describes a RAM compiler for generating and characterizing highly manufacturable optimized SRAMs using GaAs E/D MESFET technology. The compiler uses a constraint-driven design flow to achieve process tolerant RAMs. This compiler was built using a flexible design framework that can be easily adapted to optimize and characterize memories in different MESFET processes.
{"title":"The Aurora RAM Compiler","authors":"A. Chandna, C. Kibler, Richard B. Brown, M. Roberts, K. Sakallah","doi":"10.1145/217474.217539","DOIUrl":"https://doi.org/10.1145/217474.217539","url":null,"abstract":"This paper describes a RAM compiler for generating and characterizing highly manufacturable optimized SRAMs using GaAs E/D MESFET technology. The compiler uses a constraint-driven design flow to achieve process tolerant RAMs. This compiler was built using a flexible design framework that can be easily adapted to optimize and characterize memories in different MESFET processes.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115765756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Model checking is an automatic technique for verifying sequential circuit designs and protocols. An efficient search procedure is used to determine whethe or not the specification is satisfied. If it is not satisfied, our technique will produce a counter-example execution trace that shows the cause of the problem. We describe an efficient algorithm to produce counter-examples and witnesses for symbolic model checking algorithms. This algorithm is used in the SMV model checker and works quite well in practice. We also discuss how to extend our technique to more complicated specifications.
{"title":"Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking","authors":"O. G. K. M. X. Z. E.M. Clarke","doi":"10.21236/ada288583","DOIUrl":"https://doi.org/10.21236/ada288583","url":null,"abstract":"Model checking is an automatic technique for verifying sequential circuit designs and protocols. An efficient search procedure is used to determine whethe or not the specification is satisfied. If it is not satisfied, our technique will produce a counter-example execution trace that shows the cause of the problem. We describe an efficient algorithm to produce counter-examples and witnesses for symbolic model checking algorithms. This algorithm is used in the SMV model checker and works quite well in practice. We also discuss how to extend our technique to more complicated specifications.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"02 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124478146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose topology design of power distribution nets using a novel method for capturing the temporal characteristics of sink currents - the current compatibility graph. This graph carries information necessary for net area optimization. We propose a new algorithm for simultaneous topology design and wire sizing that can handle large designs. Our techniques result in significant area improvements on benchmark instances.
{"title":"Power Distribution Topology Design","authors":"Malgorzata Marek-Sadowska Ashok Vittal","doi":"10.1109/dac.1995.249999","DOIUrl":"https://doi.org/10.1109/dac.1995.249999","url":null,"abstract":"We propose topology design of power distribution nets using a novel method for capturing the temporal characteristics of sink currents - the current compatibility graph. This graph carries information necessary for net area optimization. We propose a new algorithm for simultaneous topology design and wire sizing that can handle large designs. Our techniques result in significant area improvements on benchmark instances.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121664511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Since the first papers on asymptotic waveform evaluation (AWE), reduced order models have become standard for improving interconnect simulation efficiency, and very recent work has demonstrated that bi-orthogonalization algorithms can be used to robustly generate AWE-style macromodels. In this paper we describe using block Arnoldi-based orthogonalization methods to generate reduced order models from FastHenry, a multipole-accelerated three dimensional inductance extraction program. Examples are analyzed to demonstrate the efficiency and accuracy of the block Arnoldi algorithm.
{"title":"Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances associated with 3-D Interconnect Structures","authors":"L. M. Silveira, M. Kamon, Jacob K. White","doi":"10.1145/217474.217558","DOIUrl":"https://doi.org/10.1145/217474.217558","url":null,"abstract":"Since the first papers on asymptotic waveform evaluation (AWE), reduced order models have become standard for improving interconnect simulation efficiency, and very recent work has demonstrated that bi-orthogonalization algorithms can be used to robustly generate AWE-style macromodels. In this paper we describe using block Arnoldi-based orthogonalization methods to generate reduced order models from FastHenry, a multipole-accelerated three dimensional inductance extraction program. Examples are analyzed to demonstrate the efficiency and accuracy of the block Arnoldi algorithm.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122777553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper discusses issues related to the application of information modelling to the field of Electronic CAD, using VHDL as the basis for discussion. It is shown that an information model of VHDL provides a coherent and uniform description of the VHDL objects at different levels of the language and of the transformations that interrelate these levels. In addition, it captures the time-dependent aspects of the language. Hence, a hierarchy of VHDL information models can exist which encompasses the range from abstraction to detail and can help support CAD applications in a direct manner.
{"title":"Information Models of VHDL","authors":"C. Giumale, H. J. Kahn","doi":"10.1145/217474.217610","DOIUrl":"https://doi.org/10.1145/217474.217610","url":null,"abstract":"The paper discusses issues related to the application of information modelling to the field of Electronic CAD, using VHDL as the basis for discussion. It is shown that an information model of VHDL provides a coherent and uniform description of the VHDL objects at different levels of the language and of the transformations that interrelate these levels. In addition, it captures the time-dependent aspects of the language. Hence, a hierarchy of VHDL information models can exist which encompasses the range from abstraction to detail and can help support CAD applications in a direct manner.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"40 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129808145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution method. We show that this method is inefficient when used with a scanline ordering of the elements. As an improvement, we introduce the Delayed Frontal Solution algorithm, which allows us to replace the scanline ordering by the minimumdegree ordering. Thus, extraction times are reduced with more than one order of magnitude at a small cost of extra memory.
{"title":"Delayed Frontal Solution for Finite-Element based Resistance Extraction","authors":"N. V. D. Meijs, A. V. Genderen","doi":"10.1145/217474.217541","DOIUrl":"https://doi.org/10.1145/217474.217541","url":null,"abstract":"To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution method. We show that this method is inefficient when used with a scanline ordering of the elements. As an improvement, we introduce the Delayed Frontal Solution algorithm, which allows us to replace the scanline ordering by the minimumdegree ordering. Thus, extraction times are reduced with more than one order of magnitude at a small cost of extra memory.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129952171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the idea of "behavioral templates" in scheduling. A behavioral template locks several operations into a relative schedule with respect to one another. This simple construct proves powerful in addressing: (1) timing constraints, (2) sequential operation modeling, (3) pre-chaining of certain operations, and (4) hierarchical scheduling. We present design examples from industry to demonstrate the importance of these issues in scheduling.
{"title":"Scheduling Using Behavioral Templates","authors":"David Knapp Ron Miller Don MacMillen Tai Ly","doi":"10.1109/dac.1995.250072","DOIUrl":"https://doi.org/10.1109/dac.1995.250072","url":null,"abstract":"This paper presents the idea of \"behavioral templates\" in scheduling. A behavioral template locks several operations into a relative schedule with respect to one another. This simple construct proves powerful in addressing: (1) timing constraints, (2) sequential operation modeling, (3) pre-chaining of certain operations, and (4) hierarchical scheduling. We present design examples from industry to demonstrate the importance of these issues in scheduling.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125234645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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