This paper reviews the step-response of the semi-infinite distributed RC line and focuses mainly on the step-response of a finite-length RC line with a capacitive load termination, which is the most common model for a wire inside the present day integrated CMOS chips. In particular, we obtain the values of some of the common threshold-crossing times at the output of such a line and show that even the simplest first order lumped II-approximation to the finite-length RC line terminated with a capacitive load is good enough for obtaining the 50% and 63.2% threshold-crossing times of the step-response. Higher order lumped approximations are necessary for more accurate predictions of the 10% and 90% threshold-crossing times.
{"title":"Delay Analysis of the Distributed RC Line","authors":"V. Rao","doi":"10.1145/217474.217557","DOIUrl":"https://doi.org/10.1145/217474.217557","url":null,"abstract":"This paper reviews the step-response of the semi-infinite distributed RC line and focuses mainly on the step-response of a finite-length RC line with a capacitive load termination, which is the most common model for a wire inside the present day integrated CMOS chips. In particular, we obtain the values of some of the common threshold-crossing times at the output of such a line and show that even the simplest first order lumped II-approximation to the finite-length RC line terminated with a capacitive load is good enough for obtaining the 50% and 63.2% threshold-crossing times of the step-response. Higher order lumped approximations are necessary for more accurate predictions of the 10% and 90% threshold-crossing times.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121019315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the activities at the primary outputs and all internal nodes are estimated. For the first time, the relationship between logic and probabilistic domains is investigated and two new concepts - conditional independence and isotropy of signals - are brought into attention. Based on them, a sufficient condition for analyzing complex dependencies is given. In the most general case, the conditional independence problem has been shown to be NP-complete and thus appropriate heuristics are presented to estimate switching activity. Detailed experiments demonstrate the accuracy and efficiency of the method. The results reported here are useful in low power design.
{"title":"Efficient Power Estimation for Highly Correlated Input Streams","authors":"R. Marculescu, Diana Marculescu, Massoud Pedram","doi":"10.1145/217474.217601","DOIUrl":"https://doi.org/10.1145/217474.217601","url":null,"abstract":"Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the activities at the primary outputs and all internal nodes are estimated. For the first time, the relationship between logic and probabilistic domains is investigated and two new concepts - conditional independence and isotropy of signals - are brought into attention. Based on them, a sufficient condition for analyzing complex dependencies is given. In the most general case, the conditional independence problem has been shown to be NP-complete and thus appropriate heuristics are presented to estimate switching activity. Detailed experiments demonstrate the accuracy and efficiency of the method. The results reported here are useful in low power design.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121019932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Numerous formal verification systems have been proposed and developed for Finite Sate Machine based control units (notably SMV[19] as well as others). However, most research on the equivalence checking of datapaths is still confined to the bit-level. Formal verification of arithmetic expressions and synthesized datapaths, especially considering finite word-length computation, has not been addressed. Thus formal verification techniques have been prohibited from more extensive applications in numerical and Digital Signal Processing. In this paper a formal system, called Conditional Term Rewriting on Attribute Syntax Trees (ConTRAST) is developed and demonstrated for verifying the equivalence between two differently synthesized datapaths. This result arises from a sophisticated integration of attribute grammars, which provide expressive data structures for syntactic and semantic information about designed datapaths, and term rewriting systems, which transform functionally equivalent datapaths into the same canonical form. The equivalence relation is defined as a congruence closure in the rewriting system, which can be generated from arbitrary axioms, such as associativity, commutativity, etc. in a certain algebraic system. Furthermore, the effect of finite word-lengths and their associated arithmetic precision are also considered in the definition of equivalence classes. As a particular application of ConTRAST, a formal verification system is designed to check equivalence under precision constraints. The results of initial DSP synthesis experiments are displayed, where two differently implemented IIR filters in direct II and cascaded architectures are automatically compared under given precision constraints.
{"title":"Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions","authors":"Zheng Zhou, W. Burleson","doi":"10.1145/217474.217585","DOIUrl":"https://doi.org/10.1145/217474.217585","url":null,"abstract":"Numerous formal verification systems have been proposed and developed for Finite Sate Machine based control units (notably SMV[19] as well as others). However, most research on the equivalence checking of datapaths is still confined to the bit-level. Formal verification of arithmetic expressions and synthesized datapaths, especially considering finite word-length computation, has not been addressed. Thus formal verification techniques have been prohibited from more extensive applications in numerical and Digital Signal Processing. In this paper a formal system, called Conditional Term Rewriting on Attribute Syntax Trees (ConTRAST) is developed and demonstrated for verifying the equivalence between two differently synthesized datapaths. This result arises from a sophisticated integration of attribute grammars, which provide expressive data structures for syntactic and semantic information about designed datapaths, and term rewriting systems, which transform functionally equivalent datapaths into the same canonical form. The equivalence relation is defined as a congruence closure in the rewriting system, which can be generated from arbitrary axioms, such as associativity, commutativity, etc. in a certain algebraic system. Furthermore, the effect of finite word-lengths and their associated arithmetic precision are also considered in the definition of equivalence classes. As a particular application of ConTRAST, a formal verification system is designed to check equivalence under precision constraints. The results of initial DSP synthesis experiments are displayed, where two differently implemented IIR filters in direct II and cascaded architectures are automatically compared under given precision constraints.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127222915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a direct performance-driven placement algorithm for analog integrated circuits. The performance specifications directly drive the layout tools without intermediate parasitic constraints. A simulated-annealing algorithm is used to drive an initial solution to a placement that respects the circuit's performance specifications. During each iteration, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples.
{"title":"Direct Performance-Driven Placement of Mismatch-sensitive Analog Circuits","authors":"K. Lampaert, G. Gielen, W. Sansen","doi":"10.1145/217474.217568","DOIUrl":"https://doi.org/10.1145/217474.217568","url":null,"abstract":"This paper presents a direct performance-driven placement algorithm for analog integrated circuits. The performance specifications directly drive the layout tools without intermediate parasitic constraints. A simulated-annealing algorithm is used to drive an initial solution to a placement that respects the circuit's performance specifications. During each iteration, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124864180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power dissipated in clock distribution is a major source of total system power dissipation. Instead of increasing wire widths or lengths to reduce skew which results in increased power dissipation, we use a balanced buffer insertion scheme to partition a large clock tree into a number of small subtrees. Because asymmetric loads and wire width variations in small subtrees induce very small skew, minimal wire widths are used. This results in minimal wiring capacitance and dynamic power dissipation. Then the buffer sizing problem is formulated as a constrained optimization problem: minimize power subject to tolerable skew constraints. To minimize skew caused by device parameter variations from die to die, PMOS and NMOS devices in buffers are separately sized. Substantial power reduction is achieved while skews are kept at satisfiable values under all process conditions.
{"title":"Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution","authors":"W.-M. Dai Joe G. Xi","doi":"10.1109/dac.1995.249997","DOIUrl":"https://doi.org/10.1109/dac.1995.249997","url":null,"abstract":"Power dissipated in clock distribution is a major source of total system power dissipation. Instead of increasing wire widths or lengths to reduce skew which results in increased power dissipation, we use a balanced buffer insertion scheme to partition a large clock tree into a number of small subtrees. Because asymmetric loads and wire width variations in small subtrees induce very small skew, minimal wire widths are used. This results in minimal wiring capacitance and dynamic power dissipation. Then the buffer sizing problem is formulated as a constrained optimization problem: minimize power subject to tolerable skew constraints. To minimize skew caused by device parameter variations from die to die, PMOS and NMOS devices in buffers are separately sized. Substantial power reduction is achieved while skews are kept at satisfiable values under all process conditions.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A hybrid sequential circuit test generator is described which combines deterministic algorithms for fault excitation and propagation with genetic algorithms for state justification. Deterministic procedures for state justification are used if the genetic approach is unsuccessful, to allow for identification of untestable faults and to improve the fault coverage. High fault coverages were obtained for the ISCAS89 benchmark circuits and several additional circuits, and in many cases the results are better than those for purely deterministic approaches.
{"title":"Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation","authors":"E. Rudnick, J. Patel","doi":"10.1145/217474.217527","DOIUrl":"https://doi.org/10.1145/217474.217527","url":null,"abstract":"A hybrid sequential circuit test generator is described which combines deterministic algorithms for fault excitation and propagation with genetic algorithms for state justification. Deterministic procedures for state justification are used if the genetic approach is unsuccessful, to allow for identification of untestable faults and to improve the fault coverage. High fault coverages were obtained for the ISCAS89 benchmark circuits and several additional circuits, and in many cases the results are better than those for purely deterministic approaches.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125931636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Over one hundred micro-architecture features were analyzed and simulated in order to determine if they should be included in UltraSPARC-I. A fast and flexible performance simulator was developed in order to model these features. In this paper, we describe UPS (UltraSPARC-I Performance Simulator), and show how it was used to do trade-off analysis.
{"title":"A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC™ -I","authors":"M. Tremblay, G. Maturana, A. Inoue, Leslie Kohn","doi":"10.1145/217474.217479","DOIUrl":"https://doi.org/10.1145/217474.217479","url":null,"abstract":"Over one hundred micro-architecture features were analyzed and simulated in order to determine if they should be included in UltraSPARC-I. A fast and flexible performance simulator was developed in order to model these features. In this paper, we describe UPS (UltraSPARC-I Performance Simulator), and show how it was used to do trade-off analysis.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masayuki Yuguchi, Yuichi Nakamura, K. Wakabayashi, Tomoyuki Fujita
This paper presents a novel method for logic minimization in large-scale multi-level networks. It accomplishes its great reductions on the basis of multi-signal implications and the relationships among these implications. Both are handled on a transitive implication graph, proposed in this paper, which realizes high-speed, high-quality minimization. This proposed method holds great promise for the achievement of an interactive logic design environment for large-scale networks.
{"title":"Multi-Level Logic Minimization based on Multi-Signal Implications","authors":"Masayuki Yuguchi, Yuichi Nakamura, K. Wakabayashi, Tomoyuki Fujita","doi":"10.1145/217474.217606","DOIUrl":"https://doi.org/10.1145/217474.217606","url":null,"abstract":"This paper presents a novel method for logic minimization in large-scale multi-level networks. It accomplishes its great reductions on the basis of multi-signal implications and the relationships among these implications. Both are handled on a transitive implication graph, proposed in this paper, which realizes high-speed, high-quality minimization. This proposed method holds great promise for the achievement of an interactive logic design environment for large-scale networks.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122888577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The retiming transformation can be used to optimize synchronous circuits for maximum speed of operation by relocating their storage elements. In this paper, we describe DelaY, a tool for retiming edge-triggered circuits under a realistic delay model that handles load-dependent gate delays, variable register setup times, interconnect delays, and clock skew. The operation of DelaY relies on a novel linear programming formulation of the retiming problem in this model. For the special case where clock skew is monotonic and all registers have equal propagation delays, the retiming algorithm in our tool runs in polynomial time and can transform any given edge-triggered circuit to achieve a specifi clock period in O(V/sup 3/F) steps, where V is the number of logic gates in the circuit and F is bounded by the number of registers in the circuit.
{"title":"DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling","authors":"Kumar N. Lalgudi, M. Papaefthymiou","doi":"10.1145/217474.217546","DOIUrl":"https://doi.org/10.1145/217474.217546","url":null,"abstract":"The retiming transformation can be used to optimize synchronous circuits for maximum speed of operation by relocating their storage elements. In this paper, we describe DelaY, a tool for retiming edge-triggered circuits under a realistic delay model that handles load-dependent gate delays, variable register setup times, interconnect delays, and clock skew. The operation of DelaY relies on a novel linear programming formulation of the retiming problem in this model. For the special case where clock skew is monotonic and all registers have equal propagation delays, the retiming algorithm in our tool runs in polynomial time and can transform any given edge-triggered circuit to achieve a specifi clock period in O(V/sup 3/F) steps, where V is the number of logic gates in the circuit and F is bounded by the number of registers in the circuit.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129413364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, it has been shown in [1] and [2] that in order to verify the correct timing of a manufactured circuit not all of its paths need to be considered for delay testing. In this paper, a theory is developed which puts the work of these papers into a common framework, thus allowing for a better understanding of their relation. In addition, we consider the computational problem of identifying large sets of such not-necessary-to-test paths. Since the approach of [1] can only be applied for small scale circuits, we develop a new algorithm which trades quality of the result against computation time, and allows handling of large circuits with tens of millions of paths. Experimental results show that enormous improvements in running time are only paid for by a small decrease in quality.
{"title":"Fast Identification of Robust Dependent Path Delay Faults","authors":"U. Sparmann, D. Luxenburger, K. Cheng, S. Reddy","doi":"10.1145/217474.217517","DOIUrl":"https://doi.org/10.1145/217474.217517","url":null,"abstract":"Recently, it has been shown in [1] and [2] that in order to verify the correct timing of a manufactured circuit not all of its paths need to be considered for delay testing. In this paper, a theory is developed which puts the work of these papers into a common framework, thus allowing for a better understanding of their relation. In addition, we consider the computational problem of identifying large sets of such not-necessary-to-test paths. Since the approach of [1] can only be applied for small scale circuits, we develop a new algorithm which trades quality of the result against computation time, and allows handling of large circuits with tens of millions of paths. Experimental results show that enormous improvements in running time are only paid for by a small decrease in quality.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130681320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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