Retiming has been proposed as an optimization step for sequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so changes the number of latches and the longest path delay between the latches. In this paper we show by example that retiming a design may lead to differing simulation results when the retimed design replaces the original design. We also show, by example, that retiming may not preserve the testability of a sequential test sequence for a given stuck-at fault as measured by a simulator. We identify the cause of the problemas forward retiming moves across multiple-fanout points in the circuit. The primary contribution of this paper is to show that, while an accurate logic simulation may distinguish the retimed circuit fromthe original circuit, a conservative three-valued simulator cannot do so. Hence, retiming is a safe operation when used in a design methodology based on conservative three-valued simulation starting each latch with the unknown value.
{"title":"The Validity of Retiming Sequential Circuits","authors":"V. Singhal, C. Pixley, R. Rudell, R. Brayton","doi":"10.1145/217474.217548","DOIUrl":"https://doi.org/10.1145/217474.217548","url":null,"abstract":"Retiming has been proposed as an optimization step for sequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so changes the number of latches and the longest path delay between the latches. In this paper we show by example that retiming a design may lead to differing simulation results when the retimed design replaces the original design. We also show, by example, that retiming may not preserve the testability of a sequential test sequence for a given stuck-at fault as measured by a simulator. We identify the cause of the problemas forward retiming moves across multiple-fanout points in the circuit. The primary contribution of this paper is to show that, while an accurate logic simulation may distinguish the retimed circuit fromthe original circuit, a conservative three-valued simulator cannot do so. Hence, retiming is a safe operation when used in a design methodology based on conservative three-valued simulation starting each latch with the unknown value.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Complexity measures are potentially useful in developing modeling and re-use strategies and are recognized as being useful indictors of development cost and lifecycle metrics for systems design. In this paper, a syntactic measure complexity model for VHDL descriptions is investigated. The approach leverages similarities between VHDL models and software algorithms, where syntactic modeling has been previously applied. Aspects of the measure, including observed and estimated model length, volume, syntactic information, and abstraction level are defined and discussed. As a principle result, syntactic information modeling is related to Kolmogorov intrinsic complexity as a minimum design size implementation. Experimental data on VHDL modeling and complexity measurement is presented, with potential model comprehensibility and resource estimation applications.
{"title":"Measures of Syntactic Complexity for Modeling Behavioral VHDL","authors":"N. Stollon, J. Provence","doi":"10.1145/217474.217611","DOIUrl":"https://doi.org/10.1145/217474.217611","url":null,"abstract":"Complexity measures are potentially useful in developing modeling and re-use strategies and are recognized as being useful indictors of development cost and lifecycle metrics for systems design. In this paper, a syntactic measure complexity model for VHDL descriptions is investigated. The approach leverages similarities between VHDL models and software algorithms, where syntactic modeling has been previously applied. Aspects of the measure, including observed and estimated model length, volume, syntactic information, and abstraction level are defined and discussed. As a principle result, syntactic information modeling is related to Kolmogorov intrinsic complexity as a minimum design size implementation. Experimental data on VHDL modeling and complexity measurement is presented, with potential model comprehensibility and resource estimation applications.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122936727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a methodology for automating the evaluation of partial designs using black-box testing techniques. This methodology generates black-box evaluation tests using a novel semantic graph data model to maintain the relationships between the related design and requirements data. We demonstrate the utility of this technique by using the relationship information to automatically generate and run functionality tests of partial designs against the related requirements.
{"title":"Requirements-Based Design Evaluation","authors":"S. Frezza, S. Levitan, Panos K. Chrysanthis","doi":"10.1145/217474.217510","DOIUrl":"https://doi.org/10.1145/217474.217510","url":null,"abstract":"This paper presents a methodology for automating the evaluation of partial designs using black-box testing techniques. This methodology generates black-box evaluation tests using a novel semantic graph data model to maintain the relationships between the related design and requirements data. We demonstrate the utility of this technique by using the relationship information to automatically generate and run functionality tests of partial designs against the related requirements.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121615134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan, Manjunath Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, S. Simovich, R. Sunder, B. Sur, W. Vercruysse, M. Wong, P. Yip, R. Yu, J. Zhou, G. Zyner
The overall CAD methodology for the design of UltraSPARC-I microprocessor at Sun is described in this paper. Topics discussed include: CAD flow strategy, tool development and integration strategy, and design infrastructure. The importance of concurrent design style, modular CAD flow environment, incremental design verification and early design quality checking is strongly emphasized in this paper.
{"title":"CAD Methodology for the Design of UltraSPARC™ -I Microprocessor at Sun Microsystems Inc.","authors":"A. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan, Manjunath Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, S. Simovich, R. Sunder, B. Sur, W. Vercruysse, M. Wong, P. Yip, R. Yu, J. Zhou, G. Zyner","doi":"10.1145/217474.217485","DOIUrl":"https://doi.org/10.1145/217474.217485","url":null,"abstract":"The overall CAD methodology for the design of UltraSPARC-I microprocessor at Sun is described in this paper. Topics discussed include: CAD flow strategy, tool development and integration strategy, and design infrastructure. The importance of concurrent design style, modular CAD flow environment, incremental design verification and early design quality checking is strongly emphasized in this paper.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116852997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a technique for calculating the switching activity of a set of registers shared by different data values. Based on the assumption that the joint pdf (probability density function) of the primary input random variables is known or that a suffficiently large number of input vectors has been given, the register assignment problem for minimum power consumption is formulated as a minimum cost clique covering of an appropriately defined compatibility graph (which is shown to be transitively orientable). The problem is then solved optimally (in polynomial time) using a max-cost ow algorithm. Experimental results confirm the viability and usefulness of the approach in minimizing power consumption during the register assignment phase of the behavioral synthesis process.
{"title":"Register Allocation and Binding for Low Power","authors":"Jui-Ming Chang, Massoud Pedram","doi":"10.1145/217474.217502","DOIUrl":"https://doi.org/10.1145/217474.217502","url":null,"abstract":"This paper describes a technique for calculating the switching activity of a set of registers shared by different data values. Based on the assumption that the joint pdf (probability density function) of the primary input random variables is known or that a suffficiently large number of input vectors has been given, the register assignment problem for minimum power consumption is formulated as a minimum cost clique covering of an appropriately defined compatibility graph (which is shown to be transitively orientable). The problem is then solved optimally (in polynomial time) using a max-cost ow algorithm. Experimental results confirm the viability and usefulness of the approach in minimizing power consumption during the register assignment phase of the behavioral synthesis process.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126447711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation. The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits. The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples.
{"title":"Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels","authors":"Andrew T. Yang Ivan L. Wemple","doi":"10.1109/dac.1995.249987","DOIUrl":"https://doi.org/10.1109/dac.1995.249987","url":null,"abstract":"We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation. The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits. The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132943914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present an approach to incorporate design schedule management services into a flow management system. The basis of our approach is to derive a design schedule from the simulation of a flow execution. Actual flow execution can then be tracked against the proposed schedule via design metadata. We verify our approach by implementing design scheduling into the Hercules Workflow Manager.
{"title":"Incorporating Design Schedule Management into a Flow Management System","authors":"Jay B. Brockman Eric W. Johnson","doi":"10.1109/dac.1995.250068","DOIUrl":"https://doi.org/10.1109/dac.1995.250068","url":null,"abstract":"In this paper we present an approach to incorporate design schedule management services into a flow management system. The basis of our approach is to derive a design schedule from the simulation of a flow execution. Actual flow execution can then be tracked against the proposed schedule via design metadata. We verify our approach by implementing design scheduling into the Hercules Workflow Manager.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114882984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Built-in self-test (BIST) techniques have evolved as cost-effective techniques for testing digital circuits. These techniques add test circuitry to the chip such that the chip has the capability to test itself. A prime concern in using BIST is the area overhead due to the modification of normal registers to be test registers. This paper presents data path allocation algorithms that 1) maximize the sharing of test registers resulting in a fewer number of registers being modified for BIST, and 2) minimize the number of CBILBO registers.
{"title":"Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead","authors":"I. Parulkar, S. Gupta, M. Breuer","doi":"10.1145/217474.217561","DOIUrl":"https://doi.org/10.1145/217474.217561","url":null,"abstract":"Built-in self-test (BIST) techniques have evolved as cost-effective techniques for testing digital circuits. These techniques add test circuitry to the chip such that the chip has the capability to test itself. A prime concern in using BIST is the area overhead due to the modification of normal registers to be test registers. This paper presents data path allocation algorithms that 1) maximize the sharing of test registers resulting in a fewer number of registers being modified for BIST, and 2) minimize the number of CBILBO registers.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126673893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the input and output of every hardware entity. P/sup 2/EDAS permits, accurate, concurrent, asynchronous, and efficient, i.e. deadlock free and null-message free, execution of sequential and combinatorial digital designs on parallel processors. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, preemption of inconsistent events are allowed. P/sup 2/EDAS extends to any simulator based on high-level hardware description language. This paper presents a detailed description of the algorithm.
{"title":"Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors","authors":"P. Walker, Sumit Ghosh","doi":"10.1145/217474.217521","DOIUrl":"https://doi.org/10.1145/217474.217521","url":null,"abstract":"This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the input and output of every hardware entity. P/sup 2/EDAS permits, accurate, concurrent, asynchronous, and efficient, i.e. deadlock free and null-message free, execution of sequential and combinatorial digital designs on parallel processors. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, preemption of inconsistent events are allowed. P/sup 2/EDAS extends to any simulator based on high-level hardware description language. This paper presents a detailed description of the algorithm.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125994827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We study theminimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology Extended-DME (Ex-DME) extends the DME algorithm for exact zero-skew trees via the concept of a merging region. (2) For arbitrary topology and arbitrary embedding, Extended Greedy-DME (ExG-DME) very closely matches the best known heuristics for the zero-skewcase,and for the infinite-skewcase (i.e., the Steiner minimal tree problem). (3) For arbitrary topology and single-layer (planar) embedding, the Extended Planar-DME (ExP-DME) algorithm exactly matches the best known heuristic for zero-skewplanar routing, and closely approaches the best known performance for the infinite-skewcase. Ourwork provides unifications of the clock routing and Steiner tree heuristic literatures and gives smooth cost-skew tradeoff that enable good engineering solutions.
{"title":"On the Bounded-Skew Clock and Steiner Routing Problems","authors":"D. J. Huang, A. Kahng, C. Tsao","doi":"10.1145/217474.217579","DOIUrl":"https://doi.org/10.1145/217474.217579","url":null,"abstract":"We study theminimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology Extended-DME (Ex-DME) extends the DME algorithm for exact zero-skew trees via the concept of a merging region. (2) For arbitrary topology and arbitrary embedding, Extended Greedy-DME (ExG-DME) very closely matches the best known heuristics for the zero-skewcase,and for the infinite-skewcase (i.e., the Steiner minimal tree problem). (3) For arbitrary topology and single-layer (planar) embedding, the Extended Planar-DME (ExP-DME) algorithm exactly matches the best known heuristic for zero-skewplanar routing, and closely approaches the best known performance for the infinite-skewcase. Ourwork provides unifications of the clock routing and Steiner tree heuristic literatures and gives smooth cost-skew tradeoff that enable good engineering solutions.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124094730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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