In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on each circuit path with minimum logic duplication costs to achieve implementations with minimum delay and minimum number of chips. The overall complexity of SCP is (V2). Experimental results demonstrate that SCP produces partitions that on the average have 14% fewer chips, 28% fewer pins, and 93% fewer chip-crossings on each circuit path compared to ANN which is a simulated annealing based implementation of classical multi-way partitioning. SCP achieves this performance and compact packing at the cost of duplicating 13% of logic on the average. Additionally, in comparison with a lower bound we observe that SCP has produced near-optimal solutions.
{"title":"Multi-way Partitioning For Minimum Delay For Look-Up Table Based FPGAs","authors":"Prashant S. Sawkar, D. E. Thomas","doi":"10.1145/217474.217530","DOIUrl":"https://doi.org/10.1145/217474.217530","url":null,"abstract":"In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on each circuit path with minimum logic duplication costs to achieve implementations with minimum delay and minimum number of chips. The overall complexity of SCP is (V2). Experimental results demonstrate that SCP produces partitions that on the average have 14% fewer chips, 28% fewer pins, and 93% fewer chip-crossings on each circuit path compared to ANN which is a simulated annealing based implementation of classical multi-way partitioning. SCP achieves this performance and compact packing at the cost of duplicating 13% of logic on the average. Additionally, in comparison with a lower bound we observe that SCP has produced near-optimal solutions.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation. The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits. The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples.
{"title":"Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels","authors":"Andrew T. Yang Ivan L. Wemple","doi":"10.1109/dac.1995.249987","DOIUrl":"https://doi.org/10.1109/dac.1995.249987","url":null,"abstract":"We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation. The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits. The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132943914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We show how to quantify the suboptimality of heuristic algorithms for NP-hard problems arising in VLSI layout. Our approach is based on the notion of constructing new scaled instances from an initial problem instance. From the given problem instance, we essentially construct doubled, tripled, etc. instances which have optimum solution costs at most twice, three times, etc. that of the original instance. By executing the heuristic on these scaled instances, and then comparing the growth of solution cost with the growth of instance size, we can measure the scaling suboptimality of the heuristic. We give experimentally determined scaling behavior of several placement and partitioning heuristics; these results suggest that siginificant improvement remains possible over current state-of-the-art methods.
{"title":"Quantified Suboptimality of VLSI Layout Heuristics","authors":"L. Hagen, D. J. Huang, A. Kahng","doi":"10.1145/217474.217532","DOIUrl":"https://doi.org/10.1145/217474.217532","url":null,"abstract":"We show how to quantify the suboptimality of heuristic algorithms for NP-hard problems arising in VLSI layout. Our approach is based on the notion of constructing new scaled instances from an initial problem instance. From the given problem instance, we essentially construct doubled, tripled, etc. instances which have optimum solution costs at most twice, three times, etc. that of the original instance. By executing the heuristic on these scaled instances, and then comparing the growth of solution cost with the growth of instance size, we can measure the scaling suboptimality of the heuristic. We give experimentally determined scaling behavior of several placement and partitioning heuristics; these results suggest that siginificant improvement remains possible over current state-of-the-art methods.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126706263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Retiming has been proposed as an optimization step for sequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so changes the number of latches and the longest path delay between the latches. In this paper we show by example that retiming a design may lead to differing simulation results when the retimed design replaces the original design. We also show, by example, that retiming may not preserve the testability of a sequential test sequence for a given stuck-at fault as measured by a simulator. We identify the cause of the problemas forward retiming moves across multiple-fanout points in the circuit. The primary contribution of this paper is to show that, while an accurate logic simulation may distinguish the retimed circuit fromthe original circuit, a conservative three-valued simulator cannot do so. Hence, retiming is a safe operation when used in a design methodology based on conservative three-valued simulation starting each latch with the unknown value.
{"title":"The Validity of Retiming Sequential Circuits","authors":"V. Singhal, C. Pixley, R. Rudell, R. Brayton","doi":"10.1145/217474.217548","DOIUrl":"https://doi.org/10.1145/217474.217548","url":null,"abstract":"Retiming has been proposed as an optimization step for sequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so changes the number of latches and the longest path delay between the latches. In this paper we show by example that retiming a design may lead to differing simulation results when the retimed design replaces the original design. We also show, by example, that retiming may not preserve the testability of a sequential test sequence for a given stuck-at fault as measured by a simulator. We identify the cause of the problemas forward retiming moves across multiple-fanout points in the circuit. The primary contribution of this paper is to show that, while an accurate logic simulation may distinguish the retimed circuit fromthe original circuit, a conservative three-valued simulator cannot do so. Hence, retiming is a safe operation when used in a design methodology based on conservative three-valued simulation starting each latch with the unknown value.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity. This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.
{"title":"Software Accelerated Functional Fault Simulation for Data-Path Architectures","authors":"M. Kassab, N. Mukherjee, J. Rajski, J. Tyszer","doi":"10.1145/217474.217551","DOIUrl":"https://doi.org/10.1145/217474.217551","url":null,"abstract":"This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity. This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126717057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs. Traditionally high-level synthesis systems for DSP have either assumed that all the relative times, called phases, when corresponding samples are available at input and delay nodes are zero or have automatically assigned values to as part of the scheduling step when software pipelining is simultaneously applied. Rephasing, however, manipulates the values of these phases as a transformation before the scheduling. The advantage of this approach is that phases can be chosen to optimize the algorithm for metrics such as area and power. Moreover, rephasing can be combined with other transformations. We have developed techniques for using rephasing to optimize several design metrics. The experimental results show significant improvements.
{"title":"Rephasing: A Transformation Technique for the Manipulation of Timing Constraints","authors":"M. Potkonjak, M. Srivastava","doi":"10.1145/217474.217515","DOIUrl":"https://doi.org/10.1145/217474.217515","url":null,"abstract":"We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs. Traditionally high-level synthesis systems for DSP have either assumed that all the relative times, called phases, when corresponding samples are available at input and delay nodes are zero or have automatically assigned values to as part of the scheduling step when software pipelining is simultaneously applied. Rephasing, however, manipulates the values of these phases as a transformation before the scheduling. The advantage of this approach is that phases can be chosen to optimize the algorithm for metrics such as area and power. Moreover, rephasing can be combined with other transformations. We have developed techniques for using rephasing to optimize several design metrics. The experimental results show significant improvements.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129674217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present an approach to incorporate design schedule management services into a flow management system. The basis of our approach is to derive a design schedule from the simulation of a flow execution. Actual flow execution can then be tracked against the proposed schedule via design metadata. We verify our approach by implementing design scheduling into the Hercules Workflow Manager.
{"title":"Incorporating Design Schedule Management into a Flow Management System","authors":"Jay B. Brockman Eric W. Johnson","doi":"10.1109/dac.1995.250068","DOIUrl":"https://doi.org/10.1109/dac.1995.250068","url":null,"abstract":"In this paper we present an approach to incorporate design schedule management services into a flow management system. The basis of our approach is to derive a design schedule from the simulation of a flow execution. Actual flow execution can then be tracked against the proposed schedule via design metadata. We verify our approach by implementing design scheduling into the Hercules Workflow Manager.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114882984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information about the initial state of the circuit. In this case an unknown initial state is assumed which is usually handled by introducing a three-valued logic. As it is well-known fault simulation based on this logic only determines a lower bound of the fault coverage. Recently it has been shown that fault simulation based on the multiple observation time test strategy can improve the accuracy of the fault coverage. In this paper we describe how this strategy can be successfully implemented based on Ordered Binary Decision Diagrams. Our experiments demonstrate the efficiency of the fault simulation procedure developed.
{"title":"Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy","authors":"Rolf Krieger, B. Becker, Martin Keim","doi":"10.1145/217474.217552","DOIUrl":"https://doi.org/10.1145/217474.217552","url":null,"abstract":"Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information about the initial state of the circuit. In this case an unknown initial state is assumed which is usually handled by introducing a three-valued logic. As it is well-known fault simulation based on this logic only determines a lower bound of the fault coverage. Recently it has been shown that fault simulation based on the multiple observation time test strategy can improve the accuracy of the fault coverage. In this paper we describe how this strategy can be successfully implemented based on Ordered Binary Decision Diagrams. Our experiments demonstrate the efficiency of the fault simulation procedure developed.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130975734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Instead of sizing only the gates along the critical paths for delay reduction, the trade-off possible by simultaneously sizing gate and interconnect must also be considered. We show that for optimal gate and interconnect sizing, it is imperative that the interaction between the driver and the RC interconnect load be taken into account. We present an iterative sensitivity-based approach to simultaneous gate and interconnect sizing in terms of a gate delay model which captures this interaction. During each iteration, the path delay sensitivities are efficiently calculated and used to size the components along a path.
{"title":"Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization","authors":"N. Menezes, S. Pullela, L. Pileggi","doi":"10.1145/217474.217612","DOIUrl":"https://doi.org/10.1145/217474.217612","url":null,"abstract":"With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Instead of sizing only the gates along the critical paths for delay reduction, the trade-off possible by simultaneously sizing gate and interconnect must also be considered. We show that for optimal gate and interconnect sizing, it is imperative that the interaction between the driver and the RC interconnect load be taken into account. We present an iterative sensitivity-based approach to simultaneous gate and interconnect sizing in terms of a gate delay model which captures this interaction. During each iteration, the path delay sensitivities are efficiently calculated and used to size the components along a path.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125671242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We study theminimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology Extended-DME (Ex-DME) extends the DME algorithm for exact zero-skew trees via the concept of a merging region. (2) For arbitrary topology and arbitrary embedding, Extended Greedy-DME (ExG-DME) very closely matches the best known heuristics for the zero-skewcase,and for the infinite-skewcase (i.e., the Steiner minimal tree problem). (3) For arbitrary topology and single-layer (planar) embedding, the Extended Planar-DME (ExP-DME) algorithm exactly matches the best known heuristic for zero-skewplanar routing, and closely approaches the best known performance for the infinite-skewcase. Ourwork provides unifications of the clock routing and Steiner tree heuristic literatures and gives smooth cost-skew tradeoff that enable good engineering solutions.
{"title":"On the Bounded-Skew Clock and Steiner Routing Problems","authors":"D. J. Huang, A. Kahng, C. Tsao","doi":"10.1145/217474.217579","DOIUrl":"https://doi.org/10.1145/217474.217579","url":null,"abstract":"We study theminimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology Extended-DME (Ex-DME) extends the DME algorithm for exact zero-skew trees via the concept of a merging region. (2) For arbitrary topology and arbitrary embedding, Extended Greedy-DME (ExG-DME) very closely matches the best known heuristics for the zero-skewcase,and for the infinite-skewcase (i.e., the Steiner minimal tree problem). (3) For arbitrary topology and single-layer (planar) embedding, the Extended Planar-DME (ExP-DME) algorithm exactly matches the best known heuristic for zero-skewplanar routing, and closely approaches the best known performance for the infinite-skewcase. Ourwork provides unifications of the clock routing and Steiner tree heuristic literatures and gives smooth cost-skew tradeoff that enable good engineering solutions.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124094730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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