A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified up-front by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 ip-ops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flip-flops).
{"title":"Power Estimation in Sequential Circuitsy","authors":"F. Najm, S. Goel, I. Hajj","doi":"10.1145/217474.217602","DOIUrl":"https://doi.org/10.1145/217474.217602","url":null,"abstract":"A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified up-front by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 ip-ops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flip-flops).","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132115046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new methodology for formal logic verification for combinational circuits. Specifically, a structural approach is used, based on indirect implications derived by using Recursive Learning. This is extended to formulate a hybrid approach where this structural method is used to reduce the complexity of a subsequent functional method based on OBDDs. It is demonstrated how OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment. The experimental results show the effective compromise achieved between memory-efficient structural methods and functional methods. One more advantage of these methods lies in the fact that resources that go into logic synthesis can effectively be reused for verification purposes.
{"title":"Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment","authors":"S. Reddy, W. Kunz, D. Pradhan","doi":"10.1145/217474.328705","DOIUrl":"https://doi.org/10.1145/217474.328705","url":null,"abstract":"This paper presents a new methodology for formal logic verification for combinational circuits. Specifically, a structural approach is used, based on indirect implications derived by using Recursive Learning. This is extended to formulate a hybrid approach where this structural method is used to reduce the complexity of a subsequent functional method based on OBDDs. It is demonstrated how OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment. The experimental results show the effective compromise achieved between memory-efficient structural methods and functional methods. One more advantage of these methods lies in the fact that resources that go into logic synthesis can effectively be reused for verification purposes.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114907286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new sum-of-product based asynchronous architecture, called the N-SHOT architecture, that operates correctly under internal hazardous responses and guarantees hazard-freeness at the observable non-input signals. We formally prove that within this architecture a verywide class of semi-modular state graphs with input choices (either distributive or non-distributive) that satisfy the complete state coding property always admit a correct implementation. As with synchronous circuits,we permit internal hazards in the combinational logic core, which means we can make use of conventional combinational logic minimization methods to produce the sum-of-product implementation. This represents a significant departure from most existing methods that require the combinational logic to be hazard-free and are mainly valid for distributive behaviors.
{"title":"Externally Hazard-Free Implementations of Asynchronous Circuits","authors":"Milton H. Sawasaki, C. Ykman-Couvreur, Bill Lin","doi":"10.1145/217474.217617","DOIUrl":"https://doi.org/10.1145/217474.217617","url":null,"abstract":"We present a new sum-of-product based asynchronous architecture, called the N-SHOT architecture, that operates correctly under internal hazardous responses and guarantees hazard-freeness at the observable non-input signals. We formally prove that within this architecture a verywide class of semi-modular state graphs with input choices (either distributive or non-distributive) that satisfy the complete state coding property always admit a correct implementation. As with synchronous circuits,we permit internal hazards in the combinational logic core, which means we can make use of conventional combinational logic minimization methods to produce the sum-of-product implementation. This represents a significant departure from most existing methods that require the combinational logic to be hazard-free and are mainly valid for distributive behaviors.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"426 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126079698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Covering problems occur at several steps during logic synthesis including two-level minimization and DAG covering. This paper presents a better lower bound computation algorithm and two new pruning techniques that significantly improve the efficiency of covering problem solvers. We show that these techniques reduce by up to three orders of magnitude the time required to solve covering problems exactly.
{"title":"New Ideas for Solving Covering Problems","authors":"O. Coudert, J. Madre","doi":"10.1145/217474.217603","DOIUrl":"https://doi.org/10.1145/217474.217603","url":null,"abstract":"Covering problems occur at several steps during logic synthesis including two-level minimization and DAG covering. This paper presents a better lower bound computation algorithm and two new pruning techniques that significantly improve the efficiency of covering problem solvers. We show that these techniques reduce by up to three orders of magnitude the time required to solve covering problems exactly.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123507391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gaussian-elimination based shooting-Newton methods, a commonly used approach for computing steady-state solutions, grow in computational complexity like N/sup 3/, where N is the number of circuit equations. Just using iterative methods to solve the shooting-Newton equations results in an algorithm which is still order N/sup 2/ because of the cost of calculating the dense sensitivity matrix. Below, a matrix-free Krylov-subspace approach is presented, and the method is shown to reduce shooting-Newton computational complexity to that of ordinary transient analysis. Results from several examples are given to demonstrate that the matrix-free approach is more than ten times faster than using iterative methods alone for circuits with as few as 400 equations.
{"title":"Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods","authors":"R. Telichevesky, K. Kundert, Jacob K. White","doi":"10.1145/217474.217574","DOIUrl":"https://doi.org/10.1145/217474.217574","url":null,"abstract":"Gaussian-elimination based shooting-Newton methods, a commonly used approach for computing steady-state solutions, grow in computational complexity like N/sup 3/, where N is the number of circuit equations. Just using iterative methods to solve the shooting-Newton equations results in an algorithm which is still order N/sup 2/ because of the cost of calculating the dense sensitivity matrix. Below, a matrix-free Krylov-subspace approach is presented, and the method is shown to reduce shooting-Newton computational complexity to that of ordinary transient analysis. Results from several examples are given to demonstrate that the matrix-free approach is more than ten times faster than using iterative methods alone for circuits with as few as 400 equations.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125550720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the problem of state assignment for large Finite State Machines (FSM). This is an important problem in the high performance digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system. We present a new method to solve the graph embedding problem which is the main step in the state assignment process. The basic idea is to place the state adjacency graph in a two-dimensional grid while minimizing the total wire length. The grid is then mapped into an n-dimensional hypercube while nearly preserving the adjacency relations that is with dilation at most 2. Experimental results are presented and compared with those of NOVA.
{"title":"A Fast State Assignment Procedure for Large FSMs","authors":"Massoud Pedram Shihming Liu","doi":"10.1109/dac.1995.249968","DOIUrl":"https://doi.org/10.1109/dac.1995.249968","url":null,"abstract":"This paper addresses the problem of state assignment for large Finite State Machines (FSM). This is an important problem in the high performance digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system. We present a new method to solve the graph embedding problem which is the main step in the state assignment process. The basic idea is to place the state adjacency graph in a two-dimensional grid while minimizing the total wire length. The grid is then mapped into an n-dimensional hypercube while nearly preserving the adjacency relations that is with dilation at most 2. Experimental results are presented and compared with those of NOVA.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Most information and services required today by designers will soon become available as documents distributed in a wide area hypermedia network. New integration services are required from the design environment, supporting business transactions with design information providers, automatic exchange of design data between independent groups, and integrated support for new forms of collaboration. We discuss design using electronic commerce and other services based on the Internet, and propose a hypermedia system organization for a new generation of CAD systems, conceived to make efficient use of that infrastructure. We also describe our experience as designers of an integrated design and documentation system that interfaces existing design and documentation tools with electronic commerce services based on the World Wide Web.
{"title":"The Case for Design Using the World Wide Web","authors":"Mário J. Silva, R. Katz","doi":"10.1145/217474.217593","DOIUrl":"https://doi.org/10.1145/217474.217593","url":null,"abstract":"Most information and services required today by designers will soon become available as documents distributed in a wide area hypermedia network. New integration services are required from the design environment, supporting business transactions with design information providers, automatic exchange of design data between independent groups, and integrated support for new forms of collaboration. We discuss design using electronic commerce and other services based on the Internet, and propose a hypermedia system organization for a new generation of CAD systems, conceived to make efficient use of that infrastructure. We also describe our experience as designers of an integrated design and documentation system that interfaces existing design and documentation tools with electronic commerce services based on the World Wide Web.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131520841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Often, and certainly in the early stages of a design, the knowledge about delays is imprecise. Stochastic programming is not an adequate means to account for this imprecision. Not only is a probability distribution seldom a correct translation of the designer's delay knowledge, it also leads to inefficient algorithms. In this paper possibilistic programming is proposed for handling the retiming problem where delays are modelled as (triangular) possibilistic numbers. Beside the capability of optimizing the most possible clock cycle time and generating its possibility distribution, it allows for trade-offs between reducing clock cycle time and chances for obtaining worse solutions. It is shown that the computational complexity is the same as for retiming with exact circuit delays.
{"title":"Retiming Synchronous Circuitry with Imprecise Delays","authors":"I. Karkowski, R. Otten","doi":"10.1145/217474.217549","DOIUrl":"https://doi.org/10.1145/217474.217549","url":null,"abstract":"Often, and certainly in the early stages of a design, the knowledge about delays is imprecise. Stochastic programming is not an adequate means to account for this imprecision. Not only is a probability distribution seldom a correct translation of the designer's delay knowledge, it also leads to inefficient algorithms. In this paper possibilistic programming is proposed for handling the retiming problem where delays are modelled as (triangular) possibilistic numbers. Beside the capability of optimizing the most possible clock cycle time and generating its possibility distribution, it allows for trade-offs between reducing clock cycle time and chances for obtaining worse solutions. It is shown that the computational complexity is the same as for retiming with exact circuit delays.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"294 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113995985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents new techniques in two different areas. Firstly, it proposes a solution to the problem of testing embedded processors. Towards this end, it discusses the automatic generation of executable test programs from a specification of test patterns for processor components. Secondly, the paper shows how constraint logic programming (CLP) improves the software production process for design automation tools. The advantages of CLP languages include: built-in symbolic variables and the built-in support for constraints over finite domains such as integers and Booleans.
{"title":"Retargetable Self-Test Program Generation Using Constraint Logic Programming","authors":"U. Bieker, P. Marwedel","doi":"10.1145/217474.217597","DOIUrl":"https://doi.org/10.1145/217474.217597","url":null,"abstract":"This paper presents new techniques in two different areas. Firstly, it proposes a solution to the problem of testing embedded processors. Towards this end, it discusses the automatic generation of executable test programs from a specification of test patterns for processor components. Secondly, the paper shows how constraint logic programming (CLP) improves the software production process for design automation tools. The advantages of CLP languages include: built-in symbolic variables and the built-in support for constraints over finite domains such as integers and Booleans.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114220194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Roth-Karp decomposition is a classical decomposition method. Because it can reduce the number of input variables of a function, it becomes one of the most popular techniques used in LUT-based FPGA technology mapping. However, the lambda set selection problem, which can dramatically affect the decomposition quality in Roth-Karp decomposition, has not been formally addressed before. In this paper, we propose a new heuristic-based algorithm to solve this problem. The experimental results show that our algorithm can efficiently produce outputs with better decomposition quality than that produced by other algorithms without using lambda set selection strategy.
{"title":"Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping","authors":"W. Shen, Juinn-Dar Huang, Shih-Min Chao","doi":"10.1145/217474.217508","DOIUrl":"https://doi.org/10.1145/217474.217508","url":null,"abstract":"Roth-Karp decomposition is a classical decomposition method. Because it can reduce the number of input variables of a function, it becomes one of the most popular techniques used in LUT-based FPGA technology mapping. However, the lambda set selection problem, which can dramatically affect the decomposition quality in Roth-Karp decomposition, has not been formally addressed before. In this paper, we propose a new heuristic-based algorithm to solve this problem. The experimental results show that our algorithm can efficiently produce outputs with better decomposition quality than that produced by other algorithms without using lambda set selection strategy.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114404771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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