Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337638
D. Ma, W. Ki, C. Tsui
An adaptive switching convener is presented. It adopts a dual-loop one-cycle control for right line and load regularion, while reruining f a t response and good stabilify. DC level shijiing technique eliminates the use of negative supply voltage and enables both continuous and discontinuous conduction operation. Error correction loops greatly tightens output voltage regulation. mnamic loss control funher improves the eficiency for a wide power range. The conveticr was fabricated wirh a srondard 0 . 5 d~igi ral CMOS process. The ourput voltage cm vary from 0.9V ro 2.W wirh n tracking speed of less than 14pdV for a step change of 1.6V. Maximum efliciency of 93.7% is achieved ond high efliciency above 75% is retained over an output power of l0mW to 45OmW.
{"title":"Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process","authors":"D. Ma, W. Ki, C. Tsui","doi":"10.1109/ASPDAC.2004.1337638","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337638","url":null,"abstract":"An adaptive switching convener is presented. It adopts a dual-loop one-cycle control for right line and load regularion, while reruining f a t response and good stabilify. DC level shijiing technique eliminates the use of negative supply voltage and enables both continuous and discontinuous conduction operation. Error correction loops greatly tightens output voltage regulation. mnamic loss control funher improves the eficiency for a wide power range. The conveticr was fabricated wirh a srondard 0 . 5 d~igi ral CMOS process. The ourput voltage cm vary from 0.9V ro 2.W wirh n tracking speed of less than 14pdV for a step change of 1.6V. Maximum efliciency of 93.7% is achieved ond high efliciency above 75% is retained over an output power of l0mW to 45OmW.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126821131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337599
C. Sze, Jiang Hu, C. Alpert
In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis system. In most of previous works, buffers may be inserted at any open space. Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may be useful later to fix critical paths. In addition, a buffer solution may inadvertently force wires to go through routing congested regions. Therefore, within physical synthesis, a buffer insertion scheme needs to be aware of both placement congestion and routing congestion of the existing layout and so it has to be able to decide when to insert buffers in dense regions to achieve critical performance improvement and when to utilize the sparser regions of the chip. With the proposed Steiner tree adjustment technique, this work aims at finding congestion-aware buffered Steiner trees. Our tree adjustment technique takes a Steiner tree as input, modifies the tree and simultaneously handles the objectives of timing, placement and routing congestion. To our knowledge, this is the first study, which simultaneously considers these three objectives for the buffered Steiner tree problem. Experimental results confirm the effectiveness of our algorithm while it achieves up to 20x speed-up when comparing with the state-of-the-art algorithm (C.J. Alpert et al., 2003).
为了在日益复杂的集成电路设计中实现定时关闭，需要在集成物理合成系统中的数千个网络上执行缓冲区插入。在以前的大多数作品中，缓冲区可以插入任何开放空间。即使在大块之间的小巷中似乎有缓冲区的空间，这些区域通常被密集地填充，或者可能在以后修复关键路径时很有用。此外，缓冲解决方案可能会无意中迫使线路通过路由拥塞区域。因此，在物理合成中，缓冲区插入方案需要意识到现有布局的放置拥塞和路由拥塞，因此它必须能够决定何时在密集区域插入缓冲区以实现关键性能改进，以及何时利用芯片的稀疏区域。利用提出的斯坦纳树调整技术，本工作旨在寻找具有拥塞感知的缓冲斯坦纳树。我们的树调整技术以一棵斯坦纳树作为输入，对树进行修改，同时处理定时、布局和路由拥塞的目标。据我们所知，这是第一个同时考虑缓冲斯坦纳树问题这三个目标的研究。实验结果证实了我们的算法的有效性，与最先进的算法相比，它的速度提高了20倍(C.J. Alpert et al.， 2003)。
{"title":"A place and route aware buffered Steiner tree construction","authors":"C. Sze, Jiang Hu, C. Alpert","doi":"10.1109/ASPDAC.2004.1337599","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337599","url":null,"abstract":"In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis system. In most of previous works, buffers may be inserted at any open space. Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may be useful later to fix critical paths. In addition, a buffer solution may inadvertently force wires to go through routing congested regions. Therefore, within physical synthesis, a buffer insertion scheme needs to be aware of both placement congestion and routing congestion of the existing layout and so it has to be able to decide when to insert buffers in dense regions to achieve critical performance improvement and when to utilize the sparser regions of the chip. With the proposed Steiner tree adjustment technique, this work aims at finding congestion-aware buffered Steiner trees. Our tree adjustment technique takes a Steiner tree as input, modifies the tree and simultaneously handles the objectives of timing, placement and routing congestion. To our knowledge, this is the first study, which simultaneously considers these three objectives for the buffered Steiner tree problem. Experimental results confirm the effectiveness of our algorithm while it achieves up to 20x speed-up when comparing with the state-of-the-art algorithm (C.J. Alpert et al., 2003).","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121520044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Matsuda, R. Minami, A. Kanamori, H. Iwata, T. Ohzone, S. Yamamoto, T. Ihara, S. Nakajima
A pure CMOS threshold voltage reference (VTR)circuit achieves temperature(T) coefficient of 5 μV/°C (T=60~+100 °C) and supply voltage(VDD) sensitivity of O.1 mV/V (VDD=3-5 V). The combination of subthreshold current characteristics and different operating modes in n-MOSFETs provides a small voltage and temperature dependence. A feedback scheme from the reference output to gates of n-MOSFETs not only stabilizes the output but also saves the die area.
{"title":"A V/sub DD/ and temperature independent CMOS voltage reference circuit","authors":"T. Matsuda, R. Minami, A. Kanamori, H. Iwata, T. Ohzone, S. Yamamoto, T. Ihara, S. Nakajima","doi":"10.5555/1015090.1015238","DOIUrl":"https://doi.org/10.5555/1015090.1015238","url":null,"abstract":"A pure CMOS threshold voltage reference (V<sub>TR</sub>)circuit achieves temperature(T) coefficient of 5 μV/°C (T=60~+100 °C) and supply voltage(V<sub>DD</sub>) sensitivity of O.1 mV/V (V<sub>DD</sub>=3-5 V). The combination of subthreshold current characteristics and different operating modes in n-MOSFETs provides a small voltage and temperature dependence. A feedback scheme from the reference output to gates of n-MOSFETs not only stabilizes the output but also saves the die area.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"34 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114102745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337603
V. Rapaka, Emil Talpes, Diana Marculescu
Globally-asynchronous, locally-synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal costs, as well as an enabler for allowing fine grain speed and voltage management. Due to its inherent complexity, a possible driver application for such a design style is the case of superscalar, out-of-order processors. We propose a novel mixed-clock issue queue design, and compares and contrasts this new implementation with existing synchronous or mixed-clock versions of issue queues, used in standalone mode or in conjunction with mixed-clock FIFO (first-in, first-out) buffers for inter-domain synchronization. Both transistor level, SPICE simulation, as well as cycle-accurate, microarchitectural analysis, show that cores using mixed-clock issue queues are able to provide better energy-performance operating points when compared to their synchronous or asynchronous FIFO-based counterparts.
{"title":"Mixed-clock issue queue design for energy aware, high-performance cores","authors":"V. Rapaka, Emil Talpes, Diana Marculescu","doi":"10.1109/ASPDAC.2004.1337603","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337603","url":null,"abstract":"Globally-asynchronous, locally-synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal costs, as well as an enabler for allowing fine grain speed and voltage management. Due to its inherent complexity, a possible driver application for such a design style is the case of superscalar, out-of-order processors. We propose a novel mixed-clock issue queue design, and compares and contrasts this new implementation with existing synchronous or mixed-clock versions of issue queues, used in standalone mode or in conjunction with mixed-clock FIFO (first-in, first-out) buffers for inter-domain synchronization. Both transistor level, SPICE simulation, as well as cycle-accurate, microarchitectural analysis, show that cores using mixed-clock issue queues are able to provide better energy-performance operating points when compared to their synchronous or asynchronous FIFO-based counterparts.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115803147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337644
T. Sueyoshi, H. Uchida, H.J. Mattausch, T. Koide, Y. Mitani, T. Hironaka
We designed a compact, high-speed, and low-power hank-type 12-port register file test chip for highly-parallel processors in 0.35μm CMOS technology. In this full-custom test chip design, 72% smaller area, 25% shorter access cycle time, and 62% lower power consumption are achieved in comparison to the conventional 12-port-cell-based register file.
{"title":"Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors","authors":"T. Sueyoshi, H. Uchida, H.J. Mattausch, T. Koide, Y. Mitani, T. Hironaka","doi":"10.1109/ASPDAC.2004.1337644","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337644","url":null,"abstract":"We designed a compact, high-speed, and low-power hank-type 12-port register file test chip for highly-parallel processors in 0.35μm CMOS technology. In this full-custom test chip design, 72% smaller area, 25% shorter access cycle time, and 62% lower power consumption are achieved in comparison to the conventional 12-port-cell-based register file.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121137966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337622
Aviral Shrivastava, N. Dutt
Energy consumption is emerging as a critical design concern for programmable embedded systems. Many reduced bit-width instruction set architectures (rISA) (e.g., ARM Thumb) are being increasingly used to decrease code size. Previous work has explored energy savings in noncached rISA architectures as a byproduct of code size reduction. We present an energy efficient code generation technique for rISA architectures, and furthermore explore energy savings for both cached and noncached architectures. Our code generation technique uses profile information to find the most frequently executed parts of the program. By aggressively reducing code size on frequently executed parts, fewer fetches to instruction memory are incurred, thus reducing the power consumption of the instruction memory. We achieve an average 30% reduction in instruction memory energy consumption in cached systems, on a variety of benchmarks, as compared to non-rISA architectures.
{"title":"Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)","authors":"Aviral Shrivastava, N. Dutt","doi":"10.1109/ASPDAC.2004.1337622","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337622","url":null,"abstract":"Energy consumption is emerging as a critical design concern for programmable embedded systems. Many reduced bit-width instruction set architectures (rISA) (e.g., ARM Thumb) are being increasingly used to decrease code size. Previous work has explored energy savings in noncached rISA architectures as a byproduct of code size reduction. We present an energy efficient code generation technique for rISA architectures, and furthermore explore energy savings for both cached and noncached architectures. Our code generation technique uses profile information to find the most frequently executed parts of the program. By aggressively reducing code size on frequently executed parts, fewer fetches to instruction memory are incurred, thus reducing the power consumption of the instruction memory. We achieve an average 30% reduction in instruction memory energy consumption in cached systems, on a variety of benchmarks, as compared to non-rISA architectures.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337652
J. Yeom, T. Ishitsu, H. Takahashi
We present a versatile method for signal processing as an alternative to conventional methods using discrete front-end electronics. A new Waveform Sampling Front-End (WSFE) ASIC for Positron Emission Tomography (PET) has been developed to digitize signals at an early stage. Each channel of the chip consists of a preamplifier, a variable gain amplifier (VGA) and a fast Analog to Digital Converter (ADC) per channel. Two such chips have been designed and experimental results are presented in this paper.
{"title":"Development of a waveform sampling front-end ASIC for PET","authors":"J. Yeom, T. Ishitsu, H. Takahashi","doi":"10.1109/ASPDAC.2004.1337652","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337652","url":null,"abstract":"We present a versatile method for signal processing as an alternative to conventional methods using discrete front-end electronics. A new Waveform Sampling Front-End (WSFE) ASIC for Positron Emission Tomography (PET) has been developed to digitize signals at an early stage. Each channel of the chip consists of a preamplifier, a variable gain amplifier (VGA) and a fast Analog to Digital Converter (ADC) per channel. Two such chips have been designed and experimental results are presented in this paper.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127761195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337566
Yen-Te Ho, TingTing Hwang
We study the reduction of static power consumption by dual threshold voltage assignment. Our goal is, under given timing constraint, to select a maximum number of gates working at high-Vth such that the total power gain is maximized. We propose a maximum independent set based slack assignment algorithm to select gates for high-Vth. The results show that our assignment algorithm can achieve about 68% improvement as compared to results without using dual Vth.
{"title":"Low power design using dual threshold voltage","authors":"Yen-Te Ho, TingTing Hwang","doi":"10.1109/ASPDAC.2004.1337566","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337566","url":null,"abstract":"We study the reduction of static power consumption by dual threshold voltage assignment. Our goal is, under given timing constraint, to select a maximum number of gates working at high-Vth such that the total power gain is maximized. We propose a maximum independent set based slack assignment algorithm to select gates for high-Vth. The results show that our assignment algorithm can achieve about 68% improvement as compared to results without using dual Vth.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133292841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
0.6μm CMOS integrated digital PID controllerf or a buck converfer is fabricated and tested. It conrisfs of: (1) a VCO driving a counter to serve as an ADC; (2) a PID compensator that employs a programmable intwotion time for enhancing accuracy and stability; and (3) a dual-band switching PWM generator with a modified tapped delay line for better output resolution and area efficiency. The converter switches at 1MHz, while the tracking time is 50μ for a step change of IV.
{"title":"A dual-band switching digital controller for a buck converter","authors":"Martin Yeung-Kei Chui, W. Ki, C. Tsui","doi":"10.5555/1015090.1015239","DOIUrl":"https://doi.org/10.5555/1015090.1015239","url":null,"abstract":"0.6μm CMOS integrated digital PID controllerf or a buck converfer is fabricated and tested. It conrisfs of: (1) a VCO driving a counter to serve as an ADC; (2) a PID compensator that employs a programmable intwotion time for enhancing accuracy and stability; and (3) a dual-band switching PWM generator with a modified tapped delay line for better output resolution and area efficiency. The converter switches at 1MHz, while the tracking time is 50μ for a step change of IV.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133254563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337633
K. Nishio, H. Yonezu, S. Sawa, Y. Furukawa
An analog integrated circuit for approach detection with simple-shape recognition was proposed and fabricated based on the lower animal vision. It was clarified that the approaching direction and velocity can be detected by using the fabricated chip. Moreover, it was able to recognize the simple shape such as a circle, square, rectangle and triangle.
{"title":"Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal vision","authors":"K. Nishio, H. Yonezu, S. Sawa, Y. Furukawa","doi":"10.1109/ASPDAC.2004.1337633","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337633","url":null,"abstract":"An analog integrated circuit for approach detection with simple-shape recognition was proposed and fabricated based on the lower animal vision. It was clarified that the approaching direction and velocity can be detected by using the fabricated chip. Moreover, it was able to recognize the simple shape such as a circle, square, rectangle and triangle.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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