Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517658
Mengyao Wei, B. He, S. Somasundaram, C. S. Tan, E. Wang
Micropillar based wicks were widely studied in recent years. They were proven to be promising candidates for evaporators inside vapor chambers as they possess advantages of high capillary pressure, permeability, large areas for thin film evaporation and easy-controlled fabrication processes. In this work, optimization of uniform evaporator with cylindrical silicon micropillars are conducted with Brinkman's equation derived model. Sample with optimized geometries is designed, fabricated and thermally tested inside a vacuum chamber. Theoretically, the best combination of micropillar geometries are d= 20.7 μm, h=l=36.3 μm. The calculated heat flux for optimized evaporator is q"=93.5 W/cm2 at superheat of 15 °C. Measured maximum heat flux of the actual sample is q"= 80.6 W/cm2 at 13.2 °C superheat due to deviation in pillar height. The model is proven to have good correlation with preliminary experimental results.
{"title":"Optimization and thermal characterization of uniform micropillar based silicon evaporator in advanced vapor chambers","authors":"Mengyao Wei, B. He, S. Somasundaram, C. S. Tan, E. Wang","doi":"10.1109/ITHERM.2016.7517658","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517658","url":null,"abstract":"Micropillar based wicks were widely studied in recent years. They were proven to be promising candidates for evaporators inside vapor chambers as they possess advantages of high capillary pressure, permeability, large areas for thin film evaporation and easy-controlled fabrication processes. In this work, optimization of uniform evaporator with cylindrical silicon micropillars are conducted with Brinkman's equation derived model. Sample with optimized geometries is designed, fabricated and thermally tested inside a vacuum chamber. Theoretically, the best combination of micropillar geometries are d= 20.7 μm, h=l=36.3 μm. The calculated heat flux for optimized evaporator is q\"=93.5 W/cm2 at superheat of 15 °C. Measured maximum heat flux of the actual sample is q\"= 80.6 W/cm2 at 13.2 °C superheat due to deviation in pillar height. The model is proven to have good correlation with preliminary experimental results.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"2000 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128284030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517559
Chang-Chun Lee, Pei-Chen Huang, Bow-Tsin Chian
To meet the requirements of electronic devices having high operated speed, multi-functions, and a low form factor, a great classic shift of the system integration composed of heterogeneous and homogenous substances from two-dimensional (2D) to 2.5D or even 3D integration is a promising solution while a physical limit of nano-scaled transistors and the bottlenecks emerge of related fabricated technologies are confronted. To realize the foregoing architectures of 3D-ICs packaging, the interconnects, composed of through silicon via (TSV) and microbumps, have attracted a lot of attentions due to high density connections among stacked chips can be vertically achieved. However, as the layout arrangements of microbump arrays are taken into account, because of numerous microbumps with complicated compositions and a significant dimensional mismatch among them, the failure location and precise reliability estimation of a whole packaging structure are difficult to acquire by the simulated predictions directly. To resolve this problem, the methodology of equivalent material characteristics for microbump arrays extracted from finite element analysis (FEA) by using the way of usual bulk material tests is proposed in this study. To demonstrate the feasibility of above-mentioned approach, a testing vehicle of chip-on-chip packaging with wafer level underfills (WLUFs) is utilized to explore the applied influence of internal microbump arrays with equivalent material properties on the magnitude and contour of stresses at the critical locations where the detailed configurations of microbumps are still needed to construct in FEA under the loading of temperature cycling test. In addition, the present approach for equivalent material properties of microbumps combined with a global/local sub-modeling technique is also implemented and discussed, separately. Under the supposition of that the lead-free solder within a microbump is completely transferred to Ni3Sn4 intermetallic compound (IMC), the maximum principal stress of IMC layer based on the failure mode of brittle matter is used to judge the numerical convergence of FEA. The results indicate that at least four rows of real micrbumps originated from the outermost array edge of packaging structure are required to maintain the numerical accuracy as compared with the consequence obtained by a fully constructed simulated model. Moreover, it is found that a small deviation of 5 % in stress magnitude by using a sub-modeling technique can be managed when a distance of 60 μm between the edge of local model and concerned microbump is taken into account.
{"title":"Development and demonstration of equivalent material characteristics for microbump arrays utilized in failure estimation of chip-on-chip packaging","authors":"Chang-Chun Lee, Pei-Chen Huang, Bow-Tsin Chian","doi":"10.1109/ITHERM.2016.7517559","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517559","url":null,"abstract":"To meet the requirements of electronic devices having high operated speed, multi-functions, and a low form factor, a great classic shift of the system integration composed of heterogeneous and homogenous substances from two-dimensional (2D) to 2.5D or even 3D integration is a promising solution while a physical limit of nano-scaled transistors and the bottlenecks emerge of related fabricated technologies are confronted. To realize the foregoing architectures of 3D-ICs packaging, the interconnects, composed of through silicon via (TSV) and microbumps, have attracted a lot of attentions due to high density connections among stacked chips can be vertically achieved. However, as the layout arrangements of microbump arrays are taken into account, because of numerous microbumps with complicated compositions and a significant dimensional mismatch among them, the failure location and precise reliability estimation of a whole packaging structure are difficult to acquire by the simulated predictions directly. To resolve this problem, the methodology of equivalent material characteristics for microbump arrays extracted from finite element analysis (FEA) by using the way of usual bulk material tests is proposed in this study. To demonstrate the feasibility of above-mentioned approach, a testing vehicle of chip-on-chip packaging with wafer level underfills (WLUFs) is utilized to explore the applied influence of internal microbump arrays with equivalent material properties on the magnitude and contour of stresses at the critical locations where the detailed configurations of microbumps are still needed to construct in FEA under the loading of temperature cycling test. In addition, the present approach for equivalent material properties of microbumps combined with a global/local sub-modeling technique is also implemented and discussed, separately. Under the supposition of that the lead-free solder within a microbump is completely transferred to Ni3Sn4 intermetallic compound (IMC), the maximum principal stress of IMC layer based on the failure mode of brittle matter is used to judge the numerical convergence of FEA. The results indicate that at least four rows of real micrbumps originated from the outermost array edge of packaging structure are required to maintain the numerical accuracy as compared with the consequence obtained by a fully constructed simulated model. Moreover, it is found that a small deviation of 5 % in stress magnitude by using a sub-modeling technique can be managed when a distance of 60 μm between the edge of local model and concerned microbump is taken into account.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130401257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517557
S. Young, D. Janssen, E. Wenzel, B. Shadakofsky, F. Kulacki
A new technology for onboard liquid cooling of high power density electronic devices is introduced via conformal encapsulation of the devices and direct contact liquid cooling. This research effort addresses size, weight and power constraints of onboard application with a CFD-enabled design that delivers a uniform coolant flow over single- and multi-device layouts through a microgap channel. The paradigm shift is the replacement of inefficient remote air cooling and associated high resistance conduction paths with the use of microgap flow boiling with direct coolant contact at the device level. The coolant used in all measurements is Novec™ 7200, and the electronics are emulated with resistance heaters on a 1:1 scale. Thermal performance is demonstrated at power densities on the order of 1 KW/cm3. Parameters investigated include average device temperature, pressure drop, flow field characterization, and overall heat transfer coefficients. For single chip encapsulation, thermal-fluid performance with microgaps of 0.25, 0.5 and 0.75 mm is determined. With low coolant inlet subcooling, two-phase heat transfer is seen at all coolant mass flows. Device temperatures reach 95 °C for power dissipation of 50 - 80 W depending on coolant flow for a gap of 0.5 mm. Inlet subcooling of 25 and 51 °C permits higher power dissipation with nucleate flow boiling on the device surface. For multi-device encapsulation comprising two memory chips arranged symmetrically in line with a larger processor, the best thermal performance is obtained for inlet flow over the processor. For all measurements, the gap between the processor and encapsulation is 0.5 mm, and the gap above the memory chips is 1.0 mm. For inlet coolant flow first over the memory chips, the small chips exceed the 95°C limit when processor power is ~50 W or less. Processor temperature reaches 95 °C at ~80 W over the range of coolant flows tested. For inlet flow first over the processor, memory device temperatures are approximately the same over all levels of processor and memory chip powers. For processor power <; 30 W and an inlet coolant temperature of 25°C, single-phase heat transfer is the dominant cooling mechanism. When processor power is > 40 W, two-phase heat transfer dominates, and a processor power of 120 W is reached within the 95 °C threshold.
{"title":"Electronics cooling with onboard conformal encapsulation","authors":"S. Young, D. Janssen, E. Wenzel, B. Shadakofsky, F. Kulacki","doi":"10.1109/ITHERM.2016.7517557","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517557","url":null,"abstract":"A new technology for onboard liquid cooling of high power density electronic devices is introduced via conformal encapsulation of the devices and direct contact liquid cooling. This research effort addresses size, weight and power constraints of onboard application with a CFD-enabled design that delivers a uniform coolant flow over single- and multi-device layouts through a microgap channel. The paradigm shift is the replacement of inefficient remote air cooling and associated high resistance conduction paths with the use of microgap flow boiling with direct coolant contact at the device level. The coolant used in all measurements is Novec™ 7200, and the electronics are emulated with resistance heaters on a 1:1 scale. Thermal performance is demonstrated at power densities on the order of 1 KW/cm3. Parameters investigated include average device temperature, pressure drop, flow field characterization, and overall heat transfer coefficients. For single chip encapsulation, thermal-fluid performance with microgaps of 0.25, 0.5 and 0.75 mm is determined. With low coolant inlet subcooling, two-phase heat transfer is seen at all coolant mass flows. Device temperatures reach 95 °C for power dissipation of 50 - 80 W depending on coolant flow for a gap of 0.5 mm. Inlet subcooling of 25 and 51 °C permits higher power dissipation with nucleate flow boiling on the device surface. For multi-device encapsulation comprising two memory chips arranged symmetrically in line with a larger processor, the best thermal performance is obtained for inlet flow over the processor. For all measurements, the gap between the processor and encapsulation is 0.5 mm, and the gap above the memory chips is 1.0 mm. For inlet coolant flow first over the memory chips, the small chips exceed the 95°C limit when processor power is ~50 W or less. Processor temperature reaches 95 °C at ~80 W over the range of coolant flows tested. For inlet flow first over the processor, memory device temperatures are approximately the same over all levels of processor and memory chip powers. For processor power <; 30 W and an inlet coolant temperature of 25°C, single-phase heat transfer is the dominant cooling mechanism. When processor power is > 40 W, two-phase heat transfer dominates, and a processor power of 120 W is reached within the 95 °C threshold.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126765998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517568
A. Sridhar, Ozgur Ozsun, T. Brunschwiler, B. Michel, P. Parida, T. Chainer
Novel hierarchical radially expanding micro-channel networks with pin fins have been proposed recently to enable high-performance embedded two-phase liquid cooling of two- and three-dimensional integrated circuits dissipating extremely high heat fluxes (of the order of 1kW/cm2) [1]. The effective design of such a complex two-phase liquid cooling architecture requires a comprehensive understanding of the various constituent sub-systems. Fundamental experiments were performed as a part of this work to study and model two-phase flow boiling and heat transfer using R-1234ze refrigerant in a two-port micro-scale cavity populated with pin fins which provide structures to accommodate vertical electrical interconnects (TSVs) as well as enhance heat transfer. In this first part of a two-part paper, results from the aforementioned fundamental study are presented. First, experimental procedure, including motivation, test set up, data acquisition and analysis is described. Next, the procedure for data reduction is detailed where an assumption of one-dimensional (1D) heat conduction in silicon is applied to resolve the two-phase flow boiling data. From this reduced data, empirical pressure drop and heat transfer correlations were derived as a function of mass flux, wall heat flux, pin fin angle of attack and the local vapor quality. These correlations were used to simulate and design two-phase cooled microchannels with enhanced heat transfer geometries such as pin fins, using compact low-complexity thermal models called STEAM and RTP. The accuracy and the speed of the models are demonstrated using simulations and validation against the experimental data.
{"title":"Study of two-phase pressure drop and heat transfer in a micro-scale pin fin cavity: Part A","authors":"A. Sridhar, Ozgur Ozsun, T. Brunschwiler, B. Michel, P. Parida, T. Chainer","doi":"10.1109/ITHERM.2016.7517568","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517568","url":null,"abstract":"Novel hierarchical radially expanding micro-channel networks with pin fins have been proposed recently to enable high-performance embedded two-phase liquid cooling of two- and three-dimensional integrated circuits dissipating extremely high heat fluxes (of the order of 1kW/cm2) [1]. The effective design of such a complex two-phase liquid cooling architecture requires a comprehensive understanding of the various constituent sub-systems. Fundamental experiments were performed as a part of this work to study and model two-phase flow boiling and heat transfer using R-1234ze refrigerant in a two-port micro-scale cavity populated with pin fins which provide structures to accommodate vertical electrical interconnects (TSVs) as well as enhance heat transfer. In this first part of a two-part paper, results from the aforementioned fundamental study are presented. First, experimental procedure, including motivation, test set up, data acquisition and analysis is described. Next, the procedure for data reduction is detailed where an assumption of one-dimensional (1D) heat conduction in silicon is applied to resolve the two-phase flow boiling data. From this reduced data, empirical pressure drop and heat transfer correlations were derived as a function of mass flux, wall heat flux, pin fin angle of attack and the local vapor quality. These correlations were used to simulate and design two-phase cooled microchannels with enhanced heat transfer geometries such as pin fins, using compact low-complexity thermal models called STEAM and RTP. The accuracy and the speed of the models are demonstrated using simulations and validation against the experimental data.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"6 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123634791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517690
Zhen Qin, S. Dubey, F. Choo, H. Deng, F. Duan
Thermal energy storage is widely employed in waste heat recovery. Phase change materials (PCMs) are a type of promising thermal storage (TES) approach featuring high energy stored or released during melting and freezing. In this study, a latent heat storage system is designed to collect the waste heat from hot air while its efficiency is experimentally investigated. The system consists of five cuboid chambers to store PCMs and six air channels to deliver the exhausted gas. Paraffin wax is selected as the tested PCMs and differential scanning calorimetry (DSC) is applied to calibrate its melting range and latent heat. In the experiments, the effects of average air velocities and inlet air temperature on the performance of the latent heat storage unit are experimentally investigated. The experiments show that the designed TES unit can store maximally thermal energy for near 4510 kJ within 250 min, while the latent heat occupies 15 % at fan speed 25 RPM and the heater power with 2 kW. It is indicated that increasing of air mass flow rate and increasing of air inlet temperature can improve the heat transfer performance. It is found that the temperature profiles in the freezing process are smoother than those in the melting process.
{"title":"Low-grade heat collection from a latent heat thermal energy storage unit","authors":"Zhen Qin, S. Dubey, F. Choo, H. Deng, F. Duan","doi":"10.1109/ITHERM.2016.7517690","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517690","url":null,"abstract":"Thermal energy storage is widely employed in waste heat recovery. Phase change materials (PCMs) are a type of promising thermal storage (TES) approach featuring high energy stored or released during melting and freezing. In this study, a latent heat storage system is designed to collect the waste heat from hot air while its efficiency is experimentally investigated. The system consists of five cuboid chambers to store PCMs and six air channels to deliver the exhausted gas. Paraffin wax is selected as the tested PCMs and differential scanning calorimetry (DSC) is applied to calibrate its melting range and latent heat. In the experiments, the effects of average air velocities and inlet air temperature on the performance of the latent heat storage unit are experimentally investigated. The experiments show that the designed TES unit can store maximally thermal energy for near 4510 kJ within 250 min, while the latent heat occupies 15 % at fan speed 25 RPM and the heater power with 2 kW. It is indicated that increasing of air mass flow rate and increasing of air inlet temperature can improve the heat transfer performance. It is found that the temperature profiles in the freezing process are smoother than those in the melting process.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121366823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517588
Mehrdad Mehrvand, S. Putnam
This study describes the use of optical pump-probe diagnostics to characterize the heat transfer coefficient (HTC) in a developing thermal boundary layer in a microchannel. We use a differential form of the anisotropic time-domain thermoreflectance (TDTR) technique to measure the HTC as a function of fluid flow rate (or Reynolds number, Re). The testing environment/geometry consists of single-phase, degassed water flowing in a rectangular microchannel (hydraulic diameter Dh ≅ 480 μm) with local spot heating by the pump TDTR laser beam. Relative to the HTC measured with non-flowing (static) fluids, we find a 30% increase in the HTC for single-phase water flowing at Re ~ 1800.
{"title":"Heat transfer coefficient measurements in the thermal boundary layer of microchannel heat sinks","authors":"Mehrdad Mehrvand, S. Putnam","doi":"10.1109/ITHERM.2016.7517588","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517588","url":null,"abstract":"This study describes the use of optical pump-probe diagnostics to characterize the heat transfer coefficient (HTC) in a developing thermal boundary layer in a microchannel. We use a differential form of the anisotropic time-domain thermoreflectance (TDTR) technique to measure the HTC as a function of fluid flow rate (or Reynolds number, Re). The testing environment/geometry consists of single-phase, degassed water flowing in a rectangular microchannel (hydraulic diameter Dh ≅ 480 μm) with local spot heating by the pump TDTR laser beam. Relative to the HTC measured with non-flowing (static) fluids, we find a 30% increase in the HTC for single-phase water flowing at Re ~ 1800.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517523
S. Somasundaram, K. Bagnall, S. Adera, B. He, Mengyao Wei, C. S. Tan, E. Wang
The present work describes the method by which the thermal resistance of a flat heat pipe spreader can be more accurately computed. The total effectiveness of the heat spreader is dependent on the one-dimensional (R1D) thermal resistance and the thermal spreading resistance (Rs). Recently developed more accurate methods from the literature were used to calculate the spreading resistance by taking into account all the multiple layers of the heat pipe. Both R1D and Rs depend to a large extent on the effective thermal conductivity of the wick. The calculation of effective thermal conductivity of wick is demonstrated using well-defined silicon micropillars. The effect of interfacial heat transfer resistance, which is usually neglected on the wick's thermal resistance is also discussed. Finally, the effective thermal conductivity of a flat heat pipe as a function of vapor chamber size and effective wick thermal conductivity is calculated. As the overall device performance strongly depends on the estimation of wick thermal resistance, the results of this study show that an effective thermal conductivity that is equal to or better than diamond can be attained with proper design. Furthermore, this work provides design tools that can be used to optimize the overall device level thermal performance.
{"title":"Detailed thermal resistance model for characterization of the overall effective thermal conductivity of a flat heat pipe","authors":"S. Somasundaram, K. Bagnall, S. Adera, B. He, Mengyao Wei, C. S. Tan, E. Wang","doi":"10.1109/ITHERM.2016.7517523","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517523","url":null,"abstract":"The present work describes the method by which the thermal resistance of a flat heat pipe spreader can be more accurately computed. The total effectiveness of the heat spreader is dependent on the one-dimensional (R1D) thermal resistance and the thermal spreading resistance (Rs). Recently developed more accurate methods from the literature were used to calculate the spreading resistance by taking into account all the multiple layers of the heat pipe. Both R1D and Rs depend to a large extent on the effective thermal conductivity of the wick. The calculation of effective thermal conductivity of wick is demonstrated using well-defined silicon micropillars. The effect of interfacial heat transfer resistance, which is usually neglected on the wick's thermal resistance is also discussed. Finally, the effective thermal conductivity of a flat heat pipe as a function of vapor chamber size and effective wick thermal conductivity is calculated. As the overall device performance strongly depends on the estimation of wick thermal resistance, the results of this study show that an effective thermal conductivity that is equal to or better than diamond can be attained with proper design. Furthermore, this work provides design tools that can be used to optimize the overall device level thermal performance.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125769139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517590
S. Sridhar, A. Raj, Seth Gordon, S. Thirugnanasambandam, John L. Evans, W. Johnson
Board level drop impact testing is one of the most important modes of evaluating the reliability of assemblies. This study examines the drop impact performance of no aged and isothermally aged flip chip packages on laminate assemblies for various doped lead-free solder paste alloys. A potential solution to replace the industrial standard solder paste Sn96.5 Ag3.0 Cu0.5 (SAC305) was carried out. The test vehicle consisted of 16 ball grid array packages (BGA) which were 15mm chip array ball grid array's (CABGA208) with perimeter solder balls on 0.8mm pitch. In this experimental study, SnAgCu solder bumps and SAC305 solder paste were selected to be the baseline, Solder pastes with 12 different dopant levels were investigated in comparison with the baseline to determine their reliability. Two sets of printed circuit boards (PCB) were manufactured, the first being no aged and the second set of boards were isothermally aged at 125C for 6 months and then tested. The boards were further categorized into 3 different reflow temperatures and 2 different stencil thicknesses, 4 mil and 6 mil respectively. JEDEC BS111 test standard was followed to conduct the drop testing where the half sine impact pulse duration of 0.5ms with peak acceleration at 1500G's was maintained. The boards were subjected to accelerated life testing where the test end state was 300 drops, and the data was collected at an interval of every 20 drops. The results of non-aged and aged samples were categorized and compared using data analytics and Weibull analysis. Failure analysis was carried out to determine best solder paste, solder ball, reflow temperature profile and stencil size for the future work.
{"title":"Drop impact reliability testing of isothermally aged doped low creep lead-free solder paste alloys","authors":"S. Sridhar, A. Raj, Seth Gordon, S. Thirugnanasambandam, John L. Evans, W. Johnson","doi":"10.1109/ITHERM.2016.7517590","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517590","url":null,"abstract":"Board level drop impact testing is one of the most important modes of evaluating the reliability of assemblies. This study examines the drop impact performance of no aged and isothermally aged flip chip packages on laminate assemblies for various doped lead-free solder paste alloys. A potential solution to replace the industrial standard solder paste Sn96.5 Ag3.0 Cu0.5 (SAC305) was carried out. The test vehicle consisted of 16 ball grid array packages (BGA) which were 15mm chip array ball grid array's (CABGA208) with perimeter solder balls on 0.8mm pitch. In this experimental study, SnAgCu solder bumps and SAC305 solder paste were selected to be the baseline, Solder pastes with 12 different dopant levels were investigated in comparison with the baseline to determine their reliability. Two sets of printed circuit boards (PCB) were manufactured, the first being no aged and the second set of boards were isothermally aged at 125C for 6 months and then tested. The boards were further categorized into 3 different reflow temperatures and 2 different stencil thicknesses, 4 mil and 6 mil respectively. JEDEC BS111 test standard was followed to conduct the drop testing where the half sine impact pulse duration of 0.5ms with peak acceleration at 1500G's was maintained. The boards were subjected to accelerated life testing where the test end state was 300 drops, and the data was collected at an interval of every 20 drops. The results of non-aged and aged samples were categorized and compared using data analytics and Weibull analysis. Failure analysis was carried out to determine best solder paste, solder ball, reflow temperature profile and stencil size for the future work.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134552275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517528
Jiatong Liu, Takeru Kato, Ken Suzuki, H. Miura
The crystallinity of electroplated copper thin-film interconnections varies drastically depending on its manufacturing process, and thus, their mechanical and electrical properties change significantly depending on their micro texture. These changes should cause the variation of the residual stress in the interconnections, and thus, electronic performance of devices and the lifetime of interconnections should vary depending on the amplitude of the residual stress around TSV structures. The main reasons for high residual stress is attributed to not only thermal stress but also the shrinkage of the interconnections during their thermal history. Since the crystallinity of the interconnections varies drastically depending on their electroplating process, the residual stress after high temperature annealing is a strong function of the crystallinity. In this paper, the dominant process factors for changing the crystallinity and the residual stress in the electroplated interconnections were investigated by varying the electroplating process parameters systematically. Finally, it was found that the control of the crystallinity of a seed layer material used for the electroplating is the most important factor for controlling the crystallinity and long-term reliability of thin electroplated interconnections.
{"title":"Minimization of residual stress in TSV interconnections by controlling their crystallinity","authors":"Jiatong Liu, Takeru Kato, Ken Suzuki, H. Miura","doi":"10.1109/ITHERM.2016.7517528","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517528","url":null,"abstract":"The crystallinity of electroplated copper thin-film interconnections varies drastically depending on its manufacturing process, and thus, their mechanical and electrical properties change significantly depending on their micro texture. These changes should cause the variation of the residual stress in the interconnections, and thus, electronic performance of devices and the lifetime of interconnections should vary depending on the amplitude of the residual stress around TSV structures. The main reasons for high residual stress is attributed to not only thermal stress but also the shrinkage of the interconnections during their thermal history. Since the crystallinity of the interconnections varies drastically depending on their electroplating process, the residual stress after high temperature annealing is a strong function of the crystallinity. In this paper, the dominant process factors for changing the crystallinity and the residual stress in the electroplated interconnections were investigated by varying the electroplating process parameters systematically. Finally, it was found that the control of the crystallinity of a seed layer material used for the electroplating is the most important factor for controlling the crystallinity and long-term reliability of thin electroplated interconnections.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133456654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517586
M. Motalab, M. Mustafa, J. Suhling, P. Lall
Solder materials in electronic packages are often subjected to thermal cycling, either during their application in products or during accelerated life qualification testing. Cyclic temperatures cause the solder joints to be subjected to cyclic mechanical stresses and strains due to the mismatches in the thermal expansion coefficients of the assembly materials. Such loads lead to thermo-mechanical fatigue including damage accumulation, crack initiation and propagation, and eventual failure. Prior studies have revealed that the predictions of cyclic stress-strain curves using the standard Anand viscoplastic constitutive model yield hysteresis loops that are different in shape and loop area when compared with the experimental results. In this investigation, the evolution equation of the Anand constitutive model has been modified for the lead free solders by adding a static recovery term. This modification results in the reduction of value of the internal variable (resistance to plastic deformation) of the model during the unloading/reloading steps. Software has been written to implement the modified relationship for the change of the internal variable during the cyclic stress-strain experiments of non-aged SAC305 solder material. The cyclic stress-strain data have also been measured for the same solder material and the hysteresis loop has been plotted. From the results, it has been observed that the modified equation of the Anand constitutive model gives much better correlation between the experimental and predicted cyclic stress-strain curves. Simulations have also been performed for aged SAC305 solder (0-180 days of aging of SAC305 solder material at 100 oC), and the effects of aging on the cyclic stress-strain curves have been determined. For all aging conditions, better correlations with experimental data were obtained when the modified Anand model approach was used. With aging, the area of the hysteresis loop is reduced with increasing aging time for strain controlled cyclic stress-strain tests.
{"title":"Improved predictions of cyclic stress-strain curves for lead free solders using the Anand viscoplastic constitutive model","authors":"M. Motalab, M. Mustafa, J. Suhling, P. Lall","doi":"10.1109/ITHERM.2016.7517586","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517586","url":null,"abstract":"Solder materials in electronic packages are often subjected to thermal cycling, either during their application in products or during accelerated life qualification testing. Cyclic temperatures cause the solder joints to be subjected to cyclic mechanical stresses and strains due to the mismatches in the thermal expansion coefficients of the assembly materials. Such loads lead to thermo-mechanical fatigue including damage accumulation, crack initiation and propagation, and eventual failure. Prior studies have revealed that the predictions of cyclic stress-strain curves using the standard Anand viscoplastic constitutive model yield hysteresis loops that are different in shape and loop area when compared with the experimental results. In this investigation, the evolution equation of the Anand constitutive model has been modified for the lead free solders by adding a static recovery term. This modification results in the reduction of value of the internal variable (resistance to plastic deformation) of the model during the unloading/reloading steps. Software has been written to implement the modified relationship for the change of the internal variable during the cyclic stress-strain experiments of non-aged SAC305 solder material. The cyclic stress-strain data have also been measured for the same solder material and the hysteresis loop has been plotted. From the results, it has been observed that the modified equation of the Anand constitutive model gives much better correlation between the experimental and predicted cyclic stress-strain curves. Simulations have also been performed for aged SAC305 solder (0-180 days of aging of SAC305 solder material at 100 oC), and the effects of aging on the cyclic stress-strain curves have been determined. For all aging conditions, better correlations with experimental data were obtained when the modified Anand model approach was used. With aging, the area of the hysteresis loop is reduced with increasing aging time for strain controlled cyclic stress-strain tests.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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