Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517561
J. Roberts, C. Bhat, J. Suhling, R. Jaeger, P. Lall
In this work, the reliability of a novel advanced packaging design for microprocessors has been explored. The new architecture consists of a Ceramic Ball Grid Array (CBGA) package with a flip chip die on a high CTE ceramic substrate, and an array of decoupling capacitors used within the second level interconnects. The capacitors are modified chip capacitors that are soldered immediately beneath the CBGA substrate in a square array that replaces some or all of the ball grid array solder joints. This location for the capacitors improves electrical performance of the microprocessor package (reduces noise/crosstalk and increases speed), and also provides resistance to solder joint collapse. The value of the designs in this investigation is in moving the decoupling capacitive elements of the package closer to the die while having a comparable mechanical reliability to an analogous BGA package. Test assemblies of the new packaging concept containing daisy chain test die have been prepared and subjected to thermal cycling reliability testing. Both lead free and Sn-Pb solder joint options have been examined. Weibull failure plots of the recorded failure data have been created, and failure analysis has been performed to identify failure locations and failure modes.
{"title":"Reliability of a CBGA miroproessor package incorpoating a decoupling capacitor array","authors":"J. Roberts, C. Bhat, J. Suhling, R. Jaeger, P. Lall","doi":"10.1109/ITHERM.2016.7517561","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517561","url":null,"abstract":"In this work, the reliability of a novel advanced packaging design for microprocessors has been explored. The new architecture consists of a Ceramic Ball Grid Array (CBGA) package with a flip chip die on a high CTE ceramic substrate, and an array of decoupling capacitors used within the second level interconnects. The capacitors are modified chip capacitors that are soldered immediately beneath the CBGA substrate in a square array that replaces some or all of the ball grid array solder joints. This location for the capacitors improves electrical performance of the microprocessor package (reduces noise/crosstalk and increases speed), and also provides resistance to solder joint collapse. The value of the designs in this investigation is in moving the decoupling capacitive elements of the package closer to the die while having a comparable mechanical reliability to an analogous BGA package. Test assemblies of the new packaging concept containing daisy chain test die have been prepared and subjected to thermal cycling reliability testing. Both lead free and Sn-Pb solder joint options have been examined. Weibull failure plots of the recorded failure data have been created, and failure analysis has been performed to identify failure locations and failure modes.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127960116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517642
J. Maddox, R. Knight, S. Bhavnani, James Pool
An apparatus was developed to measure the local surface temperature, local heat flux, and local heat transfer coefficient for a 3 × 3 array of circular, normal, single-phase liquid water jets impinging on a copper surface. The local thermal measurements were used to obtain the average Nusselt number for the central jet. An angled confining wall was used to manage the spent fluid by maintaining a consistent crossflow momentum ratio with downstream position, which prevents degradation in the thermal performance of downstream jets. A correlation describing the average Nusselt number as a function of jet Reynolds number, Prandtl number, confining wall angle, nozzle to plate spacing, and nozzle pitch for single phase circular water jets is presented.
{"title":"Correlation for single phase liquid jet impingement with an angled confining wall for power electronics cooling","authors":"J. Maddox, R. Knight, S. Bhavnani, James Pool","doi":"10.1109/ITHERM.2016.7517642","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517642","url":null,"abstract":"An apparatus was developed to measure the local surface temperature, local heat flux, and local heat transfer coefficient for a 3 × 3 array of circular, normal, single-phase liquid water jets impinging on a copper surface. The local thermal measurements were used to obtain the average Nusselt number for the central jet. An angled confining wall was used to manage the spent fluid by maintaining a consistent crossflow momentum ratio with downstream position, which prevents degradation in the thermal performance of downstream jets. A correlation describing the average Nusselt number as a function of jet Reynolds number, Prandtl number, confining wall angle, nozzle to plate spacing, and nozzle pitch for single phase circular water jets is presented.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129059997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517651
M. Seiß, T. Mrotzek, T. Hutsch, W. Knabl
Multilayered composites made of molybdenum and copper combine a low coefficient of thermal expansion with a high thermal conductivity. By varying the layer structure, both properties can be tailored to the application requirements. Therefore, these composites are interesting candidates for the thermal management of electronics in general and especially for thermal management of GaN based devices. In this work reliability tests were performed on a three layered structure (Cu-Mo-Cu) with 63 wt% copper according to EN 60068-2-14. The results show that the interface is not degrading by thermal cycling between -40 °C and +125 °C after 2000 cycles. Moreover, no change in thermal conductivity or flatness of the samples was observed. The molybdenum-copper-interface was found to be stable up to the melting point of copper.
{"title":"Properties and reliability of molybdenum-copper-composites for thermal management applications","authors":"M. Seiß, T. Mrotzek, T. Hutsch, W. Knabl","doi":"10.1109/ITHERM.2016.7517651","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517651","url":null,"abstract":"Multilayered composites made of molybdenum and copper combine a low coefficient of thermal expansion with a high thermal conductivity. By varying the layer structure, both properties can be tailored to the application requirements. Therefore, these composites are interesting candidates for the thermal management of electronics in general and especially for thermal management of GaN based devices. In this work reliability tests were performed on a three layered structure (Cu-Mo-Cu) with 63 wt% copper according to EN 60068-2-14. The results show that the interface is not degrading by thermal cycling between -40 °C and +125 °C after 2000 cycles. Moreover, no change in thermal conductivity or flatness of the samples was observed. The molybdenum-copper-interface was found to be stable up to the melting point of copper.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132416588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517656
Pouya Asrar, Xuchen Zhang, Casey D. Woodrum, C. Green, P. Kottke, Thomas E. Sarvey, S. Sitaraman, A. Fedorov, M. Bakir, Y. Joshi
We present an experimental study of two phase flow of refrigerant R245fa in a pin fin enhanced microgap for a range of heat fluxes between 151 W/cm2 to 326 W/cm2. The gap has a base surface area of 1cm × 1cm and height of 200 μm. An array of hydrofoil shaped pin fins covers from bottom to top of the microgap. The pin fins have chord length, longitudinal pitch, and transversal pitch of 75μm, 450μm and 225μm, respectively. On the back side of the chip, four platinum heaters are fabricated and electrically powered in series to enable two phase flow in the microgap, which was part of a pumped flow loop. Heater and surface temperature data were obtained versus heat flux dissipated. Flow visualization was performed using a high speed camera in the heat flux range from 151 W/cm2 to 326 W/cm2. The amount of heat loss across the test section is also provided.
{"title":"Flow boiling of R245fa in a microgap with integrated staggered pin fins","authors":"Pouya Asrar, Xuchen Zhang, Casey D. Woodrum, C. Green, P. Kottke, Thomas E. Sarvey, S. Sitaraman, A. Fedorov, M. Bakir, Y. Joshi","doi":"10.1109/ITHERM.2016.7517656","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517656","url":null,"abstract":"We present an experimental study of two phase flow of refrigerant R245fa in a pin fin enhanced microgap for a range of heat fluxes between 151 W/cm2 to 326 W/cm2. The gap has a base surface area of 1cm × 1cm and height of 200 μm. An array of hydrofoil shaped pin fins covers from bottom to top of the microgap. The pin fins have chord length, longitudinal pitch, and transversal pitch of 75μm, 450μm and 225μm, respectively. On the back side of the chip, four platinum heaters are fabricated and electrically powered in series to enable two phase flow in the microgap, which was part of a pumped flow loop. Heater and surface temperature data were obtained versus heat flux dissipated. Flow visualization was performed using a high speed camera in the heat flux range from 151 W/cm2 to 326 W/cm2. The amount of heat loss across the test section is also provided.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126968113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517671
R. Dhingra, P. Ghoshdastidar
A numerical study of steady, laminar, two-dimensional combined convection and radiation air cooling of four identical rectangular electronic chips (made of silicon) mounted on the left side of a vertical channel is presented in this paper. The conduction in the walls (composed of copper-epoxy) as well as in the chips in which energy is generated due to joule heating is also taken into account. The outside walls are treated as insulated. At the channel inlet the velocity is uniform. The stream function-vorticity-temperature approach with the finite-difference-based methodology has been applied to obtain flow and thermal fields in the fluid, temperature distributions in the chips and the walls, and pressure distribution in the fluid. The parameters varied to study the effect of radiation on the cooling of the silicon chips are: Reynolds number, Grashof number, emissivity of the chips and of the inside wall surfaces, chip height, chip width, and the gap between the successive chips. The energy generation rate is such that it gives rise to average heat flux in the chips in the range of 281.25 W/m2 to 1.875×103 W/m2, which is relatively low. The results reveal that there is a 14.28% drop in the dimensionless maximum temperature of the chips at Re = 500, Gr = 8.65 × 105 as compared to the case when the radiation effect is not considered. The increase in emissivity of the chips from 0.1 to 0.9 results in considerable rise in the temperature of the wall opposite to the chips accompanied by a small drop in the chip temperature. The pumping power increases by 82.69% when the chip height is increased from 0.3 to 0.6. However, increasing the chip width results in rise in pumping power by 30%. There is only a marginal drop in pumping power requirement when radiation is considered in the modeling. The novelty of this work lies in the use of realistic chip and wall materials, investigation of the effect of various geometrical parameters, calculation of pressure distribution and pumping power, and reporting of radiation effect on the walls opposite to the chips. This is only work so far which solves the flow, thermal and pressure fields in electronics cooling using stream function-vorticity-temperature approach and applies Gebhart's absorption factor method for calculation of radiation exchange.
{"title":"A numerical study of the effect of thermal radiation on the forced air cooling of low heat flux electronic chips mounted on one side of a vertical channel","authors":"R. Dhingra, P. Ghoshdastidar","doi":"10.1109/ITHERM.2016.7517671","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517671","url":null,"abstract":"A numerical study of steady, laminar, two-dimensional combined convection and radiation air cooling of four identical rectangular electronic chips (made of silicon) mounted on the left side of a vertical channel is presented in this paper. The conduction in the walls (composed of copper-epoxy) as well as in the chips in which energy is generated due to joule heating is also taken into account. The outside walls are treated as insulated. At the channel inlet the velocity is uniform. The stream function-vorticity-temperature approach with the finite-difference-based methodology has been applied to obtain flow and thermal fields in the fluid, temperature distributions in the chips and the walls, and pressure distribution in the fluid. The parameters varied to study the effect of radiation on the cooling of the silicon chips are: Reynolds number, Grashof number, emissivity of the chips and of the inside wall surfaces, chip height, chip width, and the gap between the successive chips. The energy generation rate is such that it gives rise to average heat flux in the chips in the range of 281.25 W/m2 to 1.875×103 W/m2, which is relatively low. The results reveal that there is a 14.28% drop in the dimensionless maximum temperature of the chips at Re = 500, Gr = 8.65 × 105 as compared to the case when the radiation effect is not considered. The increase in emissivity of the chips from 0.1 to 0.9 results in considerable rise in the temperature of the wall opposite to the chips accompanied by a small drop in the chip temperature. The pumping power increases by 82.69% when the chip height is increased from 0.3 to 0.6. However, increasing the chip width results in rise in pumping power by 30%. There is only a marginal drop in pumping power requirement when radiation is considered in the modeling. The novelty of this work lies in the use of realistic chip and wall materials, investigation of the effect of various geometrical parameters, calculation of pressure distribution and pumping power, and reporting of radiation effect on the walls opposite to the chips. This is only work so far which solves the flow, thermal and pressure fields in electronics cooling using stream function-vorticity-temperature approach and applies Gebhart's absorption factor method for calculation of radiation exchange.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131414882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517683
A. Raj, S. Thirugnanasambandam, T. Sanders, S. Sridhar, Seth Gordon, John L. Evans, F. Megahed, M. Bozack, W. Johnson, Mark Carpenter
In this experiment, the thermal performance of various lead-free doped solder paste alloys on leaded and leadless packages on laminate substrates were investigated. The Primary Goal of this test is to find a manufactureable solder paste that will mitigate the effects of aging on lead free solder joints. The results discuss the effects of different paste materials, the effects of doping level, and reflow profile on the resulting reliability of a variety of surface mount components. The test vehicle consists of 35 mm (PBGA 1156), 31mm (SBGA 304), 15 mm (CABGA 208) and 6mm (CABGA 36) ball grid array packages with 1.0 mm, 1.27mm and 0.8mm pitch, respectively. Additionally, a leadless 5mm QFN package (MLF 20) with 0.65mm pitch and 2512 SMRs are included in order to understand the effect of doped solder paste on conventional packages. The test boards are built with (a) three different reflow profiles on 6 mil stencil thickness, and (b) one reflow profile on a 4 mil stencil thickness, to study the differences in doping volume effects of the new doped alloys. The test vehicles were subjected to high temperature accelerated life test (HALT) in liquid shock (thermal shock) testing. Each test vehicle underwent 3000 thermal cycles with peak temperatures of -40°C to +125°C on a 15-minute thermal profile (5 minutes dwell time and 2.5 minutes transition time). Reliability of the test packages were determined from the ability of the components and solder interconnects to withstand the thermal stresses induced by alternating high and low temperature extremes. The time to failure were right censored after 3000 cycles. The experimental variables include paste materials, solder paste manufacturer, Reflow profile, stencil thickness, packages and component solder sphere. The response variable used in this test is Time to Failure (cycles). The effect of experimental variables on Time to Failure were assessed at 5% level of significance using Proportional Hazard Model. It is found that all the experimental variables except reflow profile have significant impact on the Time to Failure. Since this experimental data consists of heavy censoring, Censored Quantile Regression model is developed and it is compared with Proportional Hazard Model.
{"title":"Proportional Hazard Model of doped low creep lead free solder paste under thermal shock","authors":"A. Raj, S. Thirugnanasambandam, T. Sanders, S. Sridhar, Seth Gordon, John L. Evans, F. Megahed, M. Bozack, W. Johnson, Mark Carpenter","doi":"10.1109/ITHERM.2016.7517683","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517683","url":null,"abstract":"In this experiment, the thermal performance of various lead-free doped solder paste alloys on leaded and leadless packages on laminate substrates were investigated. The Primary Goal of this test is to find a manufactureable solder paste that will mitigate the effects of aging on lead free solder joints. The results discuss the effects of different paste materials, the effects of doping level, and reflow profile on the resulting reliability of a variety of surface mount components. The test vehicle consists of 35 mm (PBGA 1156), 31mm (SBGA 304), 15 mm (CABGA 208) and 6mm (CABGA 36) ball grid array packages with 1.0 mm, 1.27mm and 0.8mm pitch, respectively. Additionally, a leadless 5mm QFN package (MLF 20) with 0.65mm pitch and 2512 SMRs are included in order to understand the effect of doped solder paste on conventional packages. The test boards are built with (a) three different reflow profiles on 6 mil stencil thickness, and (b) one reflow profile on a 4 mil stencil thickness, to study the differences in doping volume effects of the new doped alloys. The test vehicles were subjected to high temperature accelerated life test (HALT) in liquid shock (thermal shock) testing. Each test vehicle underwent 3000 thermal cycles with peak temperatures of -40°C to +125°C on a 15-minute thermal profile (5 minutes dwell time and 2.5 minutes transition time). Reliability of the test packages were determined from the ability of the components and solder interconnects to withstand the thermal stresses induced by alternating high and low temperature extremes. The time to failure were right censored after 3000 cycles. The experimental variables include paste materials, solder paste manufacturer, Reflow profile, stencil thickness, packages and component solder sphere. The response variable used in this test is Time to Failure (cycles). The effect of experimental variables on Time to Failure were assessed at 5% level of significance using Proportional Hazard Model. It is found that all the experimental variables except reflow profile have significant impact on the Time to Failure. Since this experimental data consists of heavy censoring, Censored Quantile Regression model is developed and it is compared with Proportional Hazard Model.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"41 166","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132476936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517581
H. Erden, M. Yildirim, M. Koz, H. Khalifa
Temperature non-uniformities in traditional data centers can be eliminated or at least reduced by utilizing containment systems. As all servers receive the same inlet air temperature in a contained configuration, the cooling system can be operated more efficiently at a higher temperature, which also increases the potential for free cooling through various economizer modes. However, enclosed aisle configurations require computer room air handler (CRAH) fans to operate at a higher speed and provide entire rack air flow through the perforated tiles, unlike open aisle data centers that can make up a fraction of server air from the data center air space. Hence, the traditional enclosed aisle configuration is likely to consume more fan power. This study confirms that enclosing the aisle does not guarantee optimum cooling infrastructure power in air cooled data centers. Proposed CRAH bypass configuration for enclosed aisle data centers provides a fraction of the tile airflow rate through a set of bypass fans while CRAH fans operate at lower speeds. These low-lift fans operate across a pressure difference between the room and plenum, which is significantly less than the flow resistance of CRAH units. Meanwhile, CRAH fans operate at lower speeds and consume less energy. Accordingly, a certain bypass air fraction with respect to total rack air flow rate leads to a minimum cooling infrastructure power for a particular configuration. This study investigates energy savings potential of the enclosed aisle data centers with CRAH bypass configuration utilizing a calibrated flow network model for estimating the energy consumption of air movers as well as a thermodynamic modeling tool to evaluate the off-design performance of major components of data center cooling infrastructure. Hour-by-hour annual energy simulations complement the energy assessment for 7 U.S. cities considering indirect air side economizer operation.
{"title":"Energy assessment of CRAH bypass for enclosed aisle data centers","authors":"H. Erden, M. Yildirim, M. Koz, H. Khalifa","doi":"10.1109/ITHERM.2016.7517581","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517581","url":null,"abstract":"Temperature non-uniformities in traditional data centers can be eliminated or at least reduced by utilizing containment systems. As all servers receive the same inlet air temperature in a contained configuration, the cooling system can be operated more efficiently at a higher temperature, which also increases the potential for free cooling through various economizer modes. However, enclosed aisle configurations require computer room air handler (CRAH) fans to operate at a higher speed and provide entire rack air flow through the perforated tiles, unlike open aisle data centers that can make up a fraction of server air from the data center air space. Hence, the traditional enclosed aisle configuration is likely to consume more fan power. This study confirms that enclosing the aisle does not guarantee optimum cooling infrastructure power in air cooled data centers. Proposed CRAH bypass configuration for enclosed aisle data centers provides a fraction of the tile airflow rate through a set of bypass fans while CRAH fans operate at lower speeds. These low-lift fans operate across a pressure difference between the room and plenum, which is significantly less than the flow resistance of CRAH units. Meanwhile, CRAH fans operate at lower speeds and consume less energy. Accordingly, a certain bypass air fraction with respect to total rack air flow rate leads to a minimum cooling infrastructure power for a particular configuration. This study investigates energy savings potential of the enclosed aisle data centers with CRAH bypass configuration utilizing a calibrated flow network model for estimating the energy consumption of air movers as well as a thermodynamic modeling tool to evaluate the off-design performance of major components of data center cooling infrastructure. Hour-by-hour annual energy simulations complement the energy assessment for 7 U.S. cities considering indirect air side economizer operation.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"599 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131798585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517584
P. Lall, Nakul Kothari, J. Foley, John Deep, Ryan Lowe
Densely packed electrical assemblies like fuze, contain large number of components, potted in protective adhesives. The number of components, varying material types, irregular geometry of the components and the geometric details of the assembly makes conventional CAD modeling, meshing and Finite Element(FE) modeling of these large assemblies extremely time consuming, often, to the extent of being impractical. CAD geometries compatible with modern Finite Element (FE) platforms may not be available for several legacy systems. Furthermore, conventional CAD modeling may not account for the real geometry realized after the manufacturing process and this can often affect the fidelity of the FE model. There is no method for capturing the actual assembly geometry and its embedded components. Assessment of survivability of fuzes requires assessment of stresses and strains under operational loads. Previously, researchers have studied the reliability of key components in a fuze device subjected to high temperature and high g mechanical shocks [1]. Researchers have measured redundancy and reliability of fuze electronics using failure rates and mean time to failure as per MIL-HDBK-217F standard [2]. There is little to no literature on FE modeling of a comprehensive fuze assembly. In this paper, a methodology for the creation of an FE model based on Micro-CT (Computed Tomography) data is presented. The method has been applied to an actual fuze subjected to mechanical shock. This method involves usage of advanced 3D imaging, image segmentation, image filtering and meshing techniques to directly convert CT scanned electrical assemblies into a FE mesh. This method successfully bypasses the time consuming CAD modeling step of conventional FE modeling. The as-is geometry of each component, positioned accurately in a 3D space, as per the original assembly, has been realized in this process by usage of micro-CT scanning technique. The submicron scale tolerances of the CT scanned data ensure true representation of the fuze assembly, in this case. The FE model thus realized, allows for measurement of all the field variables, anywhere over its meshed domain. Stress and strain histories have been extracted for embedded components of the fuze assembly using explicit finite element models.
{"title":"A novel Micro-CT data based Finite Element Modeling technique to study reliability of densely packed fuze assemblies","authors":"P. Lall, Nakul Kothari, J. Foley, John Deep, Ryan Lowe","doi":"10.1109/ITHERM.2016.7517584","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517584","url":null,"abstract":"Densely packed electrical assemblies like fuze, contain large number of components, potted in protective adhesives. The number of components, varying material types, irregular geometry of the components and the geometric details of the assembly makes conventional CAD modeling, meshing and Finite Element(FE) modeling of these large assemblies extremely time consuming, often, to the extent of being impractical. CAD geometries compatible with modern Finite Element (FE) platforms may not be available for several legacy systems. Furthermore, conventional CAD modeling may not account for the real geometry realized after the manufacturing process and this can often affect the fidelity of the FE model. There is no method for capturing the actual assembly geometry and its embedded components. Assessment of survivability of fuzes requires assessment of stresses and strains under operational loads. Previously, researchers have studied the reliability of key components in a fuze device subjected to high temperature and high g mechanical shocks [1]. Researchers have measured redundancy and reliability of fuze electronics using failure rates and mean time to failure as per MIL-HDBK-217F standard [2]. There is little to no literature on FE modeling of a comprehensive fuze assembly. In this paper, a methodology for the creation of an FE model based on Micro-CT (Computed Tomography) data is presented. The method has been applied to an actual fuze subjected to mechanical shock. This method involves usage of advanced 3D imaging, image segmentation, image filtering and meshing techniques to directly convert CT scanned electrical assemblies into a FE mesh. This method successfully bypasses the time consuming CAD modeling step of conventional FE modeling. The as-is geometry of each component, positioned accurately in a 3D space, as per the original assembly, has been realized in this process by usage of micro-CT scanning technique. The submicron scale tolerances of the CT scanned data ensure true representation of the fuze assembly, in this case. The FE model thus realized, allows for measurement of all the field variables, anywhere over its meshed domain. Stress and strain histories have been extracted for embedded components of the fuze assembly using explicit finite element models.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121361913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517727
T. R. Harris, G. Pavlidis, Eric J. Wyers, D. Marshal Newberry, S. Graham, P. Franzon, W. R. Davis
Thermal management and planning is important for heterogeneous integration due to the introduction of a complex thermal path. Thermal measurement of operating devices provides necessary data points for future design as well as validation of models. In this paper, two methods for measuring thermal performance of DAHI (Diverse Accessible Heterogeneous Integration) GaN HEMTs are presented and contrasted: IR microscopy and micro Raman spectroscopy. The QFI IR system uses a per-pixel material emissivity flat temperature calibration when the device is in an off-state, and then calculates operating temperatures by CCD exposure. Two separate QFI systems with differing CCD resolutions were used to collect thermal data and are compared. Raman Thermometry by contrast, is a laser point measurement of the frequency shift in scattered photons due to phonon vibrational modes whose frequencies are temperature dependent. Differences in measurements between the two methods arising from the stack of materials used in the DAHI process and their transparency are discussed. A method for measuring the surface temperature of the devices through Raman by the use of TiO2 nanoparticles is also presented in conjunction with a profile of the HEMT. Measurements are presented alongside thermal simulation results using prototype software Mentor Graphics™ Calibre®.
{"title":"Thermal raman and IR measurement of heterogeneous integration stacks","authors":"T. R. Harris, G. Pavlidis, Eric J. Wyers, D. Marshal Newberry, S. Graham, P. Franzon, W. R. Davis","doi":"10.1109/ITHERM.2016.7517727","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517727","url":null,"abstract":"Thermal management and planning is important for heterogeneous integration due to the introduction of a complex thermal path. Thermal measurement of operating devices provides necessary data points for future design as well as validation of models. In this paper, two methods for measuring thermal performance of DAHI (Diverse Accessible Heterogeneous Integration) GaN HEMTs are presented and contrasted: IR microscopy and micro Raman spectroscopy. The QFI IR system uses a per-pixel material emissivity flat temperature calibration when the device is in an off-state, and then calculates operating temperatures by CCD exposure. Two separate QFI systems with differing CCD resolutions were used to collect thermal data and are compared. Raman Thermometry by contrast, is a laser point measurement of the frequency shift in scattered photons due to phonon vibrational modes whose frequencies are temperature dependent. Differences in measurements between the two methods arising from the stack of materials used in the DAHI process and their transparency are discussed. A method for measuring the surface temperature of the devices through Raman by the use of TiO2 nanoparticles is also presented in conjunction with a profile of the HEMT. Measurements are presented alongside thermal simulation results using prototype software Mentor Graphics™ Calibre®.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116026207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517600
J. Marcinichen, N. Lamaison, C. L. Ong, J. Thome
In the present study, a simulation code specifically developed to evaluate the thermal-hydraulic performance of thermosyphon cooling loops is validated through the experimental results obtained in the Part 1. It considers levels of heat load conventionally observed in real servers of datacenters, which means idle, normal and maximum clock speed of actual microprocessors. The thermosyphon is a very compact unit with a height of 15 cm and capable of safely operating up to a heat flux of 80 W cm-2. The loop basically is comprised of a riser, a downcomer, a micro-evaporator and a counter flow tube-in-tube condenser. The latter is cooled by cold water whose mass flow rate can be controlled through an external pump (speed control), so that parameters such as saturation temperature and/or condenser outlet subcooling can be adjusted for a pre-defined set point, and thus increasing the range of operability of the cooling loop. Other parameters were also explored experimentally, cooling looping overall performance, chip (junction) temperature, whilst the critical heat flux was estimated from a leading CHF method. Finally, the study showed that the passive two-phase closed loop thermosyphon cooling system is a safe and energetically viable technology solution for the next generation of datacenters.
{"title":"Two-phase mini-thermosyphon electronics cooling, Part 2: Model and steady-state validations","authors":"J. Marcinichen, N. Lamaison, C. L. Ong, J. Thome","doi":"10.1109/ITHERM.2016.7517600","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517600","url":null,"abstract":"In the present study, a simulation code specifically developed to evaluate the thermal-hydraulic performance of thermosyphon cooling loops is validated through the experimental results obtained in the Part 1. It considers levels of heat load conventionally observed in real servers of datacenters, which means idle, normal and maximum clock speed of actual microprocessors. The thermosyphon is a very compact unit with a height of 15 cm and capable of safely operating up to a heat flux of 80 W cm-2. The loop basically is comprised of a riser, a downcomer, a micro-evaporator and a counter flow tube-in-tube condenser. The latter is cooled by cold water whose mass flow rate can be controlled through an external pump (speed control), so that parameters such as saturation temperature and/or condenser outlet subcooling can be adjusted for a pre-defined set point, and thus increasing the range of operability of the cooling loop. Other parameters were also explored experimentally, cooling looping overall performance, chip (junction) temperature, whilst the critical heat flux was estimated from a leading CHF method. Finally, the study showed that the passive two-phase closed loop thermosyphon cooling system is a safe and energetically viable technology solution for the next generation of datacenters.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116950256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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