Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517572
S. Adera, D. Antao, R. Raj, E. Wang
The emerging three-dimensional vertical chip stacking architecture is expected to reduce form factor and improve performance by providing energy efficient chip design. However, increased power density and non-uniform heat generation in stacked dies offset its advantages and pose a significant thermal management challenge by creating hotspots where heat loads in excess of 1 kW/cm2 are generated from sub-millimeter areas. Furthermore, the localized heating in hotspots creates high junction temperature which can degrade the performance, reliability, and life time of electronic chips. Such ultra-high heat fluxes are challenging to remove using state-of-the-art single-phase cooling technology. Consequently, chip-level phase-change based hotspot thermal management is increasingly becoming pivotal for cooling next-generation of microelectronic devices and power amplifiers. This work experimentally characterizes capillary-limited thin-film evaporation from well-defined silicon micropillar wicks to demonstrate its potential as a thermal solution for ultra-high heat fluxes. We used contact photolithography and deep-reactive-ion-etching to create a 1×1 cm2 microstructured area. The microstructured area was surrounded by a water reservoir. Various sized thin-film heaters which were created using electron-beam evaporation and acetone lift-off were integrated on the backside of the test sample. Hotspots were emulated by locally heating a 640×620 μm2 area while background heating was emulated by heating the entire 1×1 cm2 microstructured area. The background and hotspot heaters were calibrated prior to experiment to measure temperature. All experiments were conducted in an environmental chamber which was maintained near saturated condition, i.e., saturation temperature and corresponding pressure. The working fluid, degassed de-ionized water, was transported from the surrounding water reservoir to the microstructured area passively via capillary-wicking. We dissipated ≈5.8 kW/cm2 from a 620×640 μm2 footprint when the hotspot temperature was ≈260 °C. Most importantly, when the surface dried out at ≈5.8 kW/cm2, the background temperature as well as the local temperatures 3 mm away from the hotspot were less than 50 °C. Increasing the heat flux beyond ≈5.8 kW/cm2 resulted in the formation of a dry island at the center of the hotspot which grew radially outwards. Dryout and thermal runaway occurred when viscous losses exceed the capillary pressure. Furthermore, the maximum dryout heat flux from a single hotspot decreased from ≈5.8 kW/cm2 to ≈2.9 kW/cm2 when the hotspot was assisted by a 20 W/cm2 background heating. Lastly, the dryout heat flux decreased from ≈5.8 kW/cm2 to ≈2.9 kW/cm2 per heater when three spatially distributed hotspots were created concurrently. Unlike the dryout heat flux, the total heating power increased by assisting hotspot with background heating as well as by creating spatially distributed concurrent hotspots over the microstructured area.
{"title":"Hotspot thermal management via thin-film evaporation","authors":"S. Adera, D. Antao, R. Raj, E. Wang","doi":"10.1109/ITHERM.2016.7517572","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517572","url":null,"abstract":"The emerging three-dimensional vertical chip stacking architecture is expected to reduce form factor and improve performance by providing energy efficient chip design. However, increased power density and non-uniform heat generation in stacked dies offset its advantages and pose a significant thermal management challenge by creating hotspots where heat loads in excess of 1 kW/cm2 are generated from sub-millimeter areas. Furthermore, the localized heating in hotspots creates high junction temperature which can degrade the performance, reliability, and life time of electronic chips. Such ultra-high heat fluxes are challenging to remove using state-of-the-art single-phase cooling technology. Consequently, chip-level phase-change based hotspot thermal management is increasingly becoming pivotal for cooling next-generation of microelectronic devices and power amplifiers. This work experimentally characterizes capillary-limited thin-film evaporation from well-defined silicon micropillar wicks to demonstrate its potential as a thermal solution for ultra-high heat fluxes. We used contact photolithography and deep-reactive-ion-etching to create a 1×1 cm2 microstructured area. The microstructured area was surrounded by a water reservoir. Various sized thin-film heaters which were created using electron-beam evaporation and acetone lift-off were integrated on the backside of the test sample. Hotspots were emulated by locally heating a 640×620 μm2 area while background heating was emulated by heating the entire 1×1 cm2 microstructured area. The background and hotspot heaters were calibrated prior to experiment to measure temperature. All experiments were conducted in an environmental chamber which was maintained near saturated condition, i.e., saturation temperature and corresponding pressure. The working fluid, degassed de-ionized water, was transported from the surrounding water reservoir to the microstructured area passively via capillary-wicking. We dissipated ≈5.8 kW/cm2 from a 620×640 μm2 footprint when the hotspot temperature was ≈260 °C. Most importantly, when the surface dried out at ≈5.8 kW/cm2, the background temperature as well as the local temperatures 3 mm away from the hotspot were less than 50 °C. Increasing the heat flux beyond ≈5.8 kW/cm2 resulted in the formation of a dry island at the center of the hotspot which grew radially outwards. Dryout and thermal runaway occurred when viscous losses exceed the capillary pressure. Furthermore, the maximum dryout heat flux from a single hotspot decreased from ≈5.8 kW/cm2 to ≈2.9 kW/cm2 when the hotspot was assisted by a 20 W/cm2 background heating. Lastly, the dryout heat flux decreased from ≈5.8 kW/cm2 to ≈2.9 kW/cm2 per heater when three spatially distributed hotspots were created concurrently. Unlike the dryout heat flux, the total heating power increased by assisting hotspot with background heating as well as by creating spatially distributed concurrent hotspots over the microstructured area.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133254747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517533
Yaqin Song, R. Abbaspour, M. Bakir, S. Sitaraman
In this paper, we have studied the microstructure evolution of one-year room-temperature-aged Through-Silicon Via (TSV) copper after annealing the TSV samples at 300 °C, 400 °C and 500 °C for 180 minutes. Hardness and elastic modulus values are obtained by using nano-indentation technique. The hardness and elastic modulus values decrease as annealing temperature increases. The microstructure of copper (Cu) is examined to obtain grain size and texture, using electron backscatter diffraction (EBSD). Copper grain growth, if any, is studied under different annealing temperatures. There was no observable grain growth for the annealing temperatures studied in this work. Moreover, microstructure variation at different locations within a Cu TSV is also studied.
{"title":"Thermal annealing effects on copper microstructure in Through-Silicon-Vias","authors":"Yaqin Song, R. Abbaspour, M. Bakir, S. Sitaraman","doi":"10.1109/ITHERM.2016.7517533","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517533","url":null,"abstract":"In this paper, we have studied the microstructure evolution of one-year room-temperature-aged Through-Silicon Via (TSV) copper after annealing the TSV samples at 300 °C, 400 °C and 500 °C for 180 minutes. Hardness and elastic modulus values are obtained by using nano-indentation technique. The hardness and elastic modulus values decrease as annealing temperature increases. The microstructure of copper (Cu) is examined to obtain grain size and texture, using electron backscatter diffraction (EBSD). Copper grain growth, if any, is studied under different annealing temperatures. There was no observable grain growth for the annealing temperatures studied in this work. Moreover, microstructure variation at different locations within a Cu TSV is also studied.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133695121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517574
Miguel Moura, E. Teodori, A. Moita, A. Moreira
The present work addresses a microprocessor cooling technique based on pool boiling of a dielectric fluid, HFE-7000 with a compact closed loop thermosyphon, which requires no pumping or auxiliary components to operate. Aiming at modern desktop CPU cooling, the devised system is modular to infer on the optimization of several parameters influencing the system performance. The evaporator bottom surface is enhanced with micro-structured cavities to increase the liquid/solid contact area and optimize nucleation and bubble dynamics within the heterogeneous nucleation process. Optimization of surface structuring must account for several interaction mechanisms and assure that the flow near the surface maximizes the heat transfer mechanisms present in pool boiling heat transfer. This optimization is based on the minimization of steady-state overall thermal resistance of the system and on transient power conditions to control the onset of nucleate boiling and the inherent temperature overshoot upon regime transition at start-up. The condenser tilt angle is optimized as well as the effect of evaporator dimensions, orientation (horizontal and vertical positioning) and liquid fill charges. Based on the outcomes of this exploratory research, a cooling system is implemented in a working computer, cooling a modern CPU, mounted vertically.
{"title":"2 phase microprocessor cooling system with controlled pool boiling of dielectrics over micro-and-nano structured Integrated Heat Spreaders","authors":"Miguel Moura, E. Teodori, A. Moita, A. Moreira","doi":"10.1109/ITHERM.2016.7517574","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517574","url":null,"abstract":"The present work addresses a microprocessor cooling technique based on pool boiling of a dielectric fluid, HFE-7000 with a compact closed loop thermosyphon, which requires no pumping or auxiliary components to operate. Aiming at modern desktop CPU cooling, the devised system is modular to infer on the optimization of several parameters influencing the system performance. The evaporator bottom surface is enhanced with micro-structured cavities to increase the liquid/solid contact area and optimize nucleation and bubble dynamics within the heterogeneous nucleation process. Optimization of surface structuring must account for several interaction mechanisms and assure that the flow near the surface maximizes the heat transfer mechanisms present in pool boiling heat transfer. This optimization is based on the minimization of steady-state overall thermal resistance of the system and on transient power conditions to control the onset of nucleate boiling and the inherent temperature overshoot upon regime transition at start-up. The condenser tilt angle is optimized as well as the effect of evaporator dimensions, orientation (horizontal and vertical positioning) and liquid fill charges. Based on the outcomes of this exploratory research, a cooling system is implemented in a working computer, cooling a modern CPU, mounted vertically.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131790350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517713
P. Parida, T. Chainer
Chip-embedded micrometer scale two-phase cooling technology can be essential to fully optimize the benefits of improved integration density of three-dimensional (3D) stacking in high performance integrated circuits (ICs) for future computing systems; but is faced with significant developmental challenges including high fidelity modeling. In the present work, an Eulerian multiphase model has been developed for simulating two-phase evaporative cooling through chip embedded microscale cavities populated with pin-fins. First the model is used to predict the flow and heat transfer characteristics for coolant R1234ze flowing through a two-port ~10 mm long micro-cavity populated with 80 μm diameter pin-fins arranged in an in-line manner. The flow is sub-cooled in the initial section of the cavity and saturated in the remaining. The results were compared to experimental data available from fundamental experiments, focusing on the model capability to predict the correct flow pattern, temperature profile and pressure drop.
{"title":"Eulerian multiphase conjugate model development and validation for flow boiling in micro-pin field","authors":"P. Parida, T. Chainer","doi":"10.1109/ITHERM.2016.7517713","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517713","url":null,"abstract":"Chip-embedded micrometer scale two-phase cooling technology can be essential to fully optimize the benefits of improved integration density of three-dimensional (3D) stacking in high performance integrated circuits (ICs) for future computing systems; but is faced with significant developmental challenges including high fidelity modeling. In the present work, an Eulerian multiphase model has been developed for simulating two-phase evaporative cooling through chip embedded microscale cavities populated with pin-fins. First the model is used to predict the flow and heat transfer characteristics for coolant R1234ze flowing through a two-port ~10 mm long micro-cavity populated with 80 μm diameter pin-fins arranged in an in-line manner. The flow is sub-cooled in the initial section of the cavity and saturated in the remaining. The results were compared to experimental data available from fundamental experiments, focusing on the model capability to predict the correct flow pattern, temperature profile and pressure drop.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134136514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517648
M. Razavi, Y. Muzychka, S. Kocabiyik
Temperature profile of electronic devices is one of the key factors that should be considered for designing an effective thermal management system. In this paper, an analytical solution for temperature distribution of a circular flux tube is presented. The boundary conditions along the source plane are specified as arbitrary temperatures and adiabatic. The boundary condition along the sink plane is convective cooling and the boundary condition along the walls is adiabatic. For solving the governing equation, the method of separation of variables and the least squares method are used. A case study is presented and the results are compared with the Finite Element Method (FEM). This analytical solution helps thermal engineers to have a better understanding of the thermal behavior of electronic devices.
{"title":"Temperature distribution in a circular flux tube with arbitrary specified contact temperatures","authors":"M. Razavi, Y. Muzychka, S. Kocabiyik","doi":"10.1109/ITHERM.2016.7517648","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517648","url":null,"abstract":"Temperature profile of electronic devices is one of the key factors that should be considered for designing an effective thermal management system. In this paper, an analytical solution for temperature distribution of a circular flux tube is presented. The boundary conditions along the source plane are specified as arbitrary temperatures and adiabatic. The boundary condition along the sink plane is convective cooling and the boundary condition along the walls is adiabatic. For solving the governing equation, the method of separation of variables and the least squares method are used. A case study is presented and the results are compared with the Finite Element Method (FEM). This analytical solution helps thermal engineers to have a better understanding of the thermal behavior of electronic devices.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"72 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114008966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517576
D. Hackenberg, M. Patterson
The rate of innovation in IT system design and especially in High Performance Computing continues to be very high. To keep pace TU Dresden has constructed its new data center using the Plenum concept. The traditional raised floor was substituted by a full building story, creating a highly flexible space to transport power, water, and air. A strict hot-aisle air separation is used and the computer room air-handling (CRAH) units in downflow configuration are positioned directly beneath the hot aisles. This unique arrangement necessitates an unconventional downward flow of hot air from the enclosed hot aisle. Extensive testing has been performed in a cluster of 24 racks (12 per side) equipped with (3+1)×100 kW CRAH unit cooling capacity and 60 test fixtures (air heaters) with 5-15 kW heating power each. Our analysis demonstrates the extremely high efficiency of this air cooling concept even in high-density configurations, up to at least 30 kW per rack. This efficiency is mostly due to the very short airflow paths and wide open cross-sections. We also showcase that no malicious thermal stratification occurs in our hot air downflow configuration. A detailed analysis of the CRAH controls for temperature (through cooling water flow modulation) and airflow (fan speed) highlights the challenges of such control systems in enclosed hot aisle configurations at high power density and short feedback loops. The analysis also considers dynamically changing load patterns including very low partial load scenarios and aspects of operational reliability.
{"title":"Evaluation of a new data center air-cooling architecture: The down-flow Plenum","authors":"D. Hackenberg, M. Patterson","doi":"10.1109/ITHERM.2016.7517576","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517576","url":null,"abstract":"The rate of innovation in IT system design and especially in High Performance Computing continues to be very high. To keep pace TU Dresden has constructed its new data center using the Plenum concept. The traditional raised floor was substituted by a full building story, creating a highly flexible space to transport power, water, and air. A strict hot-aisle air separation is used and the computer room air-handling (CRAH) units in downflow configuration are positioned directly beneath the hot aisles. This unique arrangement necessitates an unconventional downward flow of hot air from the enclosed hot aisle. Extensive testing has been performed in a cluster of 24 racks (12 per side) equipped with (3+1)×100 kW CRAH unit cooling capacity and 60 test fixtures (air heaters) with 5-15 kW heating power each. Our analysis demonstrates the extremely high efficiency of this air cooling concept even in high-density configurations, up to at least 30 kW per rack. This efficiency is mostly due to the very short airflow paths and wide open cross-sections. We also showcase that no malicious thermal stratification occurs in our hot air downflow configuration. A detailed analysis of the CRAH controls for temperature (through cooling water flow modulation) and airflow (fan speed) highlights the challenges of such control systems in enclosed hot aisle configurations at high power density and short feedback loops. The analysis also considers dynamically changing load patterns including very low partial load scenarios and aspects of operational reliability.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517670
Chuan Sun, Nuttawut Lewpiriyawong, Kent Loong Khoo, P. Lee, S. Chou
As the air-side heat transfer is controlling the efficiency of finned tube heat exchanger (FTHX), this makes its enhancement important. After analyzing the thermal hydraulic performance of conventional plain plate fin, two novel air-side fin configurations are proposed. The first design guides more airflow into the back of the tubes and eliminates wake zones. The second design significantly enlarges the heat transfer area of air-side with little pressure drop penalty. Numerical investigations of conventional and novel fin designs are conducted. Based on the temperature and velocity flow fields and Nusselt number (Nu), the two novel designs are repeatedly improved. Comparing Nu and friction factor (f) with the plain plate fin, the two novel fin designs enhance the overall thermal performance by 103.1-109.0% and 64.5-78.4% respectively, while incurring pressure drop penalty of 312.8-419.6% and (- 1.5)-6.0% respectively. As such, the proposed enhanced air-side fin designs are promising candidates for improving the efficiency for FTHXs.
{"title":"Numerical modeling and thermal enhancement of finned tube heat exchanger with guiding channel and fusiform configurations","authors":"Chuan Sun, Nuttawut Lewpiriyawong, Kent Loong Khoo, P. Lee, S. Chou","doi":"10.1109/ITHERM.2016.7517670","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517670","url":null,"abstract":"As the air-side heat transfer is controlling the efficiency of finned tube heat exchanger (FTHX), this makes its enhancement important. After analyzing the thermal hydraulic performance of conventional plain plate fin, two novel air-side fin configurations are proposed. The first design guides more airflow into the back of the tubes and eliminates wake zones. The second design significantly enlarges the heat transfer area of air-side with little pressure drop penalty. Numerical investigations of conventional and novel fin designs are conducted. Based on the temperature and velocity flow fields and Nusselt number (Nu), the two novel designs are repeatedly improved. Comparing Nu and friction factor (f) with the plain plate fin, the two novel fin designs enhance the overall thermal performance by 103.1-109.0% and 64.5-78.4% respectively, while incurring pressure drop penalty of 312.8-419.6% and (- 1.5)-6.0% respectively. As such, the proposed enhanced air-side fin designs are promising candidates for improving the efficiency for FTHXs.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124939911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517610
T. Jiang, Eungkyu Lee, M. Young, T. Luo
The efficiency of thermal transport across the interfaces presents large challenges for modern technologies such as thermal management of electronics. In this paper, we report significant enhancement of thermal transport across solid interfaces by nanopatterning the surface. We utilized nanopillars as the analogy of fins that have been used for macroscopic heat transfer enhancement in heat exchangers. We found that the major benefit sterns from the enlarged effective contact area due to the increased surface area of the nanopatterned surface. The finding from this work should be universal and can benefit the thermal management of electronics, especially high power electronics where self-heating has been a bottleneck for their further advancement.
{"title":"Nanostructure-enabled significant thermal transport enhancement across solid interfaces","authors":"T. Jiang, Eungkyu Lee, M. Young, T. Luo","doi":"10.1109/ITHERM.2016.7517610","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517610","url":null,"abstract":"The efficiency of thermal transport across the interfaces presents large challenges for modern technologies such as thermal management of electronics. In this paper, we report significant enhancement of thermal transport across solid interfaces by nanopatterning the surface. We utilized nanopillars as the analogy of fins that have been used for macroscopic heat transfer enhancement in heat exchangers. We found that the major benefit sterns from the enlarged effective contact area due to the increased surface area of the nanopatterned surface. The finding from this work should be universal and can benefit the thermal management of electronics, especially high power electronics where self-heating has been a bottleneck for their further advancement.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123650081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517577
S. Araya, Gerard F. Jones, A. Fleischer
The growing demand for data center utilization and the resulting increases in energy requirements are creating significant challenges for data center operators and for thermal designers. Design options which can cool the servers efficiently while also reducing electricity usage are thus of considerable interest. One potential technique is the use of Organic Rankine Cycle (ORC) technology which can absorb the server heat into an organic fluid and then use this heat in a power cycle to create electricity. The ORC has been found to match well with data center requirements and this paper presents the analysis of an ORC system matched with data center operating conditions and the design of an ORC test bed. The ORC test bed is designed for 20kW of waste heat collected from 2 full racks. The complete design includes the ORC power cycle and one secondary cycle as heat source. Component selection has been carefully studied in each of the two cycles. The main goals of this investigation are the steady-state characterization of an ORC under different data center operating conditions and the design of a test bed which will prove out the concept of mating ORC with data center conditions for potential customers who are seeking alternatives for data center waste heat recovery.
{"title":"The design and construction of a bench-top Organic Rankine Cycle for data center applications","authors":"S. Araya, Gerard F. Jones, A. Fleischer","doi":"10.1109/ITHERM.2016.7517577","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517577","url":null,"abstract":"The growing demand for data center utilization and the resulting increases in energy requirements are creating significant challenges for data center operators and for thermal designers. Design options which can cool the servers efficiently while also reducing electricity usage are thus of considerable interest. One potential technique is the use of Organic Rankine Cycle (ORC) technology which can absorb the server heat into an organic fluid and then use this heat in a power cycle to create electricity. The ORC has been found to match well with data center requirements and this paper presents the analysis of an ORC system matched with data center operating conditions and the design of an ORC test bed. The ORC test bed is designed for 20kW of waste heat collected from 2 full racks. The complete design includes the ORC power cycle and one secondary cycle as heat source. Component selection has been carefully studied in each of the two cycles. The main goals of this investigation are the steady-state characterization of an ORC under different data center operating conditions and the design of a test bed which will prove out the concept of mating ORC with data center conditions for potential customers who are seeking alternatives for data center waste heat recovery.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121899526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-01DOI: 10.1109/ITHERM.2016.7517526
K. Tunga, T. Wassick, L. Guerin, Maryse Cournoyer
Fine pitch interconnects combined with 2.5D/3D packaging technology offers enormous potential towards decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased stresses within the Far Back End of Line (FBEOL) and Back End of Line (BEOL) layers within the chip are the primary concerns. Several 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between -55°C and 125°C. Finite-element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad inter face. Experimental data in conjunction with mechanical modeling was used to determine a safe level of stress at the aluminum interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2.5D/3D package assembly with fine pitch interconnects. Finally, an optimized configuration has been proposed that is expected to be robust with very low chance of failure within the FBEOL region.
{"title":"Stress reduction methods within the Far Back End of Line (FBEOL) for fine pitch and 2.5D/3D packaging configurations","authors":"K. Tunga, T. Wassick, L. Guerin, Maryse Cournoyer","doi":"10.1109/ITHERM.2016.7517526","DOIUrl":"https://doi.org/10.1109/ITHERM.2016.7517526","url":null,"abstract":"Fine pitch interconnects combined with 2.5D/3D packaging technology offers enormous potential towards decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased stresses within the Far Back End of Line (FBEOL) and Back End of Line (BEOL) layers within the chip are the primary concerns. Several 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between -55°C and 125°C. Finite-element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad inter face. Experimental data in conjunction with mechanical modeling was used to determine a safe level of stress at the aluminum interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2.5D/3D package assembly with fine pitch interconnects. Finally, an optimized configuration has been proposed that is expected to be robust with very low chance of failure within the FBEOL region.","PeriodicalId":426908,"journal":{"name":"2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116420328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：