Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530298
Vijayakumar Gali, P. Amrutha
In this paper, a SEPIC converter designed for Photovoltaic water pumping system. This type of model avoids use of extra converter and use of battery which reduces the cost of whole system. The Solar water pumping system has becoming more popular in recent years. Photovoltaic (PV) cell having non linear P-V characteristics, it varies with changing solar radiation. Maximum power point tracking (MPPT) algorithms are used to track the peak power point, which helps to improve the efficiency of the system. The MPPT algorithms are incorporated with DC-DC converter which helps to track the MPP of PV cell. The Advantage of SEPIC converter is reduce the ripple at the output stage and also gives the same polarity as input polarity, which feeds the DC motor, so that the motor runs smoothly without any jerking moments, therefore life the DC motor will be increased. The proposed system is tested with different insolation conditions by changing the solar radiation and observed the DC motor characteristics. The P&O algorithm is used to track the MPP point according to changes in solar insolation and tested using MATLAB SIMULINK model and observed all the results.
{"title":"Fast dynamic response of SEPIC converter based photovoltaic DC motor drive for water pumping system","authors":"Vijayakumar Gali, P. Amrutha","doi":"10.1109/ICCPCT.2016.7530298","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530298","url":null,"abstract":"In this paper, a SEPIC converter designed for Photovoltaic water pumping system. This type of model avoids use of extra converter and use of battery which reduces the cost of whole system. The Solar water pumping system has becoming more popular in recent years. Photovoltaic (PV) cell having non linear P-V characteristics, it varies with changing solar radiation. Maximum power point tracking (MPPT) algorithms are used to track the peak power point, which helps to improve the efficiency of the system. The MPPT algorithms are incorporated with DC-DC converter which helps to track the MPP of PV cell. The Advantage of SEPIC converter is reduce the ripple at the output stage and also gives the same polarity as input polarity, which feeds the DC motor, so that the motor runs smoothly without any jerking moments, therefore life the DC motor will be increased. The proposed system is tested with different insolation conditions by changing the solar radiation and observed the DC motor characteristics. The P&O algorithm is used to track the MPP point according to changes in solar insolation and tested using MATLAB SIMULINK model and observed all the results.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117334499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530134
G. V. Pradeep Kumar, D. K. Reddy
Cognitive Radio is relatively new standard for mobile communication, especially designed to meet the challenges of high spectrum demand for packet data. As spectrum is limited and expensive, unutilized spectrum is an economic constraint for the service provider. Cognitive radio provides a solution for this by providing means of reallocating the unused spectrum to secondary user (SU) when part of spectrum is unused by primary users (PU). Several past works have addressed this issue using various algorithm which ranges from statistical analysis to predictive analysis. In this paper we propose a novel solution for spectrum sensing using frequency domain analysis of the transmitted data. However one of the lesser addressed issues in this direction has been the consideration of PU emulation attack. If a SU has sufficient means of estimating void spectrum, then it can emulate a PU spectrum which then results is low accuracy in void spectrum detection. In this work we primarily focus on frequency domain analysis for void spectrum detection such that free spectrum can be padded up to prevent emulation attacks. We consider a cognitive radio network and adopt BPSK transmission. We assume that the access points are time synchronized and have preliminary knowledge of beginning of a transmission cycle. FFT of signal data in a time slot reveals the energy in the bands. By adaptive thresholding the energy of distinct bands we determine the free spectrum. Further we also demonstrate the means of reallocating this band by injecting secondary user data in the spectrum. We analyze the solution under AWGN channel. Comparison with QR based spectrum sensing technique reveals that the proposed work provides better sensing under high noise by triggering fewer false alarms and through more accurate prediction of the unused spectrum.
{"title":"Frequency domain techniques for void spectrum detection in cognitive radio network for emulation attack prevention","authors":"G. V. Pradeep Kumar, D. K. Reddy","doi":"10.1109/ICCPCT.2016.7530134","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530134","url":null,"abstract":"Cognitive Radio is relatively new standard for mobile communication, especially designed to meet the challenges of high spectrum demand for packet data. As spectrum is limited and expensive, unutilized spectrum is an economic constraint for the service provider. Cognitive radio provides a solution for this by providing means of reallocating the unused spectrum to secondary user (SU) when part of spectrum is unused by primary users (PU). Several past works have addressed this issue using various algorithm which ranges from statistical analysis to predictive analysis. In this paper we propose a novel solution for spectrum sensing using frequency domain analysis of the transmitted data. However one of the lesser addressed issues in this direction has been the consideration of PU emulation attack. If a SU has sufficient means of estimating void spectrum, then it can emulate a PU spectrum which then results is low accuracy in void spectrum detection. In this work we primarily focus on frequency domain analysis for void spectrum detection such that free spectrum can be padded up to prevent emulation attacks. We consider a cognitive radio network and adopt BPSK transmission. We assume that the access points are time synchronized and have preliminary knowledge of beginning of a transmission cycle. FFT of signal data in a time slot reveals the energy in the bands. By adaptive thresholding the energy of distinct bands we determine the free spectrum. Further we also demonstrate the means of reallocating this band by injecting secondary user data in the spectrum. We analyze the solution under AWGN channel. Comparison with QR based spectrum sensing technique reveals that the proposed work provides better sensing under high noise by triggering fewer false alarms and through more accurate prediction of the unused spectrum.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530209
M. Theja, T. Balakumaran
In this paper, hybrid logic style is adopted to design the full adder. The main objective of this design is to achieve Low power and high speed. Hybrid logic style used is the combination of C-CMOS logic (Complementary Metal Oxide Semiconductor) and Transmission gate (TG) logic. The Circuit was implemented using Microwind tool in 90 nm and 180 nm technology. Performance metrics of power and speed are compared with existing adder designs such as conventional CMOS adder, Transmission gate adder (TGA) and Transmission Function adder (TFA). Average Power consumption of the proposed design is found to be 1.114 μW at 90 nm for 1.2 V supply and 5.641 μW at 180 nm for 1.8 V supply. Delay in the signal propagation is measured as 0.011 ns and 0.087 ns for 90 nm and 180 nm technologies respectively. Thus consuming extremely low power and requires less time than existing designs for the same testing environment. Power Delay Product (PDP) is calculated as product of Power and delay values signifies energy requirement of the design. Proposed design requires 71% less energy than TFA and 81% less energy than TGA and 92% less energy than conventional CMOS adder.
{"title":"Energy efficient low power high speed full adder design using hybrid logic","authors":"M. Theja, T. Balakumaran","doi":"10.1109/ICCPCT.2016.7530209","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530209","url":null,"abstract":"In this paper, hybrid logic style is adopted to design the full adder. The main objective of this design is to achieve Low power and high speed. Hybrid logic style used is the combination of C-CMOS logic (Complementary Metal Oxide Semiconductor) and Transmission gate (TG) logic. The Circuit was implemented using Microwind tool in 90 nm and 180 nm technology. Performance metrics of power and speed are compared with existing adder designs such as conventional CMOS adder, Transmission gate adder (TGA) and Transmission Function adder (TFA). Average Power consumption of the proposed design is found to be 1.114 μW at 90 nm for 1.2 V supply and 5.641 μW at 180 nm for 1.8 V supply. Delay in the signal propagation is measured as 0.011 ns and 0.087 ns for 90 nm and 180 nm technologies respectively. Thus consuming extremely low power and requires less time than existing designs for the same testing environment. Power Delay Product (PDP) is calculated as product of Power and delay values signifies energy requirement of the design. Proposed design requires 71% less energy than TFA and 81% less energy than TGA and 92% less energy than conventional CMOS adder.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123275272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530156
D. A. A. G. Singh, A. Fernando, E. Leavline
Software fault detection is the process of analyzing the software for identifying the errors before it is being deployed to the customer. The classifier is employed to perform the software fault detection. Therefore, the accuracy of the software fault detection highly depends on the classifier which is employed in fault detection. Developing the classifier with irrelevant and redundant features of the error-prone data deteriorates the accuracy in software fault detect. Therefore, the feature selection process is employed to remove the redundant and irrelevant features from the error-prone data to improve the accuracy in the software fault detection. Hence, this paper presents an experimental study on the performance of the feature selection methods namely gain ratio (GR), Info gain (IG), OneR, ReliefF, and symmetric uncertainty (SU) to develop the highly accurate classifier for improving the accuracy in software fault detection.
{"title":"Experimental study on feature selection methods for software fault detection","authors":"D. A. A. G. Singh, A. Fernando, E. Leavline","doi":"10.1109/ICCPCT.2016.7530156","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530156","url":null,"abstract":"Software fault detection is the process of analyzing the software for identifying the errors before it is being deployed to the customer. The classifier is employed to perform the software fault detection. Therefore, the accuracy of the software fault detection highly depends on the classifier which is employed in fault detection. Developing the classifier with irrelevant and redundant features of the error-prone data deteriorates the accuracy in software fault detect. Therefore, the feature selection process is employed to remove the redundant and irrelevant features from the error-prone data to improve the accuracy in the software fault detection. Hence, this paper presents an experimental study on the performance of the feature selection methods namely gain ratio (GR), Info gain (IG), OneR, ReliefF, and symmetric uncertainty (SU) to develop the highly accurate classifier for improving the accuracy in software fault detection.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123696082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530133
R. Sakthivel, Vrushali Jalke, Ishita Mishra, Asmita Wachaspati
Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one.
{"title":"A custom reconfigurable power efficient FIR filter","authors":"R. Sakthivel, Vrushali Jalke, Ishita Mishra, Asmita Wachaspati","doi":"10.1109/ICCPCT.2016.7530133","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530133","url":null,"abstract":"Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129761731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530335
A. Nanda, S. Pati, N. Rani
Switched reluctance motor because of its simple construction, robustness and reliability has become superior to other electric machine. This paper presents the speed control of switched reluctance motor (SRM). In this work the performance of the switched reluctance motor is evaluated by subjecting the motor to two different disturbances. First the motor is subjected to a step change in load torque and its performance was evaluated. Again a step change in speed is done to study the system performance. Three different i.e. conventional PI controller, fuzzy PD and fuzzy PID controller are used for the controlled purpose of the switched reluctance motor and their performances are studied and compared in this work. The whole work is done in MATLAB/SIMULINK environment.
{"title":"Performance comparison of a SRM drive with conventional PI, fuzzy PD and fuzzy PID controllers","authors":"A. Nanda, S. Pati, N. Rani","doi":"10.1109/ICCPCT.2016.7530335","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530335","url":null,"abstract":"Switched reluctance motor because of its simple construction, robustness and reliability has become superior to other electric machine. This paper presents the speed control of switched reluctance motor (SRM). In this work the performance of the switched reluctance motor is evaluated by subjecting the motor to two different disturbances. First the motor is subjected to a step change in load torque and its performance was evaluated. Again a step change in speed is done to study the system performance. Three different i.e. conventional PI controller, fuzzy PD and fuzzy PID controller are used for the controlled purpose of the switched reluctance motor and their performances are studied and compared in this work. The whole work is done in MATLAB/SIMULINK environment.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129996100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530275
Vedika Agrawal, Shubham Agrawal, Sayak Nag, D. Chakraborty, B. K. Panigrahi, P. Subbarao
Modern coal fired power plants are required to handle a variety of coal types and accommodate large load changes. Coal mills grind the coal to required fineness and primary air dries and supplies the pulverized fuel to the burners. The dynamic response of coal mills is poor due to simple controls and various faults occurring inside the milling system. In this paper, an approach for time series prediction of n-step ahead values of important variables associated with the milling system is provided. A simple, data driven, non parametric technique i.e. k-NN regression is used for the prediction. The prediction of mill variables is helpful for improving controls and optimizing the mill operation. The proposed approach is applied for 5 minute ahead prediction and validated using the actual data obtained from a coal fired power plant in Gujarat, India.
{"title":"Application of K-NN regression for predicting coal mill related variables","authors":"Vedika Agrawal, Shubham Agrawal, Sayak Nag, D. Chakraborty, B. K. Panigrahi, P. Subbarao","doi":"10.1109/ICCPCT.2016.7530275","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530275","url":null,"abstract":"Modern coal fired power plants are required to handle a variety of coal types and accommodate large load changes. Coal mills grind the coal to required fineness and primary air dries and supplies the pulverized fuel to the burners. The dynamic response of coal mills is poor due to simple controls and various faults occurring inside the milling system. In this paper, an approach for time series prediction of n-step ahead values of important variables associated with the milling system is provided. A simple, data driven, non parametric technique i.e. k-NN regression is used for the prediction. The prediction of mill variables is helpful for improving controls and optimizing the mill operation. The proposed approach is applied for 5 minute ahead prediction and validated using the actual data obtained from a coal fired power plant in Gujarat, India.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129745593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530294
G. Ram, D. S. Rani, Y. R. Lakshmanna, K. B. Sindhuri
This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.
本文介绍了高速吠陀乘法器的设计，该乘法器采用基于16经(算法)的吠陀数学技术来提高性能。本文介绍了吠陀纵向和横向乘法的效率，它不同于正常的乘法过程。Urdhva-Tiryagbhyam是最有效的算法，它为所有类型的数字提供最小的乘法延迟，而不管它们的大小。吠陀乘法器用Verilog HDL编码，在Spartan 3E kit上使用XILINX软件12.2进行仿真合成。并将阵列乘法器的设计与所提出的乘法器在时延、内存和功耗方面进行了比较。
{"title":"Area efficient modified vedic multiplier","authors":"G. Ram, D. S. Rani, Y. R. Lakshmanna, K. B. Sindhuri","doi":"10.1109/ICCPCT.2016.7530294","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530294","url":null,"abstract":"This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130178756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530165
S. Preetha, R. Bhavani, N. Prabha
Power Quality (PQ) is the most significant perspectives at transmission and distribution levels. The supply of high grade electrical services required to the customers illustrates this concept. The voltage sag and swell are the most frequent PQ problems that mainly occur in the distribution systems since it may cause equipment tripping, failure of drive systems, shutdown for domestic and industrial equipment. The Dynamic Voltage Restorer (DVR)connected in series has magnificent dynamic capabilities and is a flexible solution for PQ problems. Ultra-capacitors (UCAP)have ideal characteristics such as high power and low energy density essential for the mitigation of voltage sag and swell. This paper presents an enhanced DVR topology capable of delivering deep, extended mitigation for power quality problems. In the proposed DVR, UCAP is used as energy storage as it provides excessive power in a short interval of time. The DVR is integrated into Ultra-capacitor via bidirectional DC-DC converter which supports in presenting a rigid dc-link voltage, and also helps in compensating temporary voltage sag and voltage swell. PI Controller is used in DVR for power quality enhancement. The simulation model for the proposed system has been developed in MATLAB and the performance over conventional DVR is validated with the results obtained.
{"title":"Design of ultra-capacitor based DVR for power quality improvement","authors":"S. Preetha, R. Bhavani, N. Prabha","doi":"10.1109/ICCPCT.2016.7530165","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530165","url":null,"abstract":"Power Quality (PQ) is the most significant perspectives at transmission and distribution levels. The supply of high grade electrical services required to the customers illustrates this concept. The voltage sag and swell are the most frequent PQ problems that mainly occur in the distribution systems since it may cause equipment tripping, failure of drive systems, shutdown for domestic and industrial equipment. The Dynamic Voltage Restorer (DVR)connected in series has magnificent dynamic capabilities and is a flexible solution for PQ problems. Ultra-capacitors (UCAP)have ideal characteristics such as high power and low energy density essential for the mitigation of voltage sag and swell. This paper presents an enhanced DVR topology capable of delivering deep, extended mitigation for power quality problems. In the proposed DVR, UCAP is used as energy storage as it provides excessive power in a short interval of time. The DVR is integrated into Ultra-capacitor via bidirectional DC-DC converter which supports in presenting a rigid dc-link voltage, and also helps in compensating temporary voltage sag and voltage swell. PI Controller is used in DVR for power quality enhancement. The simulation model for the proposed system has been developed in MATLAB and the performance over conventional DVR is validated with the results obtained.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128813784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530341
Gauri Kalnoor, Jayashree Agarkhed
Wireless Sensor networks (WSN) is basically comprised of sensors that are spatially distributed with self-ruling capability, which monitors physical or environmental conditions such as, pressure, temperature, motion, sound and so on. Sensors also passes all the related information throughout the network. As the number of nodes and size of the network increases, there will be rapid increase in internet traffic. In WSN, security is the major issue and needs to a system that can provide security. Intrusion detection system is the system which plays a vital role in security of a system. One of the major challenges of WSN is to provide consistent Quality of Service (QoS) such as reliability, congestion control, energy efficiency and end-to-end delay, by applying secured routing protocols along with detection of an intruder so that QoS of WSN does not get affected. In our research work, we have discussed different routing protocols that are QoS based, to improve overall performance of the network.
{"title":"QoS based multipath routing for intrusion detection of sinkhole attack in wireless sensor networks","authors":"Gauri Kalnoor, Jayashree Agarkhed","doi":"10.1109/ICCPCT.2016.7530341","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530341","url":null,"abstract":"Wireless Sensor networks (WSN) is basically comprised of sensors that are spatially distributed with self-ruling capability, which monitors physical or environmental conditions such as, pressure, temperature, motion, sound and so on. Sensors also passes all the related information throughout the network. As the number of nodes and size of the network increases, there will be rapid increase in internet traffic. In WSN, security is the major issue and needs to a system that can provide security. Intrusion detection system is the system which plays a vital role in security of a system. One of the major challenges of WSN is to provide consistent Quality of Service (QoS) such as reliability, congestion control, energy efficiency and end-to-end delay, by applying secured routing protocols along with detection of an intruder so that QoS of WSN does not get affected. In our research work, we have discussed different routing protocols that are QoS based, to improve overall performance of the network.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122288452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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