Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530209
M. Theja, T. Balakumaran
In this paper, hybrid logic style is adopted to design the full adder. The main objective of this design is to achieve Low power and high speed. Hybrid logic style used is the combination of C-CMOS logic (Complementary Metal Oxide Semiconductor) and Transmission gate (TG) logic. The Circuit was implemented using Microwind tool in 90 nm and 180 nm technology. Performance metrics of power and speed are compared with existing adder designs such as conventional CMOS adder, Transmission gate adder (TGA) and Transmission Function adder (TFA). Average Power consumption of the proposed design is found to be 1.114 μW at 90 nm for 1.2 V supply and 5.641 μW at 180 nm for 1.8 V supply. Delay in the signal propagation is measured as 0.011 ns and 0.087 ns for 90 nm and 180 nm technologies respectively. Thus consuming extremely low power and requires less time than existing designs for the same testing environment. Power Delay Product (PDP) is calculated as product of Power and delay values signifies energy requirement of the design. Proposed design requires 71% less energy than TFA and 81% less energy than TGA and 92% less energy than conventional CMOS adder.
{"title":"Energy efficient low power high speed full adder design using hybrid logic","authors":"M. Theja, T. Balakumaran","doi":"10.1109/ICCPCT.2016.7530209","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530209","url":null,"abstract":"In this paper, hybrid logic style is adopted to design the full adder. The main objective of this design is to achieve Low power and high speed. Hybrid logic style used is the combination of C-CMOS logic (Complementary Metal Oxide Semiconductor) and Transmission gate (TG) logic. The Circuit was implemented using Microwind tool in 90 nm and 180 nm technology. Performance metrics of power and speed are compared with existing adder designs such as conventional CMOS adder, Transmission gate adder (TGA) and Transmission Function adder (TFA). Average Power consumption of the proposed design is found to be 1.114 μW at 90 nm for 1.2 V supply and 5.641 μW at 180 nm for 1.8 V supply. Delay in the signal propagation is measured as 0.011 ns and 0.087 ns for 90 nm and 180 nm technologies respectively. Thus consuming extremely low power and requires less time than existing designs for the same testing environment. Power Delay Product (PDP) is calculated as product of Power and delay values signifies energy requirement of the design. Proposed design requires 71% less energy than TFA and 81% less energy than TGA and 92% less energy than conventional CMOS adder.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123275272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530343
Aishwarya V, B. Jayanand
This paper presents a method for estimation of the rotor speed and position of a BLDC motor. As BLDC motors are non-linear systems, Extended Kalman Filter (EKF), an advanced version of the Kalman filter has been used for designing the control algorithm for the motor. In the proposed work, the motor state variables are estimated using an Extended Kalman Filter, using the measurements of the stator line voltages and currents alone. The estimated rotor speed has been used for the closed loop speed control of the BLDC motor and the simulation results have been verified.
{"title":"Estimation and control of sensorless brushless DC motor drive using Extended Kalman Filter","authors":"Aishwarya V, B. Jayanand","doi":"10.1109/ICCPCT.2016.7530343","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530343","url":null,"abstract":"This paper presents a method for estimation of the rotor speed and position of a BLDC motor. As BLDC motors are non-linear systems, Extended Kalman Filter (EKF), an advanced version of the Kalman filter has been used for designing the control algorithm for the motor. In the proposed work, the motor state variables are estimated using an Extended Kalman Filter, using the measurements of the stator line voltages and currents alone. The estimated rotor speed has been used for the closed loop speed control of the BLDC motor and the simulation results have been verified.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128157900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530271
G. Ramkumar, S. Vigneshwari, S. Roodyn
Hackers try to induce malicious content on Facebook. The user is unknown about the characteristic of malicious apps which differ expressively from friendly apps with respect to numerous features. Weka tool is a collection of machine learning algorithms for data mining tasks which are used to detect and classify the malicious app on Facebook. App-nets are large groups of securely connected applications which are improved using the widely used algorithms. K-means clustering is one such algorithm which is implemented in Weka tool. Security is a major issue for retrieving the clustered data. There is a need to reduce the risk of hackers on Facebook Application. To develop secured business applications Frappe, is used. Frappe is a web information gathering framework to observe the posting behaviour of Facebook app users. Using Frappe for detecting malicious apps and Weka tool for efficient classification, an efficient framework is developed in the proposed system to identify the mischievous Facebook applications.
{"title":"An enhanced system to identify mischievous social malwares on Facebook applications","authors":"G. Ramkumar, S. Vigneshwari, S. Roodyn","doi":"10.1109/ICCPCT.2016.7530271","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530271","url":null,"abstract":"Hackers try to induce malicious content on Facebook. The user is unknown about the characteristic of malicious apps which differ expressively from friendly apps with respect to numerous features. Weka tool is a collection of machine learning algorithms for data mining tasks which are used to detect and classify the malicious app on Facebook. App-nets are large groups of securely connected applications which are improved using the widely used algorithms. K-means clustering is one such algorithm which is implemented in Weka tool. Security is a major issue for retrieving the clustered data. There is a need to reduce the risk of hackers on Facebook Application. To develop secured business applications Frappe, is used. Frappe is a web information gathering framework to observe the posting behaviour of Facebook app users. Using Frappe for detecting malicious apps and Weka tool for efficient classification, an efficient framework is developed in the proposed system to identify the mischievous Facebook applications.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128390030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530165
S. Preetha, R. Bhavani, N. Prabha
Power Quality (PQ) is the most significant perspectives at transmission and distribution levels. The supply of high grade electrical services required to the customers illustrates this concept. The voltage sag and swell are the most frequent PQ problems that mainly occur in the distribution systems since it may cause equipment tripping, failure of drive systems, shutdown for domestic and industrial equipment. The Dynamic Voltage Restorer (DVR)connected in series has magnificent dynamic capabilities and is a flexible solution for PQ problems. Ultra-capacitors (UCAP)have ideal characteristics such as high power and low energy density essential for the mitigation of voltage sag and swell. This paper presents an enhanced DVR topology capable of delivering deep, extended mitigation for power quality problems. In the proposed DVR, UCAP is used as energy storage as it provides excessive power in a short interval of time. The DVR is integrated into Ultra-capacitor via bidirectional DC-DC converter which supports in presenting a rigid dc-link voltage, and also helps in compensating temporary voltage sag and voltage swell. PI Controller is used in DVR for power quality enhancement. The simulation model for the proposed system has been developed in MATLAB and the performance over conventional DVR is validated with the results obtained.
{"title":"Design of ultra-capacitor based DVR for power quality improvement","authors":"S. Preetha, R. Bhavani, N. Prabha","doi":"10.1109/ICCPCT.2016.7530165","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530165","url":null,"abstract":"Power Quality (PQ) is the most significant perspectives at transmission and distribution levels. The supply of high grade electrical services required to the customers illustrates this concept. The voltage sag and swell are the most frequent PQ problems that mainly occur in the distribution systems since it may cause equipment tripping, failure of drive systems, shutdown for domestic and industrial equipment. The Dynamic Voltage Restorer (DVR)connected in series has magnificent dynamic capabilities and is a flexible solution for PQ problems. Ultra-capacitors (UCAP)have ideal characteristics such as high power and low energy density essential for the mitigation of voltage sag and swell. This paper presents an enhanced DVR topology capable of delivering deep, extended mitigation for power quality problems. In the proposed DVR, UCAP is used as energy storage as it provides excessive power in a short interval of time. The DVR is integrated into Ultra-capacitor via bidirectional DC-DC converter which supports in presenting a rigid dc-link voltage, and also helps in compensating temporary voltage sag and voltage swell. PI Controller is used in DVR for power quality enhancement. The simulation model for the proposed system has been developed in MATLAB and the performance over conventional DVR is validated with the results obtained.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128813784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530133
R. Sakthivel, Vrushali Jalke, Ishita Mishra, Asmita Wachaspati
Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one.
{"title":"A custom reconfigurable power efficient FIR filter","authors":"R. Sakthivel, Vrushali Jalke, Ishita Mishra, Asmita Wachaspati","doi":"10.1109/ICCPCT.2016.7530133","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530133","url":null,"abstract":"Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129761731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530275
Vedika Agrawal, Shubham Agrawal, Sayak Nag, D. Chakraborty, B. K. Panigrahi, P. Subbarao
Modern coal fired power plants are required to handle a variety of coal types and accommodate large load changes. Coal mills grind the coal to required fineness and primary air dries and supplies the pulverized fuel to the burners. The dynamic response of coal mills is poor due to simple controls and various faults occurring inside the milling system. In this paper, an approach for time series prediction of n-step ahead values of important variables associated with the milling system is provided. A simple, data driven, non parametric technique i.e. k-NN regression is used for the prediction. The prediction of mill variables is helpful for improving controls and optimizing the mill operation. The proposed approach is applied for 5 minute ahead prediction and validated using the actual data obtained from a coal fired power plant in Gujarat, India.
{"title":"Application of K-NN regression for predicting coal mill related variables","authors":"Vedika Agrawal, Shubham Agrawal, Sayak Nag, D. Chakraborty, B. K. Panigrahi, P. Subbarao","doi":"10.1109/ICCPCT.2016.7530275","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530275","url":null,"abstract":"Modern coal fired power plants are required to handle a variety of coal types and accommodate large load changes. Coal mills grind the coal to required fineness and primary air dries and supplies the pulverized fuel to the burners. The dynamic response of coal mills is poor due to simple controls and various faults occurring inside the milling system. In this paper, an approach for time series prediction of n-step ahead values of important variables associated with the milling system is provided. A simple, data driven, non parametric technique i.e. k-NN regression is used for the prediction. The prediction of mill variables is helpful for improving controls and optimizing the mill operation. The proposed approach is applied for 5 minute ahead prediction and validated using the actual data obtained from a coal fired power plant in Gujarat, India.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129745593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530294
G. Ram, D. S. Rani, Y. R. Lakshmanna, K. B. Sindhuri
This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.
本文介绍了高速吠陀乘法器的设计，该乘法器采用基于16经(算法)的吠陀数学技术来提高性能。本文介绍了吠陀纵向和横向乘法的效率，它不同于正常的乘法过程。Urdhva-Tiryagbhyam是最有效的算法，它为所有类型的数字提供最小的乘法延迟，而不管它们的大小。吠陀乘法器用Verilog HDL编码，在Spartan 3E kit上使用XILINX软件12.2进行仿真合成。并将阵列乘法器的设计与所提出的乘法器在时延、内存和功耗方面进行了比较。
{"title":"Area efficient modified vedic multiplier","authors":"G. Ram, D. S. Rani, Y. R. Lakshmanna, K. B. Sindhuri","doi":"10.1109/ICCPCT.2016.7530294","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530294","url":null,"abstract":"This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130178756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530309
S. D. Pavithira, N. Prabakaran
Long Term Evolution (LTE) is the individual technologies which supports the selection of increasing file transfer, Internet browsing, Voice over Internet Protocol, Video conferencing. LTE networks have been conceived with very motivated requirements that strongly go beyond facial appearance of 3G systems, so as to preserve several applications, Radio Resource Management (RRM) is the best application to improve the scheme presentation. Packet scheduling mechanisms play an essential role, because they are dependable for choosing with fine time and frequency resolutions. Then, a novel Binary Search Algorithm (BSA) is proposed to increase the efficiency. 4G LTE is the proper technology for reducing data traffic.
{"title":"Downlink packet scheduling mechanism in long term evolution technology","authors":"S. D. Pavithira, N. Prabakaran","doi":"10.1109/ICCPCT.2016.7530309","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530309","url":null,"abstract":"Long Term Evolution (LTE) is the individual technologies which supports the selection of increasing file transfer, Internet browsing, Voice over Internet Protocol, Video conferencing. LTE networks have been conceived with very motivated requirements that strongly go beyond facial appearance of 3G systems, so as to preserve several applications, Radio Resource Management (RRM) is the best application to improve the scheme presentation. Packet scheduling mechanisms play an essential role, because they are dependable for choosing with fine time and frequency resolutions. Then, a novel Binary Search Algorithm (BSA) is proposed to increase the efficiency. 4G LTE is the proper technology for reducing data traffic.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530199
Chandrima Chatterjee
In India, the accreditation process in engineering made the management and performance of learning process should be enforced to achieve standard goals. The part of every engineering profession is the teaching of the basics of the computer science. At the international level, it had been showed that it is almost impossible to satisfying the standard goals. It had been established in a lack of comprehensive maps about scientific concepts. It happens because of getting error in mental model. The results that are based on ideas are definitive. This paper allows concluding that complementing the comprehension of students mental model with a concrete motivation that is based on virtual and actual robots.
{"title":"Use of intelligent systems to teach computer engineering","authors":"Chandrima Chatterjee","doi":"10.1109/ICCPCT.2016.7530199","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530199","url":null,"abstract":"In India, the accreditation process in engineering made the management and performance of learning process should be enforced to achieve standard goals. The part of every engineering profession is the teaching of the basics of the computer science. At the international level, it had been showed that it is almost impossible to satisfying the standard goals. It had been established in a lack of comprehensive maps about scientific concepts. It happens because of getting error in mental model. The results that are based on ideas are definitive. This paper allows concluding that complementing the comprehension of students mental model with a concrete motivation that is based on virtual and actual robots.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127097243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-18DOI: 10.1109/ICCPCT.2016.7530194
R. Ranjani, S. Rajan, R. Vengatesh
This paper investigates the performance analysis of coupled inductor Active Network Converter (ANC) for photovoltaic energy harvesting system. The proposed converter has an integrated with two coupled inductors in a single magnetic core which reduces the size of magnetic components and provides high step-up Voltage gain (Gv) without requiring an extreme Duty ratio (D). The voltage conversion ratio of ANC is high and has low switching losses due to the low voltage and current stress of power switches. The Voltage gain characteristic curve of this converter circuit with different turn's ratio (n) has been studied for various duty cycle. The efficiency of this converter is about to 98.73%. Further, this proposed converter is integrated with the Photovoltaic panel for the harvesting of solar energy. The performance of the solar system for extracting the maximum power depends on the solar irradiance (G), cell temperature (T) and the operating point of MPP (Maximum Power Point) with respect to working conditions. Here, the Incremental Conductance (I&C) algorithm and Fuzzy Logic Control (FLC) method are incorporated for finding the MPP under different operating conditions. The Incremental conductance method overcomes the drawbacks of conventional P&O algorithm. The simulation works have been studied under MATLAB-SIMULINK environment. The effectiveness of the FLC technique adopted in this work for finding MPP has been evaluated and the simulation results are compared with IC method. The simulation results show that the FLC method gives a better improvement in the tracking of MPP than I&C method.
{"title":"Performance analysis of coupled inductor active network converter for photovoltaic energy harvesting system using fuzzy based MPPT control techniques","authors":"R. Ranjani, S. Rajan, R. Vengatesh","doi":"10.1109/ICCPCT.2016.7530194","DOIUrl":"https://doi.org/10.1109/ICCPCT.2016.7530194","url":null,"abstract":"This paper investigates the performance analysis of coupled inductor Active Network Converter (ANC) for photovoltaic energy harvesting system. The proposed converter has an integrated with two coupled inductors in a single magnetic core which reduces the size of magnetic components and provides high step-up Voltage gain (Gv) without requiring an extreme Duty ratio (D). The voltage conversion ratio of ANC is high and has low switching losses due to the low voltage and current stress of power switches. The Voltage gain characteristic curve of this converter circuit with different turn's ratio (n) has been studied for various duty cycle. The efficiency of this converter is about to 98.73%. Further, this proposed converter is integrated with the Photovoltaic panel for the harvesting of solar energy. The performance of the solar system for extracting the maximum power depends on the solar irradiance (G), cell temperature (T) and the operating point of MPP (Maximum Power Point) with respect to working conditions. Here, the Incremental Conductance (I&C) algorithm and Fuzzy Logic Control (FLC) method are incorporated for finding the MPP under different operating conditions. The Incremental conductance method overcomes the drawbacks of conventional P&O algorithm. The simulation works have been studied under MATLAB-SIMULINK environment. The effectiveness of the FLC technique adopted in this work for finding MPP has been evaluated and the simulation results are compared with IC method. The simulation results show that the FLC method gives a better improvement in the tracking of MPP than I&C method.","PeriodicalId":431894,"journal":{"name":"2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127311426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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