Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457242
Ramakrishna Vadlamani, Jia Zhao, W. Burleson, R. Tessier
The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can be an increased processor exposure to soft errors. To address this issue, a flexible fault prevention mechanism has been developed to selectively enable a small amount of per-core dual modular redundancy (DMR) in response to increased vulnerability, as measured by the processor architectural vulnerability factor (AVF). Our new algorithm for DMR deployment aims to provide a stable effective soft error rate (SER) by using DMR in response to DVFS caused by thermal events. The algorithm is implemented in real-time on the multicore using a dedicated monitor network-on-chip and controller which evaluates thermal information and multicore performance statistics. Experiments with a multicore simulator using standard benchmarks show an average 6% improvement in overall power consumption and a stable SER by using selective DMR versus continuous DMR deployment.
{"title":"Multicore soft error rate stabilization using adaptive dual modular redundancy","authors":"Ramakrishna Vadlamani, Jia Zhao, W. Burleson, R. Tessier","doi":"10.1109/DATE.2010.5457242","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457242","url":null,"abstract":"The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can be an increased processor exposure to soft errors. To address this issue, a flexible fault prevention mechanism has been developed to selectively enable a small amount of per-core dual modular redundancy (DMR) in response to increased vulnerability, as measured by the processor architectural vulnerability factor (AVF). Our new algorithm for DMR deployment aims to provide a stable effective soft error rate (SER) by using DMR in response to DVFS caused by thermal events. The algorithm is implemented in real-time on the multicore using a dedicated monitor network-on-chip and controller which evaluates thermal information and multicore performance statistics. Experiments with a multicore simulator using standard benchmarks show an average 6% improvement in overall power consumption and a stable SER by using selective DMR versus continuous DMR deployment.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121415710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5456899
Manfred Dietrich, Uwe Eichler, J. Haase
Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects on power and delay times at chip level is Monte Carlo Simulation, which can be very accurate but time consuming if applied to transistor-level models. We present an alternative approach, namely a statistical gate-level simulation flow, based on parameter sensitivities and a generated VHDL cell model. This solution provides a good speed/accuracy tradeoff by using the event-driven digital simulation domain together with an extended consideration of signal slope times directly in the cell model. The designer gets a fast and accurate overview about the statistical behavior of power consumption and timing of the circuit depending on the manufacturing variations. The paper shortly illustrates the general flow from cell characterization to the model structure and presents first simulation results.
{"title":"Digital statistical analysis using VHDL","authors":"Manfred Dietrich, Uwe Eichler, J. Haase","doi":"10.1109/DATE.2010.5456899","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456899","url":null,"abstract":"Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects on power and delay times at chip level is Monte Carlo Simulation, which can be very accurate but time consuming if applied to transistor-level models. We present an alternative approach, namely a statistical gate-level simulation flow, based on parameter sensitivities and a generated VHDL cell model. This solution provides a good speed/accuracy tradeoff by using the event-driven digital simulation domain together with an extended consideration of signal slope times directly in the cell model. The designer gets a fast and accurate overview about the statistical behavior of power consumption and timing of the circuit depending on the manufacturing variations. The paper shortly illustrates the general flow from cell characterization to the model structure and presents first simulation results.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129357566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457011
Ruirui Gu, A. Forin, Richard Neil Pittman
Hardware acceleration uses hardware to perform some software functions faster than it is possible on a processor. This paper proposes to optimize hardware acceleration using path-based scheduling algorithms derived from dataflow static scheduling, and from control-flow state machines. These techniques are applied to the MIPS-to-Verilog (M2V) compiler, which translates blocks of MIPS machine code into a hardware design represented in Verilog for reconfigurable platforms. The simulation results demonstrate a factor of 22 in performance improvement for simple self-looped basic blocks over the base compiler.
{"title":"Path-based scheduling in a hardware compiler","authors":"Ruirui Gu, A. Forin, Richard Neil Pittman","doi":"10.1109/DATE.2010.5457011","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457011","url":null,"abstract":"Hardware acceleration uses hardware to perform some software functions faster than it is possible on a processor. This paper proposes to optimize hardware acceleration using path-based scheduling algorithms derived from dataflow static scheduling, and from control-flow state machines. These techniques are applied to the MIPS-to-Verilog (M2V) compiler, which translates blocks of MIPS machine code into a hardware design represented in Verilog for reconfigurable platforms. The simulation results demonstrate a factor of 22 in performance improvement for simple self-looped basic blocks over the base compiler.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116976033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communication domain specific processor, and then proposes a novel processor architecture for the next generation wireless communication named GAEA using this design flow. GAEA is a shared memory multi-core SoC based on Software Controlled Time Division Multiplexing Bus, with which programmers can easily explore memory-level parallelism of applications by proper instructions and scheduling algorithms. MPE, which is the kernel component of GAEA, adopts hybrid parallel processing scheme to explore instruction-level and data-level parallelism. The pipeline and instruction set of GAEA are also optimized for the next generation wireless communication systems. The evaluation and implementation results show that GAEA architecture is suitable for the next generation wireless communication systems.
{"title":"Domain specific architecture for next generation wireless communication","authors":"Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo, Ting Chen","doi":"10.1109/DATE.2010.5457034","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457034","url":null,"abstract":"In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communication domain specific processor, and then proposes a novel processor architecture for the next generation wireless communication named GAEA using this design flow. GAEA is a shared memory multi-core SoC based on Software Controlled Time Division Multiplexing Bus, with which programmers can easily explore memory-level parallelism of applications by proper instructions and scheduling algorithms. MPE, which is the kernel component of GAEA, adopts hybrid parallel processing scheme to explore instruction-level and data-level parallelism. The pipeline and instruction set of GAEA are also optimized for the next generation wireless communication systems. The evaluation and implementation results show that GAEA architecture is suitable for the next generation wireless communication systems.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116779808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457150
L. Fanucci, G. Pasetti, P. D'Abramo, R. Serventi, F. Tinfena, P. Chassard, L. Labiste, P. Tisserand
This paper presents an innovative and effective approach to design and test a regulator for an automotive alternator with programmable functionalities. The prototype system consists of two different parts: an integrated circuit (IC) and a FPGA. The IC, implemented in austriamicrosystems HVCMOS 0.35 µm technology, includes all the high voltage parts and a power switch with very low ON resistance. It is able to manage full reverse polarity on every pin, including the reverse battery condition, and over voltages up to 50 V. The programmability is guaranteed through the FPGA. This prototype system can be used to develop a new type of intelligent smart and flexible regulators which implement many additional programmable functions that give the car maker a better control and allow to reduce vehicle fuel consumption and CO2 emissions. In the demonstrator all the implemented functions, including regulation, can be changed during the development phase and many properties, including loop stability, can be checked before releasing a final version of the regulator. The proposed system is also included in a standard brush-holder that can be mounted on Valeo Engine and Electrical System mechatronic alternator and verified directly in a real application.
{"title":"An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability","authors":"L. Fanucci, G. Pasetti, P. D'Abramo, R. Serventi, F. Tinfena, P. Chassard, L. Labiste, P. Tisserand","doi":"10.1109/DATE.2010.5457150","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457150","url":null,"abstract":"This paper presents an innovative and effective approach to design and test a regulator for an automotive alternator with programmable functionalities. The prototype system consists of two different parts: an integrated circuit (IC) and a FPGA. The IC, implemented in austriamicrosystems HVCMOS 0.35 µm technology, includes all the high voltage parts and a power switch with very low ON resistance. It is able to manage full reverse polarity on every pin, including the reverse battery condition, and over voltages up to 50 V. The programmability is guaranteed through the FPGA. This prototype system can be used to develop a new type of intelligent smart and flexible regulators which implement many additional programmable functions that give the car maker a better control and allow to reduce vehicle fuel consumption and CO2 emissions. In the demonstrator all the implemented functions, including regulation, can be changed during the development phase and many properties, including loop stability, can be checked before releasing a final version of the regulator. The proposed system is also included in a standard brush-holder that can be mounted on Valeo Engine and Electrical System mechatronic alternator and verified directly in a real application.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114254344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457151
Wei Gao, R. Hornsey
A new sub-space max-monomial modeling scheme for CMOS transistors in sub-micron technologies is proposed to improve the modeling accuracy. Major electrical parameters of CMOS transistors in each sub-space from the design space are modeled with max-monomials. This approach is demonstrated to have a better accuracy for sub-micron technologies than single-space models. Sub-space modeling based geometric programming power optimization has been successfully applied to three different op-amps in 0.18µm technology. HSPICE simulation results show that sub-space modeling based GP optimization can allow efficient and accurate analog design. Computational effort can be managed to an acceptable level when searching sub-spaces for transistors by using practical constraints. An efficient scheme in dealing with non-convex constraint inherent in Kirchhoff's voltage law is suggested in this paper. By using this scheme, the non-convex constraint, such as posynomial equality, can be relaxed to a convex constraint without affecting the result.
{"title":"A power optimization method for CMOS Op-Amps using sub-space based geometric programming","authors":"Wei Gao, R. Hornsey","doi":"10.1109/DATE.2010.5457151","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457151","url":null,"abstract":"A new sub-space max-monomial modeling scheme for CMOS transistors in sub-micron technologies is proposed to improve the modeling accuracy. Major electrical parameters of CMOS transistors in each sub-space from the design space are modeled with max-monomials. This approach is demonstrated to have a better accuracy for sub-micron technologies than single-space models. Sub-space modeling based geometric programming power optimization has been successfully applied to three different op-amps in 0.18µm technology. HSPICE simulation results show that sub-space modeling based GP optimization can allow efficient and accurate analog design. Computational effort can be managed to an acceptable level when searching sub-spaces for transistors by using practical constraints. An efficient scheme in dealing with non-convex constraint inherent in Kirchhoff's voltage law is suggested in this paper. By using this scheme, the non-convex constraint, such as posynomial equality, can be relaxed to a convex constraint without affecting the result.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114494675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457243
Chuan-Yue Yang, Jian-Jia Chen, L. Thiele, Tei-Wei Kuo
Leakage power consumption contributes significantly to the overall power dissipation for systems that are manufactured in advanced deep sub-micron technology. Different from many previous results, this paper explores leakageaware energy-efficient scheduling if leakage power consumption depends on temperature. We propose a pattern-based approach which divides a given time horizon into several time segments with the same length, where the processor is in the active (dormant, respectively) mode for a fixed amount of time at the beginning (end, respectively) of each time segment. Computation is advanced in the active mode, whereas the dormant mode helps reduce the temperature via cooling as well as the leakage power consumption. Since the pattern-based approach leads to a steady state with an equilibrium temperature, we develop a procedure to find the optimal pattern whose energy consumption in steady state is the minimum. Compared to existing work, our approach is more effective, has less run-time scheduling overhead, and requires only a simple scheduler to control the system mode periodically. The paper contains extensive simulation results which validate the new models and methods.
{"title":"Energy-efficient real-time task scheduling with temperature-dependent leakage","authors":"Chuan-Yue Yang, Jian-Jia Chen, L. Thiele, Tei-Wei Kuo","doi":"10.1109/DATE.2010.5457243","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457243","url":null,"abstract":"Leakage power consumption contributes significantly to the overall power dissipation for systems that are manufactured in advanced deep sub-micron technology. Different from many previous results, this paper explores leakageaware energy-efficient scheduling if leakage power consumption depends on temperature. We propose a pattern-based approach which divides a given time horizon into several time segments with the same length, where the processor is in the active (dormant, respectively) mode for a fixed amount of time at the beginning (end, respectively) of each time segment. Computation is advanced in the active mode, whereas the dormant mode helps reduce the temperature via cooling as well as the leakage power consumption. Since the pattern-based approach leads to a steady state with an equilibrium temperature, we develop a procedure to find the optimal pattern whose energy consumption in steady state is the minimum. Compared to existing work, our approach is more effective, has less run-time scheduling overhead, and requires only a simple scheduler to control the system mode periodically. The paper contains extensive simulation results which validate the new models and methods.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114086582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5456927
A. Canedo, T. Yoshizawa, H. Komatsu
Modern automotive and aerospace embedded applications require very high-performance simulations that are able to produce new values every microsecond. Simulations must now rely on scalable performance of multi-core systems rather than faster clock frequencies. Novel parallelization techniques are needed to satisfy the industrial simulation demands that are essential for the development of safety-critical systems. Simulink formalism is the industrial de facto standard, but current state-of-the-art simulation and code generation techniques fail to fully exploit the parallelism in modern multi-core systems. However, closed-loop and dynamic system simulations are very difficult to parallelize because of the loop-carried dependencies. In this paper we introduce a novel skewed pipelining technique that overcomes these difficulties and allows loop-carried Simulink applications to be executed concurrently in multi-core systems. By delaying the forwarding of values for a few iterations, we can break some data dependencies and coarsen the granularity of programs. This improves the concurrency and reduces the high cost of inter-processor communication. Implementation studies to demonstrate the viability of our method on a commodity multi-core system with 2, 3, and 4 processors show a 1.72, 2.38, and 3.33 fold speedup over uniprocessor execution.
{"title":"Skewed pipelining for parallel simulink simulations","authors":"A. Canedo, T. Yoshizawa, H. Komatsu","doi":"10.1109/DATE.2010.5456927","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456927","url":null,"abstract":"Modern automotive and aerospace embedded applications require very high-performance simulations that are able to produce new values every microsecond. Simulations must now rely on scalable performance of multi-core systems rather than faster clock frequencies. Novel parallelization techniques are needed to satisfy the industrial simulation demands that are essential for the development of safety-critical systems. Simulink formalism is the industrial de facto standard, but current state-of-the-art simulation and code generation techniques fail to fully exploit the parallelism in modern multi-core systems. However, closed-loop and dynamic system simulations are very difficult to parallelize because of the loop-carried dependencies. In this paper we introduce a novel skewed pipelining technique that overcomes these difficulties and allows loop-carried Simulink applications to be executed concurrently in multi-core systems. By delaying the forwarding of values for a few iterations, we can break some data dependencies and coarsen the granularity of programs. This improves the concurrency and reduces the high cost of inter-processor communication. Implementation studies to demonstrate the viability of our method on a commodity multi-core system with 2, 3, and 4 processors show a 1.72, 2.38, and 3.33 fold speedup over uniprocessor execution.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114769037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5456942
V. Aue
LTE is the first cellular communications standard that has been designed from the start for delivering internet content to mobile devices. This will enable a whole new set of applications and devices that are currently beyond our imagination. While new devices will easily consume orders of magnitude more data delivered over the cellular communication pipe than their early 2G counter parts, the challenge for low power consumption remains. LTE not only promises higher data rates, it also offers lower power consumption on a per bit basis than any preceding cellular communications standard thus making it ideal for battery powered data hungry devices.
{"title":"Low power mobile internet devices using LTE technology","authors":"V. Aue","doi":"10.1109/DATE.2010.5456942","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456942","url":null,"abstract":"LTE is the first cellular communications standard that has been designed from the start for delivering internet content to mobile devices. This will enable a whole new set of applications and devices that are currently beyond our imagination. While new devices will easily consume orders of magnitude more data delivered over the cellular communication pipe than their early 2G counter parts, the challenge for low power consumption remains. LTE not only promises higher data rates, it also offers lower power consumption on a per bit basis than any preceding cellular communications standard thus making it ideal for battery powered data hungry devices.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125377269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457127
Wei Liu, A. Nannarelli, A. Calimera, E. Macii, M. Poncino
With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.
{"title":"Post-placement temperature reduction techniques","authors":"Wei Liu, A. Nannarelli, A. Calimera, E. Macii, M. Poncino","doi":"10.1109/DATE.2010.5457127","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457127","url":null,"abstract":"With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122008160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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