Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480496
Yu-Sheng Chen, Heng-Yuan Lee, Pang-Shiu Chen, Y. D. Lin, K. Tsai, C. Hsu, W. Chen, M. Tsai, T. Ku, P. H. Wang
A Ta ultra-thin metal layer was treated by O2 plasma at low temperature to form TaOx, which severs as a resistive element or internal resistor. The low current operated Ta/TaOx/HfOx and Ta/TaOx/AlOx devices exhibit self-compliance, good LRS nonlinearity (>40), robust retention at 85 °C, and enough endurance (>1000). A plausible mechanism is proposed. The low temperature plasma oxidation of Ta layer is demonstrated an potential process for vertical RRAM with self-compliance and low current operation of 5 μA.
{"title":"Low power/self-compliance of resistive switching elements modified with a conduction Ta-oxide layer through low temperature plasma oxidization of Ta thin film","authors":"Yu-Sheng Chen, Heng-Yuan Lee, Pang-Shiu Chen, Y. D. Lin, K. Tsai, C. Hsu, W. Chen, M. Tsai, T. Ku, P. H. Wang","doi":"10.1109/VLSI-TSA.2016.7480496","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480496","url":null,"abstract":"A Ta ultra-thin metal layer was treated by O2 plasma at low temperature to form TaOx, which severs as a resistive element or internal resistor. The low current operated Ta/TaOx/HfOx and Ta/TaOx/AlOx devices exhibit self-compliance, good LRS nonlinearity (>40), robust retention at 85 °C, and enough endurance (>1000). A plausible mechanism is proposed. The low temperature plasma oxidation of Ta layer is demonstrated an potential process for vertical RRAM with self-compliance and low current operation of 5 μA.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121686164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480484
Simone Cortese, Maria Trapatseli, A. Khiat, T. Prodromakis
ReRAM crossbar arrays are known to be susceptible to the presence of the sneak current issue during the readout operations which undermines crossbar scaling. This problem can be solved by the addition of an highly non-linear two-terminal selector device. In this work we present a 5 nm thick TiO2-based selector which exploits a volatile threshold resistive switching, so far unreported for this material. The device shows a current density up to 100 kA/cm2, 107 current non-linearity and a 4 V voltage margin, the highest reported for TiO2-based selectors and sub 100 pA off current.
{"title":"A TiO2-based volatile threshold switching selector device with 107 non linearity and sub 100 pA Off current","authors":"Simone Cortese, Maria Trapatseli, A. Khiat, T. Prodromakis","doi":"10.1109/VLSI-TSA.2016.7480484","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480484","url":null,"abstract":"ReRAM crossbar arrays are known to be susceptible to the presence of the sneak current issue during the readout operations which undermines crossbar scaling. This problem can be solved by the addition of an highly non-linear two-terminal selector device. In this work we present a 5 nm thick TiO2-based selector which exploits a volatile threshold resistive switching, so far unreported for this material. The device shows a current density up to 100 kA/cm2, 107 current non-linearity and a 4 V voltage margin, the highest reported for TiO2-based selectors and sub 100 pA off current.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127081329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480516
S. Di, K. Zhao, Zhiyuan Lun Tiao Lu, G. Du, Xiaoyan Liu
A nano-scale double gate In0.53Ga0.47As nMOSFET device structure is simulated by deterministically solving the time dependent Boltzmann Transport Equation (BTE). The results show that the contribution of the L valleys cannot be ignored even if the energy gap between r and L valleys are very large. Moreover, the quasi-ballistic transport is observed despite the existence of scattering.
{"title":"Simulation of nano-scale double gate In0.53Ga0.47As nMOSFETs by a deterministic BTE solver","authors":"S. Di, K. Zhao, Zhiyuan Lun Tiao Lu, G. Du, Xiaoyan Liu","doi":"10.1109/VLSI-TSA.2016.7480516","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480516","url":null,"abstract":"A nano-scale double gate In0.53Ga0.47As nMOSFET device structure is simulated by deterministically solving the time dependent Boltzmann Transport Equation (BTE). The results show that the contribution of the L valleys cannot be ignored even if the energy gap between r and L valleys are very large. Moreover, the quasi-ballistic transport is observed despite the existence of scattering.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132840274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480486
E. Hsieh, C. Chuang, S. Chung
For the first time, a new 1T1R of volatile memory based on the interfacial dipole flipping mechanism, named as Dipole Dynamic Random Access Memory (DiRAM), has been reported. It features 4ns per bit of dipole switching time, larger than 109 of endurance, and 10 seconds of retention with reasonable positive and negative resistance window, low operation voltages with bit line at 0.8V and word line at 0.2V, and around 1 nano-Watt per bit of operation power. DiRAM is also easy to be integrated with state-of-the-art CMOS technology. The results have shown that this volatile memory may be a potential candidate for the next generation DRAM technology.
{"title":"An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring high speed, ultra-low power, and low voltage operation","authors":"E. Hsieh, C. Chuang, S. Chung","doi":"10.1109/VLSI-TSA.2016.7480486","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480486","url":null,"abstract":"For the first time, a new 1T1R of volatile memory based on the interfacial dipole flipping mechanism, named as Dipole Dynamic Random Access Memory (DiRAM), has been reported. It features 4ns per bit of dipole switching time, larger than 109 of endurance, and 10 seconds of retention with reasonable positive and negative resistance window, low operation voltages with bit line at 0.8V and word line at 0.2V, and around 1 nano-Watt per bit of operation power. DiRAM is also easy to be integrated with state-of-the-art CMOS technology. The results have shown that this volatile memory may be a potential candidate for the next generation DRAM technology.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132903814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480511
S. Fathipour, Hua-Min Li, M. Remškar, L. Yeh, W. Tsai, Yu-Ming Lin, S. Fullerton‐Shirey, A. Seabaugh
Record high current density of 300 μA/μm with low contact resistance of 200 Ω μm and a channel length of 0.8 μm at a drain-source bias of 1.6 V has been achieved for the first time in MoS2 field-effect transistors (FETs) grown by chemical vapor transport. The low contact resistance is achieved using a polyethylene-oxide cesium-perchlorate solid polymer ion conductor formed by drop casting. The charged ions are placed into position over the channel by the application of a bias to a side gate and then locked into place by lowering the temperature. A weak temperature dependence of the drain current after ion doping indicates that transport in the Schottky contacts is dominated by tunneling.
{"title":"Record high current density and low contact resistance in MoS2 FETs by ion doping","authors":"S. Fathipour, Hua-Min Li, M. Remškar, L. Yeh, W. Tsai, Yu-Ming Lin, S. Fullerton‐Shirey, A. Seabaugh","doi":"10.1109/VLSI-TSA.2016.7480511","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480511","url":null,"abstract":"Record high current density of 300 μA/μm with low contact resistance of 200 Ω μm and a channel length of 0.8 μm at a drain-source bias of 1.6 V has been achieved for the first time in MoS2 field-effect transistors (FETs) grown by chemical vapor transport. The low contact resistance is achieved using a polyethylene-oxide cesium-perchlorate solid polymer ion conductor formed by drop casting. The charged ions are placed into position over the channel by the application of a bias to a side gate and then locked into place by lowering the temperature. A weak temperature dependence of the drain current after ion doping indicates that transport in the Schottky contacts is dominated by tunneling.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480517
Y.-S Wu, C. Tsai, T. Miyashita, P.N. Chen, B. Hsu, P. Wu, H. Hsu, C. Chiang, H.H. Liu, H.-L. Yang, K. Kwong, Juei-Chun Chiang, C.-W Lee, Y.-J Lin, C.-A Lu, C. Lin, S. Wu
A comprehensive analysis of fin profile effect on bulk FinFET device characteristics is described in this paper. Optimal fin profile and anti-punch-through (APT) implant profile are important to DC performance and multiple-Vt offering capability, which are essential for system-on-chip (SoC) applications. This study provides practical device design guidelines for bulk FinFET technology.
{"title":"Optimization of fin profile and implant in bulk FinFET technology","authors":"Y.-S Wu, C. Tsai, T. Miyashita, P.N. Chen, B. Hsu, P. Wu, H. Hsu, C. Chiang, H.H. Liu, H.-L. Yang, K. Kwong, Juei-Chun Chiang, C.-W Lee, Y.-J Lin, C.-A Lu, C. Lin, S. Wu","doi":"10.1109/VLSI-TSA.2016.7480517","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480517","url":null,"abstract":"A comprehensive analysis of fin profile effect on bulk FinFET device characteristics is described in this paper. Optimal fin profile and anti-punch-through (APT) implant profile are important to DC performance and multiple-Vt offering capability, which are essential for system-on-chip (SoC) applications. This study provides practical device design guidelines for bulk FinFET technology.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133165006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work reports the first experimental submicron and sub-100 nm ZnON TFTs with excellent performance. Field-effect mobility values as high as 55 and 9.2 cm2/V-s were measured from ZnON TFTs with channel lengths of 0.5 μm and 75 nm, respectively. Those are the highest values ever reported on oxide-semiconductor TFTs of comparable channel length. The results confirm ZnON TFTs as an effective building block for the construction of BEOL circuits integrated in a chip.
{"title":"Short-channel BEOL ZnON thin-film transistors with superior mobility performance","authors":"Chin-I Kuan, Horng-Chih Lin, Pei-Wen Li, Tiao-Yuan Huang","doi":"10.1109/VLSI-TSA.2016.7480533","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480533","url":null,"abstract":"This work reports the first experimental submicron and sub-100 nm ZnON TFTs with excellent performance. Field-effect mobility values as high as 55 and 9.2 cm2/V-s were measured from ZnON TFTs with channel lengths of 0.5 μm and 75 nm, respectively. Those are the highest values ever reported on oxide-semiconductor TFTs of comparable channel length. The results confirm ZnON TFTs as an effective building block for the construction of BEOL circuits integrated in a chip.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131811372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480529
L. Larcher, G. Sereni, A. Padovani, L. Vandelli
The semiconductor technology development requires a full understanding of material implications at the device level. This requires connecting the microscopic/atomic properties of the material (e.g. defect) to the macroscopic electrical characteristics of the device. In this scenario, we developed a new methodology, supported by a multi-scale modeling and simulation (MS) software [1], [2], which allows extracting from the simulations of the electrical characterization measurements (I-V, C-V, G-V, BTI, Charge-Pumping, noise, stress) the material and device properties that can be used for the technology development, the design of novel devices and the analysis of the device reliability also at statistical level (TDDB, leakage currents), Fig. 1.
{"title":"Electrical defect spectroscopy and reliability prediction through a novel simulation-based methodology","authors":"L. Larcher, G. Sereni, A. Padovani, L. Vandelli","doi":"10.1109/VLSI-TSA.2016.7480529","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480529","url":null,"abstract":"The semiconductor technology development requires a full understanding of material implications at the device level. This requires connecting the microscopic/atomic properties of the material (e.g. defect) to the macroscopic electrical characteristics of the device. In this scenario, we developed a new methodology, supported by a multi-scale modeling and simulation (MS) software [1], [2], which allows extracting from the simulations of the electrical characterization measurements (I-V, C-V, G-V, BTI, Charge-Pumping, noise, stress) the material and device properties that can be used for the technology development, the design of novel devices and the analysis of the device reliability also at statistical level (TDDB, leakage currents), Fig. 1.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124394518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480536
Ta-Chun Lin, Y. Sun, Ming-Huei Lin, Tomonari Yamamoto, Shyh-Horng Yang
We demonstrated a strain boost technique tailored for 3-Dimensional (3-D) structure on pFinFETs so the longitudinal stress can be locally maximized in the fin. The resulting effective mobility (μeff) improvement by this technique was effectively transferred to the enhancement of the injection velocity (Uinj). The saturation drain current (Idsat) and the ring oscillator speed under the same electrostatics were hence improved by 5% and 3% at Vdd=0.8V, respectively. Moreover, the electrical characteristics at the varied Vdd and temperatures, the fin number dependence, and the local variability were also systematically discussed in this paper.
{"title":"Experimental demonstration of performance improvement with a strain boost technique tailored for 3-Dimensional structure on nano-scaled bulk pFinFETs","authors":"Ta-Chun Lin, Y. Sun, Ming-Huei Lin, Tomonari Yamamoto, Shyh-Horng Yang","doi":"10.1109/VLSI-TSA.2016.7480536","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480536","url":null,"abstract":"We demonstrated a strain boost technique tailored for 3-Dimensional (3-D) structure on pFinFETs so the longitudinal stress can be locally maximized in the fin. The resulting effective mobility (μeff) improvement by this technique was effectively transferred to the enhancement of the injection velocity (Uinj). The saturation drain current (Idsat) and the ring oscillator speed under the same electrostatics were hence improved by 5% and 3% at Vdd=0.8V, respectively. Moreover, the electrical characteristics at the varied Vdd and temperatures, the fin number dependence, and the local variability were also systematically discussed in this paper.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123169968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480512
M. Ichihashi, Y. Woo, S. Parihar
This paper describes the performance analysis of SRAM cell capability beyond 10-nm FinFET technology. Through the circuit simulation with a pseudo memory macro, optimized SRAM cell can demonstrate almost the same performance of traditional metal architecture though the read-out delay analysis. Comparing between HD (High-Density) and HC (High-Current) cell, HD cell shows better performance in the large array macro due to the less parasitic resistance and capacitance.
{"title":"SRAM cell performance analysis beyond 10-nm FinFET technology","authors":"M. Ichihashi, Y. Woo, S. Parihar","doi":"10.1109/VLSI-TSA.2016.7480512","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480512","url":null,"abstract":"This paper describes the performance analysis of SRAM cell capability beyond 10-nm FinFET technology. Through the circuit simulation with a pseudo memory macro, optimized SRAM cell can demonstrate almost the same performance of traditional metal architecture though the read-out delay analysis. Comparing between HD (High-Density) and HC (High-Current) cell, HD cell shows better performance in the large array macro due to the less parasitic resistance and capacitance.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133612589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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