Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480502
Weijie Wang, Hongxin Yang, V. Y. Zhuo, Minghua Li, E. Chua, Yu Jiang
Of all the advantages exhibited by the RRAM devices, e.g. low power consumption, fast switching speed, and especially the good scalability are particularly striking for high density memory application. However, 3D RRAM still suffer from poor endurance especially during high speed operation which limits its extensive applications. Here, we report the transient control method which enables a significant improvement of device stability and endurance. We demonstrated the stable transient control under the fast pulse switching in RRAM cells with different sizes of 1 μm and 200 nm. Endurance higher than 107 cycles are achieved while keeping the ratio of high/low resistance level at 103. High speed switching with 1 ns pulse width can be achieved. We unveil the material switching dynamics responsible for the stable transient process, which is responsible for the higher endurance for RRAM devices.
{"title":"Transient control of resistive random access memory for high speed and high endurance performance","authors":"Weijie Wang, Hongxin Yang, V. Y. Zhuo, Minghua Li, E. Chua, Yu Jiang","doi":"10.1109/VLSI-TSA.2016.7480502","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480502","url":null,"abstract":"Of all the advantages exhibited by the RRAM devices, e.g. low power consumption, fast switching speed, and especially the good scalability are particularly striking for high density memory application. However, 3D RRAM still suffer from poor endurance especially during high speed operation which limits its extensive applications. Here, we report the transient control method which enables a significant improvement of device stability and endurance. We demonstrated the stable transient control under the fast pulse switching in RRAM cells with different sizes of 1 μm and 200 nm. Endurance higher than 107 cycles are achieved while keeping the ratio of high/low resistance level at 103. High speed switching with 1 ns pulse width can be achieved. We unveil the material switching dynamics responsible for the stable transient process, which is responsible for the higher endurance for RRAM devices.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114379776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480495
S. Z. Rahaman, Yu-De Lin, P. Gu, Heng-Yuan Lee, Yu-Sheng Chen, Pang-Shiu Chen, K. Tsai, Weisu Chen, Chien-Hua Hsu, Po-tsung Tu, Frederick T. Chen, M. Tsai, T. Ku, Pei-Hua Wang
This paper investigates the Ti thickness modulation based simple strategy to regulate the oxygen vacancy concentration in the HfOx film and implemented to realize the resistive switching properties. Accordingly, we demonstrated a way to control the forming voltage, decrease the operation current to sub-μA level, controllable BRS/CRS and to bypass the self-CRS phenomena in Ti/HfOx based 1T1R RRAM devices for future memory applications.
{"title":"Effect of Ti buffer layer on HfOx-based bipolar and complementary resistive switching for future memory applications","authors":"S. Z. Rahaman, Yu-De Lin, P. Gu, Heng-Yuan Lee, Yu-Sheng Chen, Pang-Shiu Chen, K. Tsai, Weisu Chen, Chien-Hua Hsu, Po-tsung Tu, Frederick T. Chen, M. Tsai, T. Ku, Pei-Hua Wang","doi":"10.1109/VLSI-TSA.2016.7480495","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480495","url":null,"abstract":"This paper investigates the Ti thickness modulation based simple strategy to regulate the oxygen vacancy concentration in the HfOx film and implemented to realize the resistive switching properties. Accordingly, we demonstrated a way to control the forming voltage, decrease the operation current to sub-μA level, controllable BRS/CRS and to bypass the self-CRS phenomena in Ti/HfOx based 1T1R RRAM devices for future memory applications.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121406134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480489
Shih-Wei Lee, Shu-Chiao Kuo, Kuan-Neng Chen
A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated.
{"title":"Electrical testing structure for stacking error measurement in 3D integration","authors":"Shih-Wei Lee, Shu-Chiao Kuo, Kuan-Neng Chen","doi":"10.1109/VLSI-TSA.2016.7480489","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480489","url":null,"abstract":"A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124194434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480510
Chang-Hung Yu, P. Su, C. Chuang
Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.
{"title":"Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits","authors":"Chang-Hung Yu, P. Su, C. Chuang","doi":"10.1109/VLSI-TSA.2016.7480510","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480510","url":null,"abstract":"Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121702265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480526
S.-H. Huang, Fang-Liang Lu, C. W. Liu
The electron concentration of 3×1020 cm-3 in phosphorus-doped Ge is obtained by in-situ chemical vapor deposition doping and laser annealing. The laser annealing effectively improve the crystallinity in the Ge layer. The pulse laser not only activates the phosphorus, but also produces the biaxial tensile strain. With the nickel germanide contact, the contact resistivity is as low as 1.5×10-8 Ω-cm2 by greatly reducing the tunneling distance. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with on/off ratio of ~1×105.
{"title":"Low contact resistivity (1.5×10−8 Ω-cm2) of phosphorus-doped Ge by in-situ chemical vapor deposition doping and laser annealing","authors":"S.-H. Huang, Fang-Liang Lu, C. W. Liu","doi":"10.1109/VLSI-TSA.2016.7480526","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480526","url":null,"abstract":"The electron concentration of 3×10<sup>20</sup> cm<sup>-3</sup> in phosphorus-doped Ge is obtained by in-situ chemical vapor deposition doping and laser annealing. The laser annealing effectively improve the crystallinity in the Ge layer. The pulse laser not only activates the phosphorus, but also produces the biaxial tensile strain. With the nickel germanide contact, the contact resistivity is as low as 1.5×10<sup>-8</sup> Ω-cm<sup>2</sup> by greatly reducing the tunneling distance. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with on/off ratio of ~1×10<sup>5</sup>.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120946137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480535
Z. Ling, K. Majumdar, S. Sakar, S. Mathew, Juntao Zhu, K. Gopinadhan, T. Venkatesan, K. Ang
We demonstrate a new contact technology for realizing a near band edge contact Schottky barrier height (ΦB) in black phosphorus (BP) p-channel transistors. This is achieved via the use of high work function nickel (Ni) and thermal anneal to produce a novel nickel-phosphide (Ni2P) alloy which enables a record low hole ΦB of ~12 meV. The formation of reactive Ni2P/BP contact was found to further improve the transmission probability as compared to the Ni/BP contact. Moreover, the penetration of Ni2P in the source and drain regions could additionally reduce the parasitic series resistance, leading to drive current improvement.
{"title":"Nickel-phosphide contact for effective Schottky barrier modulation in black phosphorus p-channel transistors","authors":"Z. Ling, K. Majumdar, S. Sakar, S. Mathew, Juntao Zhu, K. Gopinadhan, T. Venkatesan, K. Ang","doi":"10.1109/VLSI-TSA.2016.7480535","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480535","url":null,"abstract":"We demonstrate a new contact technology for realizing a near band edge contact Schottky barrier height (ΦB) in black phosphorus (BP) p-channel transistors. This is achieved via the use of high work function nickel (Ni) and thermal anneal to produce a novel nickel-phosphide (Ni2P) alloy which enables a record low hole ΦB of ~12 meV. The formation of reactive Ni2P/BP contact was found to further improve the transmission probability as compared to the Ni/BP contact. Moreover, the penetration of Ni2P in the source and drain regions could additionally reduce the parasitic series resistance, leading to drive current improvement.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127063430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480518
H. Lue, C. Chiu, Chih-Yuan Lu
We have developed a novel single-gate vertical channel (SGVC) 3D NAND Flash architecture. The device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. The ultra-thin body TFT device enables tight initial Vt distribution as well as excellent short-channel effect that is comparable to and sometimes superior than the more prevailing gate-all-around (GAA) macaroni devices of other 3D NAND architectures. Unlike GAA device for which the electric field is a function of channel hole curvature, the flat cell is insensitive to etching CD, thus SGVC device is very tolerable to the non-ideal vertical etching and has shown superb layer-to-layer device uniformity. Even without help from curvature (like in GAA) our SGVC flat cell achieves excellent P/E window of >10V with only modest interferences that can support TLC (3 logic bits per cell) operation. Owing to the double-density in a single WL trench and much more efficient array design with minimal overhead, SGVC architecture offers 2 to 4 times memory density than GAA VC 3D NAND at the same stack layer number.
我们开发了一种新颖的单栅垂直通道(SGVC) 3D NAND闪存架构。该器件是一种超薄机身的单栅极、平面通道TFT电荷捕获器件。超薄体TFT器件可实现紧凑的初始Vt分布以及出色的短通道效应，可与其他3D NAND架构中更流行的栅极全方位(GAA)通心粉器件相媲美，有时甚至优于后者。与电场是通道孔曲率的函数的GAA器件不同，平面电池对蚀刻CD不敏感，因此SGVC器件对非理想的垂直蚀刻非常耐受，并表现出优异的器件层间均匀性。即使没有曲率的帮助(如在GAA中)，我们的SGVC平面单元也可以实现>10V的优秀P/E窗口，只有适度的干扰，可以支持TLC(每个单元3个逻辑位)操作。由于单WL沟槽的双密度和更高效的阵列设计和最小的开销，在相同的堆栈层数下，SGVC架构提供的存储密度是GAA VC 3D NAND的2到4倍。
{"title":"A novel double-density single-gate vertical-channel (SGVC) 3D NAND flash featuring a flat-channel device with excellent layer uniformity","authors":"H. Lue, C. Chiu, Chih-Yuan Lu","doi":"10.1109/VLSI-TSA.2016.7480518","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480518","url":null,"abstract":"We have developed a novel single-gate vertical channel (SGVC) 3D NAND Flash architecture. The device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. The ultra-thin body TFT device enables tight initial Vt distribution as well as excellent short-channel effect that is comparable to and sometimes superior than the more prevailing gate-all-around (GAA) macaroni devices of other 3D NAND architectures. Unlike GAA device for which the electric field is a function of channel hole curvature, the flat cell is insensitive to etching CD, thus SGVC device is very tolerable to the non-ideal vertical etching and has shown superb layer-to-layer device uniformity. Even without help from curvature (like in GAA) our SGVC flat cell achieves excellent P/E window of >10V with only modest interferences that can support TLC (3 logic bits per cell) operation. Owing to the double-density in a single WL trench and much more efficient array design with minimal overhead, SGVC architecture offers 2 to 4 times memory density than GAA VC 3D NAND at the same stack layer number.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133447661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480485
P. Cheng, Chihching Yang, Meng-Yin Hsu, C. Lin, Y. King
This work presents a novel embedded Analog Gateless One-Time-Programming Memory (AG-OTP), implemented by standard CMOS logic process. The NVM cell includes a gateless storage node in series with a select transistor; where the charge stored on the parasitic ONO structure. The p-channel device is programmed by channel hot hole induced hot electron injection (CHHIHE). An angled-shaped source region allows the gateless channel to be partially turned-on and gradually increase the read current level. This unique structure enable the storage of analog data as continuous read current can be readily achieved.
{"title":"Variable-length gateless transistor for analog one-time-programmable memory applications","authors":"P. Cheng, Chihching Yang, Meng-Yin Hsu, C. Lin, Y. King","doi":"10.1109/VLSI-TSA.2016.7480485","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480485","url":null,"abstract":"This work presents a novel embedded Analog Gateless One-Time-Programming Memory (AG-OTP), implemented by standard CMOS logic process. The NVM cell includes a gateless storage node in series with a select transistor; where the charge stored on the parasitic ONO structure. The p-channel device is programmed by channel hot hole induced hot electron injection (CHHIHE). An angled-shaped source region allows the gateless channel to be partially turned-on and gradually increase the read current level. This unique structure enable the storage of analog data as continuous read current can be readily achieved.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133158435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480531
C. Ni, Y. Huang, S. Jun, S. Sun, A. Vyas, F. Khaja, K. V. Rao, S. Sharma, N. Breil, M. Jin, C. Lazik, A. Mayur, J. Gelatos, H. Chung, R. Hung, M. Chudzik, N. Yoshida, N. Kim
We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.
{"title":"PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond","authors":"C. Ni, Y. Huang, S. Jun, S. Sun, A. Vyas, F. Khaja, K. V. Rao, S. Sharma, N. Breil, M. Jin, C. Lazik, A. Mayur, J. Gelatos, H. Chung, R. Hung, M. Chudzik, N. Yoshida, N. Kim","doi":"10.1109/VLSI-TSA.2016.7480531","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480531","url":null,"abstract":"We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124429391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480500
C. Y. Chen, L. Goux, A. Fantini, A. Redolfi, G. Groeseneken, M. Jurczak
We explain in detail how to optimize the oxygen chemical potential profile of Ta2O5-based stack to improve switching speed at reduced operating current (<;10μA). Using industry-relevant programming scheme, we demonstrate an oxide-based RRAM stack giving large on/off ratio (~x200) while the good reliability properties are preserved.
{"title":"Oxygen chemical potential profile optimization for fast low current (<10μA) resistive switching in oxide-based RRAM","authors":"C. Y. Chen, L. Goux, A. Fantini, A. Redolfi, G. Groeseneken, M. Jurczak","doi":"10.1109/VLSI-TSA.2016.7480500","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480500","url":null,"abstract":"We explain in detail how to optimize the oxygen chemical potential profile of Ta2O5-based stack to improve switching speed at reduced operating current (<;10μA). Using industry-relevant programming scheme, we demonstrate an oxide-based RRAM stack giving large on/off ratio (~x200) while the good reliability properties are preserved.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116143763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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